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Session 1: Introduction & Development Pipeline

Session summary: What we learned

This session covered the basics of what a chip is and how it’s built, then walked through the standard chip design pipeline. We learned how the course toolchain runs inside a container (hosted or local Docker), how to run example simulations and view .vcd waveforms in GTKWave, and why PDKs matter because they provide the manufacturing rules and models. We also touched on low-cost tapeout options and using Git to track and manage hardware design files.

Homework Given

  • Install the course toolchain (Docker container)
  • Run a "hello world" synthesis
  • Verify your tools work before Thursday!

What I did (quick summary)

I set up the environment and successfully ran a simulation inside the provided toolchain. I used the hosted environment (Option A) and connected to the running container using a VNC client.

Environment Setup (Option A: Hosted Container)

Tool portal Used

I used the hosted microservices environment here:

From there, I started a container for the course toolchain.

Initially I opened the browser VNC viewer to check how it works before I decided to use a local VNC client.

Local VNC Client

To access the container GUI, I decided I would use a local vnc client since I have already used it before and I decided to go with RealVNC Viewer. However there was quite a delay and lagging, so decided to go with tiger VNC as recommended.

I opened a terminal and went into the examples folder:

cd /foss/example

Running Simulation

I ran the sample simulation workflow from the examples directory. Since there was multiple examples, I tried simulating the fortune teller first followed by the other examples.

make sim-fortune

Waveform

After the simulation to view its wave form, I used the command 

gtkwave fortune_teller/fortune_teller_tb.vcd

which didn't work and I tried "gtkwave fortune_teller.vcd" which worked for me. Then once I got inot the gtkwave viewer, I appended the signals from the sst and zoomed in to view the wave form

I was able to observe the following: The waveform shows how the system behaved over time in response to simulated inputs. The clock (clk) is running continuously which I was only able to see once I zoomed in further

The reset (rst_n) is high, meaning the system is active. When the button signal (btn) goes high, it triggers the internal logic, causing registers like i to update (which is why you see it change from unknown X to a defined value).

The testbench also feeds in a byte (rx_byte = 0A). When we zoom in to the waveform, we are able to see the ASCll bytes being processed. The values are in hex but the output can be changed to view in ASCII and we are able to see cannot predict, which we were able to observe in the simulation.

The design transmits data through the tx line using UART protocol and the small dips in the tx signal represent serial transmission bits being sent over time.

Overall, the waveform confirms that the design is functioning correctly: inputs change, internal logic reacts, and outputs are generated as expected.

Other things I did

  • Did simulation of other examples

What more to do?

  • Observe their waveforms and understand
  • Try modifying one of the examples after I explore and understand more

The hello-world synthesis

I wanted to see how the hello world example would work to understand how to write my first verilog code.

I didn't go indepth about verilog but based on some websites that I looked into I understand and looking into the simulation files in the example:

module myCircuit (input a, b, output y);
// logic here
endmodule

I looked into this website: - Chip Verify - Based on their explaination, we want the ' Hello World' to be displayed when simulating, also since it doesnt have any inputs or output we write it as a test bench module.

When I looked into the fortune teller test bench file, there was definition on testbench and how to run it.

I was able to understand it was verilog module that is used to test another module and they are not syenthesizable and only run in simulation.

So for this the hello world file looks as follows:

module tb;
  initial begin
    $display("Hello World!");
    $finish;
  end
endmodule

I followed the direction from the fortune teller testbench on how to run this and got the hello world output.

There is still a lot to explore and understand about verilog