Session 2: Analog Basics¶

Session summary: What we learned¶

In this lesson, I learned that electronics is essentially about controlling the flow of electrons using voltage to create current, similar to water moving through pipes . We explored passive components like resistors, capacitors, and inductors and how they affect signal speed and power, then moved on to transistors, which act as switches that turn electron flow on and off. I understood how high and low voltages represent “1” and “0,” and how NMOS and PMOS transistors combine to form logic gates like AND, OR, and NOT using CMOS structures. We also learned about SPICE netlist. Finally, the lesson connected everything to system-level ideas like clock distribution and introduced the Schmitt trigger for handling noisy signals, helping me see how analog physics, digital logic, and simulation all fit together.

Homework Given¶

Modify the AND gate netlist to create an OR gate instead
Schmitt trigger analysis: Look up a CMOS Schmitt trigger schematic and identify which transistors set the upper vs lower threshold
Optional: Build a simple circuit (LED + resistor + button) in TinkerCAD and observe current flow

What I did (quick summary)¶

I simulated the given AND-gate netlist in ngspice, fixed a node-label plotting issue, and verified the output, then modified it into an OR gate and confirmed its waveform. I also simulated a CMOS Schmitt trigger in Multisim and identified M3 as setting Pull-up and M6 as setting Pull-down (final inverter is just a buffer), and built a basic LED–resistor–button circuit in TinkerCAD to observe current flow.

Understanding AND gate netlist and running it¶

Firstly before I modified the and gate to or, I decided to look into the and netlist which was in the analog basics folder and decided to run it on .ngspice to see the wave form. I also looked into the Ng spice manual as reference

I was able to see the output as such with an error at the end, which suggested there was an error in the syntax

After this I was able to view only 2 waveforms which is of V(a) and V(b) and there was no wave form of the output due to the error.

To fix the error, I edited the and.sp file where I changed the v(AND) to v(OUT and AND to OUT.

Once that was fixed, I was able to view a separate wave for AND

To view the waveforms together, I edited the file as follows:

Through this I was able to verify that the outcome matches as per how and gates work.

Modify AND gate Netlist to OR gate¶

Firstly to understand how the OR gate looks , I decided to used circuit lab to create the circuit.

Then I copied the and.sp from the analog basics folder to my designs folder to modify it to or.sp Once that was done, simulated and viewed the waveform to confirm the output

Schmitt Trigger analysis¶

For the CMOS Schmitt Trigger analysis, we were asked to identify which transistors set the Upper vs Lower threshold

For the schematic I decided to use the online simulator website Multism

The CMOS Schmitt trigger consists of:

A modified inverter with feedback (left section)

A standard inverter buffer stage (right section)

The hysteresis behavior is created by the feedback transistors in the left network.

The right inverter stage only buffers the output and does not affect the switching thresholds.

To understand how the graph looks, I did the simulation and observed the following:

From the transient simulation:

Green trace represents Input voltage (Vin)
Gray trace represents the Output voltage (Vout)
V(4) is the Internal pull-up node (between M4 and M5, connected to feedback PMOS M6)
V(3) is the Internal pull-down node (connected to NMOS feedback M3)

Important Observation

When Vin rises, the internal node V(4) drops before the output switches LOW. This indicates that the pull-down network becomes dominant at the switching moment.

Upper Threshold

Condition: - Vin is increasing - Output is initially HIGH - Output eventually switches HIGH to LOW

What Happens: - NMOS stack (M1, M2) begins turning ON. - Pull-down path strengthens. - Internal node V(4) drops. - Pull-up network weakens. - Output flips LOW.

Conclusion: The switching event is controlled by the NMOS feedback transistor (M3).

M3 reinforces the pull-down path when the output is HIGH, requiring Vin to rise further before switching occurs.

Therefore:

The NMOS feedback transistor (M3) sets the upper threshold.

Lower Threshold

Condition: - Vin is decreasing - Output is initially LOW - Output eventually switches LOW to HIGH

What Happens: - NMOS stack weakens. - Pull-up network regains strength. - PMOS feedback transistor (M6) reinforces pull-up. - Output flips HIGH.

Conclusion: The switching event is controlled by the PMOS feedback transistor (M6).

M6 strengthens the pull-up path when the output is LOW, requiring Vin to fall further before switching occurs.

Therefore: The PMOS feedback transistor (M6) sets the lower threshold.

Simple Circuit LED design¶

For the simple circuit LED Design, I used Tinker cad This circuit uses a 9V battery to power an LED through a resistor, with a push button acting as a switch. When the button is pressed, the circuit closes and current flows through the resistor and LED, turning it on; when released, the circuit opens and the LED turns off. The resistor limits current so the LED doesn’t burn out.