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Session 4: Layout & Fabrication

Homework Given

  • Block diagram: Sketch your project's architecture showing major modules and data flow (e.g., Pocket Synth: button inputs → tone selector → oscillator → PWM output)

  • Explore a standard cell: Open the sky130 standard cell library in KLayout and find an inverter (sky130_fd_sc_hd__inv_1). Identify metal, poly, and diffusion layers. In the container: 

    klayout/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
    Tip: Use Edit → Find (Ctrl+F) to search for "inv_1"

  • Connect the dots: Pick one block from your diagram — what standard cells might implement it? (e.g., "counter" needs flip-flops, "tone selector" needs muxes)

Block Diagram for Project Architecture

For my project I was thinking of doing something fun and wanted to see what I could do which was beginner level but something I could figure out as well. I looked into this website and I found some interesting projects. Verilog Projects

However I decided to go with a Digital Password Lock where the user enters a password using switches and the systems and compares it with the correct passoword and unlocks if corrects and denies access if it's wrong.

My project consists of the following components:

  • Switch input
  • Button input
  • Debounce circuit
  • Input register
  • Password comparator
  • FSM controller
  • LED output controller

The user enters a 4-bit password using switches which represent binary inputs (0 or 1). The debounce circuit removes noise from the button signal, which acts as the enter button. The input register stores the entered password when the button is pressed. The password comparator checks the entered password against the predefined correct password. The FSM controls the sequence of operation. The fail counter counts the number of incorrect password attempts, and if it reaches three attempts, the system enters a lock state where the red LED blinks to indicate a security lock. The LED outputs indicate whether access is granted or denied.

Understanding KLayout

Before exploring the standard cell in KLayout, I wanted to understand how Klayout works and how it had to be setup. I looked into the following tutorial video: KLayout Tutorial

Based on the video, I had to keep the default mode to editing:

Once that was done, I closed the KLayout and opened it again to see the following buttons which was not in viewer mode

I decided to explore a bit, before looking in the inverter, first I created a new hierarchical layout, with the technology as default but realized I can change it sg13g2 later in the layout.

In the layout, you are able to see the library on the left and the layer on the left

To get familiar with the layout and tools. I decided to look into the Nmos and Pmos which were in the sg13 _ dev library

After selecting and placing it on the canvas, I was able to see that the Nmos and Pmos were in blocks, However I wanted to see how it would look in different layers.

I noticed on the navigation bar, there was a display option, which made me wonder if this was for selecting different views of the component. I pressed the Full hierarchy and was able to view the layers of the Nmos and Pmos. I also wanted to try the other options like top level, however this didn't make any change.

First I wanted to observe the NMOS, I noticed in the layers I was able to see some of them in bold, which I assumed was probably indicating the different layers of the Nmos.

At first when I created the hierarchical layout, I had kept it at default and I noticed there was no layers unlike the sg13g2 technology. I wondered if the default showed layers only when we place the component on the canvas.

I wanted to observe how the layers when its default looks like, so I changed the technology to default and I was able to see a very simplified layer of the NMOS.

To understand the different layers of NMOS, I looked into the following video: NMOS Transistor

This video for the layout colors Layout Colors

This is my following understanding: - Substrate: which is the base on which the transistor is built on. For NMOS the substrate is P type, meaning the majority carriers are holes. - Active/ Diffusion region: This is the area where the source and drain of transitor are. - Polysilicon region: This is the area where the gate is formed. - Metal: Used for connections of different components such as the gate, darin and source. - Contact Region: This layer defines the contact between the diffusion and the metal layers.

As I was exploring, I found out double clicking on each layer on KLayout allows you to hide and unhide it. This way I was able to observe and understand each layer.

With this I wanted to try it on the sg13g2 technology, and obsreve how each layers look. As I had assumed, the bold words on the layer indicated the layers of the nmos.

I did the same for Pmos and to understand Pmos layers, I watched this video :

PMOS Transistor

I was able to understand the layers typically was same except for the type of substrate, which in case of PMOS is N type substrate meaning the majority carriers is electrons.

Explore a standard cell in KLayout

Now to look into the inverter in the sky130 standard cell library.

In the container, I used the command as instructed in the terminal:

klayout/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds

I got an error and so I tried opening the gds file from the KLayout which worked out for me.

Once the file was open, I was able to see the different cells of the sky130 and I tried finding the file with the hint given, where I saw the file for inv_1 and I pressed on it.

This was how the canvas displayed the inverter, I chnaged the display to full hierarchy and was able to see different layers.

From previous session, we learned that inverter consist of one PMOS and NMOS transistor. Based on what I saw on the hierarchical layout of PMOS and CMOS that I explored KLayout, I expected to see active region, poly layer, metal and contact region.

I looked into the KLayout documentation which helped me understand the different layers of an inverter better:

KLayout

From the schematic of Inverter, we are able to undertsnad how the placement of the CMOS Transistor and hence the different layers can be identified as such.

Based on the documentation, I was able to see how the different layers looked.

In the KLayout where I opened the inverter, I hid some of the layers and I was able to identify the different layers, however the layer name were in numbers.

I looked into the KLayout documentation to find a way to display the layers in words instead of numbers:

Technology

Based on the documentation, when the layer names and display can change when we switch technologies, because of layer mapping and layer properties.

Under the tools option, we can see technology manager where we can add new technlogy.

This website was helpful as well. KLayout Forum

I had to look for a .lyt file, which I found under the following path 

/foss/pdks/sky130A/libs.tech/klayout/tech/

Once the technology was added, I switched to sky130A Technology, which gave the layer names as follows:

Looking at the layout, we are able to figure out that the PMOS is on the top and the NMOS in the bottom.

Layer Name Full Form / Meaning Purpose
li1 Local Interconnect Short local wiring layer inside cells
licon Local Interconnect Contact Connects diffusion or poly to LI1
mcon Metal Contact Connects local interconnect to Metal1
metal1 (met1) Metal Layer First main routing metal layer
poly Polysilicon Forms the transistor gate
diff Diffusion (Active) Region where source/drain are formed
nwell N-type Well Region where PMOS transistors are built
pwell P-type Well Region where NMOS transistors are built
psdm P-type Source Drain Implant Doping mask for PMOS source/drain
nsdm N-type Source Drain Implant Doping mask for NMOS source/drain
tap Well Tap / Substrate Tap Connects well to power or ground
HVTP High Threshold Voltage PMOS implant The HVTP layer is used to create PMOS transistors with a higher threshold voltage (Vt).

Connect the dots

I wanted to explore the password comparator, which is one of the most important block.

For the comparator block, after referring the following website on comparators, I am planning to use the equality comparator which is used for electronic locks and security devices.

This block can be implemented using XNOR gates and AND gates. Each XNOR gate compares one entered bit with one stored password bit. If all bit pairs match, the outputs of the XNOR gates become 1. These outputs are then combined through AND gates to generate a final match signal. This signal is used to control the green or red LED output.

Truth Table for Comparator | A[3:0] | B[3:0] | MATCH | | --------- | --------------- | ----- | | 0000 | 0000 | 1 | | 0001 | 0001 | 1 | | 0010 | 0010 | 1 | | 1011 | 1011 | 1 | | 0101 | 0100 | 0 | | 1111 | 0111 | 0 | | 1001 | 1011 | 0 | | any value | different value | 0 |

XNOR (Exclusive NOR) gate only outputs a high signal '1' when the input are equal and it is a complement of XOR. XNOR= NOT (A XOR B)

XNOR can be made using of 2 AND gates and an OR gate

Truth table for XNOR gate | A | B | MATCH | | --------- | --------------- | ----- | | 0 | 0 | 1 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 1 |

For a CMOS XNOR gate, it has a total of twelve transistors, four of them are used to create two inverters. Each of the two input signals is fed into an inverter. Each input is split into an non-inverted input signal and an inverted input signal, given by A and B. Non-inverted and inverted A and B signals are then given to the P-MOS and N-MOS transistors.

I was curious about how the XNOR would look in the KLayout and decided to check it out. When I counted the number of transistor, I found out there was a total of 10 Transistors only. I looked it up online and found out that with XNOR gatethe CMOS implementation can be realized with 10 transistors, although typically it is often considered 12 transistors. The 10 transistors consist of 5 PMOS and 5 NMOS.

I also wanted to observe the AND gate. A 4-input AND gate can be implemented using a 4-input NAND gate followed by an inverter. The NAND gate requires eight transistors and the inverter requires two transistors, giving a total of ten transistors.

In the Verilog implementation, this equality comparison is represented using the == operator, but at the hardware level the synthesis tool implements it using XNOR and AND logic gates.