Session 6: Synthesis & Physical Design¶
Homework¶
- Synthesize your design — review gate count and check for unintended latches
- Run place and route flow
- Analyze timing reports — identify and fix any violations
- Generate GDS and review layout in KLayout
Design Synthesis¶
Now to work on the synthesis of the RTL I wrote and simulated. Basically the synthesis converts the verilog RTL to gate-level netlist made of standard cells.
Verilog RTL to logic synthesis to Gate-level netlist.
I ran the yosys command and was able to get following output:
> yosys
yosys> read_verilog digital_password_lock.v debounce.v
1. Executing Verilog-2005 frontend: digital_password_lock.v
Parsing Verilog input from `digital_password_lock.v' to AST representation.
Generating RTLIL representation for module `\password_core'.
Generating RTLIL representation for module `\register4'.
Generating RTLIL representation for module `\digital_password_lock'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: debounce.v
Parsing Verilog input from `debounce.v' to AST representation.
Generating RTLIL representation for module `\debounce'.
Successfully finished Verilog frontend.
Yosys sucessfully loaded my files and all the modules were recognized.
Next was to run the hierarchy :
yosys> hierarchy -check -top digital_password_lock
3. Executing HIERARCHY pass (managing design hierarchy).
3.1. Analyzing design hierarchy..
Top module: \digital_password_lock
Used module: \password_core
Used module: \register4
Used module: \debounce
Parameter \CLK_FREQ = 50000000
3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\debounce'.
Parameter \CLK_FREQ = 50000000
Generating RTLIL representation for module `$paramod\debounce\CLK_FREQ=s32'00000010111110101111000010000000'.
3.3. Analyzing design hierarchy..
Top module: \digital_password_lock
Used module: \password_core
Used module: \register4
Used module: $paramod\debounce\CLK_FREQ=s32'00000010111110101111000010000000
3.4. Analyzing design hierarchy..
Top module: \digital_password_lock
Used module: \password_core
Used module: \register4
Used module: $paramod\debounce\CLK_FREQ=s32'00000010111110101111000010000000
Removing unused module `\debounce'.
Removed 1 unused modules.
Next I ran the following inside yosys:
synth -top digital_password_lock
stat
check
yosys> stat
5. Printing statistics.
=== $paramod\debounce\CLK_FREQ=s32'00000010111110101111000010000000 ===
+----------Local Count, excluding submodules.
|
118 wires
154 wire bits
8 public wires
26 public wire bits
4 ports
4 port bits
151 cells
40 $_ANDNOT_
4 $_AND_
1 $_DFFE_PN0P_
22 $_DFF_PN0_
15 $_NAND_
5 $_NOR_
1 $_NOT_
13 $_ORNOT_
31 $_OR_
6 $_XNOR_
13 $_XOR_
=== digital_password_lock ===
+----------Local Count, excluding submodules.
|
62 wires
145 wire bits
15 public wires
51 public wire bits
7 ports
12 port bits
79 cells
18 $_ANDNOT_
3 $_AND_
5 $_DFFE_PN0P_
12 $_DFF_PN0_
1 $_MUX_
7 $_NAND_
2 $_NOR_
3 $_NOT_
5 $_ORNOT_
12 $_OR_
2 $_XNOR_
9 $_XOR_
3 submodules
1 $paramod\debounce\CLK_FREQ=s32'00000010111110101111000010000000
1 password_core
1 register4
=== password_core ===
+----------Local Count, excluding submodules.
|
4 wires
7 wire bits
2 public wires
5 public wire bits
2 ports
5 port bits
3 cells
1 $_ANDNOT_
1 $_AND_
1 $_ORNOT_
=== register4 ===
+----------Local Count, excluding submodules.
|
5 wires
11 wire bits
5 public wires
11 public wire bits
5 ports
11 port bits
4 cells
4 $_DFFE_PN0P_
=== design hierarchy ===
+----------Count including submodules.
|
237 digital_password_lock
151 $paramod\debounce\CLK_FREQ=s32'00000010111110101111000010000000
3 password_core
4 register4
+----------Count including submodules.
|
189 wires
317 wire bits
30 public wires
93 public wire bits
18 ports
32 port bits
- memories
- memory bits
- processes
237 cells
59 $_ANDNOT_
8 $_AND_
10 $_DFFE_PN0P_
34 $_DFF_PN0_
1 $_MUX_
22 $_NAND_
7 $_NOR_
4 $_NOT_
19 $_ORNOT_
43 $_OR_
8 $_XNOR_
22 $_XOR_
3 submodules
1 $paramod\debounce\CLK_FREQ=s32'00000010111110101111000010000000
1 password_core
1 register4
The design was synthesized in Yosys using digital_password_lock as the top module. The synthesis stat showed a total of 237 cells in the full design hierarchy. This includes 44 flip-flop cells and a combination of logic gates such as AND, OR, NAND, NOR, XOR, and XNOR. A significant portion of the cell count comes from the debounce module, which contains internal counters and sequential logic. The synthesized design therefore includes both combinational and sequential hardware as expected.
Next I ran the check command
yosys> check
6. Executing CHECK pass (checking for obvious problems).
Checking module $paramod\debounce\CLK_FREQ=s32'00000010111110101111000010000000...
Checking module digital_password_lock...
Checking module password_core...
Checking module register4...
Found and reported 0 problems.
Through this since no problems was detected, no intented latches were inferred during synthesis.
Then I mapped it it to sky130 cells, I used the command from the class page, I forgot about the path and it gave me some error. So I made sure to give the correct path:
dfflibmap -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
abc -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
I also generated the gate-level netlist after cleaning it up
yosys> clean
Removed 0 unused cells and 254 unused wires.
yosys> write_verilog -noattr synth.v
7. Executing Verilog backend.
7.1. Executing BMUXMAP pass.
7.2. Executing DEMUXMAP pass.
Dumping module `$paramod\debounce\CLK_FREQ=s32'00000010111110101111000010000000'.
Dumping module `\digital_password_lock'.
Dumping module `\password_core'.
Dumping module `\register4'.
Place and Route¶
For the P&R step, I have to expect the following: - Floorplanning - Power planning - Cell placement - Clock tree synthesis - Routing - Fill
With this I ran the openroad command in my project folder.
I ran the following command:
read_lef $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
openroad> read_lef $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
[WARNING ODB-0229] Error: library (sky130_fd_sc_hd) already exists
openroad> read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
[WARNING STA-1140] /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists.
1
Read Synthesized Netlist I ran the following command:
read_verilog synth.v //generated in yosys
link_design
```