Synthesis & Physical Design

Homework :

• Synthesize your design — review gate count and check for unintended latches
• Run place and route flow
• Analyze timing reports — identify and fix any violations
• Generate GDS and review layout in KLayout

Design synthesis

I modified the given Makefile by adding my projet to the list to be able to synthetise it by typing make synth-til. til being the short name of the project as it’s copying the til311 IC. The end of the run give us some stats :

=== design hierarchy ===

        +----------Count including submodules.
        |
       58 til311
       50 decoder
        8 shift

        +----------Count including submodules.
        |
       53 wires
       92 wire bits
       16 public wires
       55 public wire bits
       14 ports
       47 port bits
        - memories
        - memory bits
        - processes
       58 cells
        3   $_ANDNOT_
        1   $_AND_
        8   $_DFF_PP0_
       27   $_MUX_
        1   $_NAND_
        1   $_NOR_
        3   $_NOT_
        3   $_ORNOT_
       11   $_OR_
        2 submodules
        1   decoder
        1   shift

Now the synthesis for Sky130, launched by typing make sky130-til. It uses the synth.tcl script because there are more steps. Result is slightly different :

=== design hierarchy ===

        +----------Count including submodules.
        |        +-Area including submodules.
        |        | 
       52  431.664 til311
       36  201.443 decoder
       16  230.221 shift

        +----------Count including submodules.
        |        +-Area including submodules.
        |        | 
       47        - wires
       86        - wire bits
       16        - public wires
       55        - public wire bits
       14        - ports
       47        - port bits
        -        - memories
        -        - memory bits
        -        - processes
       52  431.664 cells
        1    7.507   sky130_fd_sc_hd__a21o_1
        2    10.01   sky130_fd_sc_hd__a21oi_1
        1    8.758   sky130_fd_sc_hd__a22o_1
        1    7.507   sky130_fd_sc_hd__a22oi_1
        2   17.517   sky130_fd_sc_hd__a2bb2oi_1
        1    8.758   sky130_fd_sc_hd__a32oi_1
       10   37.536   sky130_fd_sc_hd__clkinv_1
        8  200.192   sky130_fd_sc_hd__dfrtp_1
        3   18.768   sky130_fd_sc_hd__lpflow_isobufsrc_1
        5   18.768   sky130_fd_sc_hd__nand2_1
        2   12.512   sky130_fd_sc_hd__nand2b_1
        4   15.014   sky130_fd_sc_hd__nor2_1
        2    10.01   sky130_fd_sc_hd__nor3_1
        7   35.034   sky130_fd_sc_hd__o21ai_0
        1    6.256   sky130_fd_sc_hd__o22ai_1
        2   17.517   sky130_fd_sc_hd__o32ai_1
        2  431.664 submodules
        1  201.443   decoder
        1  230.221   shift

   Chip area for top module '\til311': 431.664000
     of which used for sequential elements: 200.192000 (46.38%)

This time, two files are created in the build/ directory, a JSON file and Verilog file. We can visualize in a graph what was created using the show command in yosys or by sending the .json file to netlistsvg, a tool we can use online or install localy. Netlistsvg result : We can add this in the flow TCL file:

# Generate DOT file for graphics visualization
show -prefix $OUT_DIR/${TOP}_synth -notitle -colors 2 -width -format dot

It creates a DOT file we can view with xdot. It creates a big graph not so easy to read. I barely explored the options to visualize a netlist.

Place & Route

make pnr-til uses the much bigger flow/pnr.tcl script and takes a little bit more time to execute, even for a simple design like this. Most report files are empty, i’m not sure it’s normal. Design area 432 um^2 44% utilization. As the design is very simple with no real clock, timing analysis is not really usefull here.

GDS

make gds-til runs quickly.