* NAND gate adapted from AND gate ngspice example

* Include the Sky130 device models
.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt

* Power supply: 1.8V
Vdd vdd gnd 1.8


* AND pull-up network -- two pmos in parallel
Xp1 NAND_OUT A VDD VDD sky130_fd_pr__pfet_01v8_hvt  l=0.150  w=0.99
Xp2 NAND_OUT B VDD VDD sky130_fd_pr__pfet_01v8_hvt  l=0.150  w=0.99


* Pull-down network -- two nmos in series
Xn1 NAND_OUT A npd 0 sky130_fd_pr__nfet_01v8 w=0.5 l=0.150 
Xn2 npd B 0 0 sky130_fd_pr__nfet_01v8 w=0.5 l=0.150

* Input voltage source, ramps up to VDD then back down
vin1 A 0 PWL(0 0 0.5mS 0 0.501mS 1V 1.5mS 1V 1.501mS 0) 
vin2 B 0 PWL(0 0 1mS 0 1.001mS 1V 2.0mS 1V 2.0001mS 0) 

.control 
* transient simulation using vin sweep
  tran 100n 4m 

* plot vout against vin 
  plot v(A) 
  plot v(B) 
  plot v(NAND_OUT)
  meas tran tpd_hl TRIG v(A) VAL=0.9 RISE=1 TARG v(NAND_OUT) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(A) VAL=0.9 FALL=1 TARG v(NAND_OUT) VAL=0.9 RISE=1

.endc