Session 3: Schematic Design & Simulation¶
Netlisting, schematic capture, cell libraries
Assignment¶
Reuse and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter) and change the models to refer to the PDK models
Simulate it in SPICE, verify truth table (it will look something like the right table), and measure propagation delays (low-to-high and high-to-low)
Write an initial analog block that you can use in your chip project (e.g., an adder, counter, etc.)
NAND gate from AND gate¶
NAND gate netlist derived from AND gate netlist with PDK models
Results of running simulation with ‘ngspice nand_s03_pdk.sp’
Truth table matches expectations (from left to right on the graph: inputs 00, 01, 11, 10; output 1, 1, 0, 1)
Transient analysis from SPICE shows low-high transition of 82.7 ns and high-low of 500 us.