Session 5: RTL Design & Verification

Assignment

Write Verilog for your project’s core module (aim for 10-30 lines to start)

Integrate with any provided library modules (e.g., debounce, UART, PWM) — create a top-level wrapper

Simulate with a testbench and examine waveforms in GTKWave

Run linter (verilator –lint-only) and fix any warnings