Session03 schematics&simulation

For session 3 we learned about basic schematic elements, such as wires, net labels, ports, power symbols, etc. The circuit diagrams we’ve seen up to this point represented circuits, but weren’t proper schematics from a standardization view. (no dots where wires should connect, no pin numbers or pin labels, no reference numbers, etc.).

Netlist labeling convention¶

For Netlists, its similar to reference labels in kicad, where:

R=resistor, C=capacitor, L=inductor, V=voltage, I=current, M=mosfet, and X=subcircuit, which is a condensed circuit.

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For the Inverter circuit it states .include “sky130.lib”. which is a new library nomenclature.

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Variances in library models¶

Power indicated with the labels used for power and the voltage

Vdd vdd gnd 1.8

Input signal rise/fall times

PULSE(starting voltage (0), high voltage (1.8), starting point delay (0), rise time (100p), fall time(100p), hold time(1n), and repeat time(2n))

Vin in gnd PULSE(0 1.8 0 100p 100p 1n 2n)

PMOS: drain / gate / source / body connect Pmos output to drain(out), in to gate(in), source(vdd) substrate(vdd), new model of pfet(sky130_fd_p__pfet_01v8), width(W=1u), length(L=150n)

Mp out in vdd vdd sky130_fd_p__pfet_01v8 W=1u L=150n

Simulation commands¶

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p=steps, n=duration
tran 10p 10n

Save the node voltages for plotting¶

.save v(vin) v(vout)

For the .dc, .tran, and .ac analysis, the applied change is along the horizontal/X axis, and side effects of the change are seen on the vertical/Y axis.

Run the block¶

control block .control run plot v(in) v(out)

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Measurements for plots¶

measure, tran=type of measurement, pulldown (high to low), triggered by vin, starting value, rise value, target for vout is where it gets to .9v, falling edge.

meas tran tpd_lh TRIG v(in) VAL=0.9 RISE=1 TARG v(out) VAL=0.9 FALL=1

Measure transiton from low to high, trigger of rise time for when vin goes to .9

meas tran tpd_hl TRIG v(in) VAL=0.9 RISE=1 TARG v(out) VAL=0.9 RISE=1

Save results for external plotting¶

Then you can plot the results in Python.

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.control run wrdata results.csv v(in) v(out)

.endc .end

Speed simulation¶

To emulate changes in timing, you can simulate fast and slow speeds.

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you can abstract away the transistor level details in to a “behavioral” one.

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## Homework

Summary

Schematic capture is the first step in circuit design
SPICE simulates circuit behavior with detailed models
Analysis types: DC, AC, Transient, Operating Point
PDK libraries provide calibrated device models
Corner simulation ensures robustness across process variation

Homework

Reuse and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter) and change the models to refer to the PDK models

If we look at the original code, we can see the inverterlisted below the pull-up and pull-down network, which can be removed to turn it into a NAND gate:

* AND gate ngspice example

* NGSPICE transistor models
.model mosn NMOS level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16
.model mosp PMOS level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16

* 1 V power supply
vsup VDD 0 1

* AND pull-up network -- two pmos in parallel
* Syntax: Pmos output to drain(nOUT), in to gate(in), source(VDD) substrate(VDD), new model of pfet(sky130_fd_p__pfet_01v8), width(W=1u), length(L=150n)
Mp1 nOUT A VDD VDD mosp L=0.35u W=2u
Mp2 nOUT B VDD VDD mosp L=0.35u W=2u

*AND Pull-down network -- two nmos in series
Mn1 nOUT A npd 0 mosn L=0.35u W=2u
Mn2 npd B 0 0 mosn L=0.35u W=2u

* Inverter, or a logical NOT
Mp3 AND nOUT VDD VDD mosp L=0.35u W=2u
Mn3 AND nOUT 0 0 mosn L=0.35u W=2u

* Input voltage source, ramps up to VDD then back down
vin1 A 0 PWL(0 0 2mS 0 2.001mS 1V 3mS 1V 3.001mS 0)
vin2 B 0 PWL(0 0 1mS 0 1.001mS 1V 2.5mS 1V 2.5001mS 0)

.control
* transient simulation using vin sweep
  tran 100n 4m

* plot vout against vin
  plot v(A)
  plot v(B)
  plot v(AND)
.endc

Next, let’s swap the mosfet models for PDK models. You do this by adding the lib file at the top “sky130A/libs.tech/ngspice/sky130.lib.spice” tt, and replacing the NMOS with sky130_fd_pr__nfet_01v8, and replace the PMOS sky130_fd_pr__pfet_01v8. Because we’re now working with the sky models, the voltage is brought up to 1.8 to match the nominal voltage of the SKY130 model. We need to tell the directory where to find the .lib file alt text

pmos and nmos transistors are reformatted to match the library name syntax, and the meas command is added at the end to measure the propagation delays.

* NAND gate ngspice example

* Sky130 PDK models, typical-typical corner
.lib "sky130A/libs.tech/ngspice/sky130.lib.spice" tt

* 1.8 V power supply (Sky130 nominal)
vsup VDD 0 1.8

* NAND pull-up network -- two pmos in parallel
* Format: Xname drain gate source body model L=... W=... 
Xp1 NAND A VDD VDD sky130_fd_pr__pfet_01v8 L=0.35u W=2u 
Xp2 NAND B VDD VDD sky130_fd_pr__pfet_01v8 L=0.35u W=2u

* NAND pull-down network -- two nmos in series
* Format: Xname drain gate source body model L=... W=... 
Xn1 NAND A npd 0 sky130_fd_pr__nfet_01v8 L=0.35u W=2u
Xn2 npd  B 0   0 sky130_fd_pr__nfet_01v8 L=0.35u W=2u

* Input voltage sources, ramps up to VDD then back down
vin1 A 0 PWL(0 0 2mS 0 2.001mS 1.8V 3mS 1.8V 3.001mS 0)
vin2 B 0 PWL(0 0 1mS 0 1.001mS 1.8V 2.5mS 1.8V 2.5001mS 0)

.control
* transient simulation using vin sweep
  tran 100n 4m

* measure propagation delays (threshold = VDD/2 = 0.9V)
meas tran tpd_hl TRIG v(B) VAL=0.9 RISE=1 TARG v(NAND) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(B) VAL=0.9 FALL=1 TARG v(NAND) VAL=0.9 RISE=1

* export to CSV
wrdata nand_output.csv v(A) v(B) v(NAND)

* plot out against vin
plot v(A)
plot v(B)
plot v(NAND)
.endc

In order to simulate this in spice, you need to make sure the library files are included.

I cannot get it to find the library file. I’ve tried so many things. what is the issue?

Simulate it in SPICE, verify truth table (it will look something like the right table), and measure propagation delays (low-to-high and high-to-low)
Write an initial analog block that you can use in your chip project (e.g., an adder, counter, etc.)

Here’s a good starting point: https://analoghub.ie/category/verilogModels/article/counter

referencing the example above, we can use the analog block: