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Session 3: Schematic Design & Simulation

Netlisting, schematic capture, and cell libraries

Summary:

In this section we review the previous lecture. We learned about schamtic capture & translation to netlisting. Common SPICE errors & commands, plotting results in Python, propogation delays, and corner cases.

Homework assignments:

  1. Reuse the and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter) and change the models to refer to the PDK models
  2. Simulate it in SPICE, verify truth table (it will look something like the table below) and measure propogation delays (low-to-high and high-to-low) A B OUT 0 0 1 0 1 1 1 0 1 1 1 0
  3. Wire an initial anolog block that you can use in you chip project (e.g. an adder, counter, etc.)

Here’s a good starting point: https://analoghub.ie/category/verilogModels/article/counter

Research

Results