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Session 5: RTL Design & Verification

Summary:

Homework assignments:

  1. Write Verilog for you project’s core modeule (aim for 10-30 lines to start)
  2. Integrate with any provided library modules (e.g., debounce, UART, PWM) - create a top-level wrapper
  3. Simulate with a testbench and examine waveforms in GTKWave
  4. Run linter (verilator --lint-only) and fix any warnings

Research

Results