Session 6: Synthesis & Physical Design

In Thursday’s session, Andreas Olofsson walked through the full path from RTL to physical silicon: synthesizing Verilog into a standard-cell netlist, running place & route, and then validating the result with static timing analysis before generating a GDS to inspect in KLayout. The tasks for this week are: (1) synthesize your design and review warnings/cell counts (and confirm no unintended latches), (2) run place & route, (3) analyze the STA timing reports, and (4) generate the GDS and inspect it in KLayout.

The tasks for this week are:

• Synthesize your design and review warnings/cell counts (and confirm no unintended latches),
• Run place & route
• Analyze the STA timing reports
• Generate the GDS and inspect it in KLayout.

Synthesis

Synthesis (in digital design) is the step that transforms your RTL description (e.g., Verilog) into a concrete hardware implementation built from gates and standard cells.

In practice, synthesis:

• Parses your RTL and extracts the intended logic (combinational logic, registers/flip-flops, FSMs, etc.).
• Maps that logic onto a specific technology library (for example sky130 standard cells): NAND/NOR gates, muxes, flip-flops, buffers, and so on.
• Optimizes the design to meet a set of constraints (typically provided in an SDC file: clock period, uncertainty, I/O delays), trading off timing, area, and power.
• Produces a gate-level netlist plus reports (cell counts, critical paths/slack estimates, area summaries, and warnings such as unintended latch inference).

Key idea: RTL describes what the circuit should do; synthesis decides how to build it using real cells so it can be physically implemented and meet timing.

In a typical digital ASIC/standard-cell flow, the synthesis process is usually broken into these stages (tool names vary, but the concepts are the same):

1. Read & elaborate RTL

2. Parse the Verilog/SystemVerilog, resolve parameters/generates, build the design hierarchy, and determine which module is the top.

3. Apply constraints

4. Load timing constraints (usually SDC): clock definitions, input/output delays, clock uncertainty, false/multicycle paths, etc.

5. RTL → Boolean logic

6. Translate behavioral RTL into an internal representation of combinational logic + sequential elements (registers, enables, resets).

7. Generic optimization

8. Optimize the logic independent of a specific cell library: constant propagation, logic simplification, common-subexpression sharing, retiming (sometimes), removal of unreachable logic, etc.

9. Technology mapping

10. Map the generic logic onto a specific standard-cell library (e.g., sky130_fd_sc_hd): choose real gates, muxes, flip-flops, etc.

11. Often includes specialized mapping steps for flip-flops and then combinational mapping (e.g., ABC).

12. Timing-driven optimization

13. Iterate to meet timing: gate sizing (selecting stronger/weaker drive cells), buffering, restructuring logic, replication to reduce fanout, etc.

14. Check & report

15. Produce reports: WNS/TNS, critical paths, cell counts, area estimate, and warnings (latches, combinational loops, unconstrained paths).

16. Write outputs

17. Emit the gate-level netlist (mapped Verilog), and often auxiliary outputs like timing/area reports, and sometimes an SDF for gate-level timing simulation.

That’s “synthesis.” After this, you hand the netlist (plus constraints) to place & route, which turns it into a physical layout.

Logic Synthesis with Yosys (Ring Modulator)

For my ring modulator project, I use Yosys to translate the Verilog RTL into a gate-level netlist. Conceptually, the flow is:

Verilog RTL → (Yosys synthesis) → generic netlist → (ABC mapping) → mapped netlist (Sky130 standard cells).

The synthesis steps follow the standard process: Yosys parses the RTL, elaborates the hierarchy (resolving the top module and parameters), performs logic optimization, and then does technology mapping to a target cell library. The mapping stage uses the Sky130 Liberty file so the final result is described in real standard cells (e.g., sky130_fd_sc_hd__*).

ring_modulator.v

Before starting the synthesis analysis, I first want to recall the RTL design I am working with. My project is a ring modulator written in Verilog, with a clock input, an active-low reset, two signed 16-bit inputs (signal_in and carrier_in), and one signed 16-bit output (mod_out). Internally, I use a signed 32-bit register called product to store the result of multiplying the two input signals.

At every positive clock edge, the design multiplies signal_in and carrier_in and stores the result in product. Then, to keep the output within a 16-bit range, I take the middle part of that multiplication result, specifically product[30:15], and assign it to mod_out. When reset is active, both product and mod_out are cleared to zero. This is the RTL description that I later use as the starting point for synthesis with Yosys.

module ring_modulator (
    input  wire              clk,
    input  wire              rst_n,
    input  wire signed [15:0] signal_in,
    input  wire signed [15:0] carrier_in,
    output reg  signed [15:0] mod_out
);

    reg signed [31:0] product;


    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            product <= 32'sd0;
            mod_out <= 16'sd0;
        end else begin
            product <= signal_in * carrier_in;
            mod_out <= product[30:15];       
        end
    end
endmodule

Gate Count Estimation

Estimated standard-cell count before running Yosys (rough)

This is a back-of-the-envelope estimate for me ring_modulator before synthesis, just to anticipate where the area will go. The exact numbers will change after Yosys optimizations (especially because you only use product[30:15]).

Assumptions

• Signed 16-bit × 16-bit multiply (signal_in * carrier_in)
• Output takes product[30:15]
• Two pipeline registers: product (32-bit) and mod_out (16-bit)
• Standard-cell implementation (no dedicated multiplier macro)

Block	Function	Width	Estimated cells (range)	Notes
product register	Stores product (pipeline stage)	32 bits	~32 DFF	One FF per bit (may be reduced if bits are optimized away)
mod_out register	Stores output	16 bits	~16 DFF	One FF per bit
16×16 signed multiplier	Main arithmetic	16×16	~800–2500	Dominant cost: partial products + adder tree
Sign/extension logic	Signed handling around the multiply	small	~10–100	Depends on mapping/structure
Bit slicing / wiring	mod_out <= product[30:15]	16 bits	~0–20	Often just wiring; sometimes a few buffers
Reset-related logic	Async reset behavior	48 bits	~0–100	Many libs have reset FFs, otherwise extra gates appear
Total (rough)			~900–2800	Multiplier dominates; synthesis can prune unused bits

Key takeaway: the multiplier is the heavy part, while the registers are predictable (~48 FFs unless pruned).

Basic Yosys Commands (as used in the class)

Yosys is an open-source digital synthesis tool that converts a Verilog RTL design into a gate-level netlist. In the design flow, it is used to interpret the hardware description, optimize the logic, and generate a synthesized representation of the circuit that can later be processed by place-and-route tools such as OpenROAD. This makes Yosys a key step between the logical design of the circuit and its physical implementation.

This is the minimal command sequence (same structure as the notebook) write in a new file synth.tcl, adapted to ring_modulator.v:

# Read Verilog
read_verilog ring_modulator.v

# Elaborate hierarchy (choose the top module)
hierarchy -check -top ring_modulator

# Synthesize to a generic netlist
synth -top ring_modulator

# Map to Sky130 standard cells
dfflibmap -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
abc       -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

# Clean up and write output
clean
stat
write_verilog -noattr ring_modulator_synth.v

I need set the full path of lib, because with $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib dont find the path or same with only sky130_fd_sc_hd__tt_025C_1v80.lib. After see documentation I can resolve with export PDK_ROOT=/foss/pdks, I will try later.

Running Yosys

I can run Yosys in a few different ways depending on what I need: interactively from the Yosys prompt, by executing a script file for a repeatable flow, or as a single command-line one-liner—following the same approach shown in the class notes.

Script run (recommended):

yosys -s synth.tcl

One-liner run:

yosys -p "
  read_verilog ring_modulator.v;
  hierarchy -check -top ring_modulator;
  synth -top ring_modulator;
  dfflibmap -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib;
  abc -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib;
  clean;
  stat;
  write_verilog -noattr ring_modulator_synth.v;
"

What to check after synthesis

After running synthesis in Yosys, I focus on the same checkpoints described in the notebook: I review any warnings, confirm that no unintended latches were inferred (which would usually indicate a bug), and use the stat report to look at the standard-cell and flip-flop counts to gauge the overall design size. In my ring modulator, the 16×16 multiplier is likely to dominate the cell count, so the stat output is a particularly useful sanity check.

Terminal contents

/foss/designs/ring_modulator > yosys -s synth.tcl

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2026  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.62 (git sha1 7326bb7d6, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)

-- Executing script file `synth.tcl' --

1. Executing Verilog-2005 frontend: ring_modulator.v
Parsing Verilog input from `ring_modulator.v' to AST representation.
Generating RTLIL representation for module `\ring_modulator'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \ring_modulator

2.2. Analyzing design hierarchy..
Top module:  \ring_modulator
Removed 0 unused modules.

3. Executing SYNTH pass.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Analyzing design hierarchy..
Top module:  \ring_modulator

3.1.2. Analyzing design hierarchy..
Top module:  \ring_modulator
Removed 0 unused modules.

3.2. Executing PROC pass (convert processes to netlists).

3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$ring_modulator.v:12$1 in module ring_modulator.
Removed a total of 0 dead cases.

3.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 2 redundant assignments.
Promoted 0 assignments to connections.

3.2.4. Executing PROC_INIT pass (extract init attributes).

3.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \rst_n in `\ring_modulator.$proc$ring_modulator.v:12$1'.

3.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\ring_modulator.$proc$ring_modulator.v:12$1'.
     1/2: $0\mod_out[15:0]
     2/2: $0\product[31:0]

3.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\ring_modulator.\mod_out' using process `\ring_modulator.$proc$ring_modulator.v:12$1'.
  created $adff cell `$procdff$8' with positive edge clock and positive level reset.
Creating register for signal `\ring_modulator.\product' using process `\ring_modulator.$proc$ring_modulator.v:12$1'.
  created $adff cell `$procdff$13' with positive edge clock and positive level reset.

3.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `ring_modulator.$proc$ring_modulator.v:12$1'.
Cleaned up 0 empty switches.

3.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
<suppressed ~4 debug messages>

3.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Removed 3 unused cells and 7 unused wires.
<suppressed ~4 debug messages>

3.5. Executing CHECK pass (checking for obvious problems).
Checking module ring_modulator...
Found and reported 0 problems.

3.6. Executing OPT pass (performing simple optimizations).

3.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 3 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ring_modulator..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

3.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \ring_modulator.
Performed a total of 0 changes.

3.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 3 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.6.6. Executing OPT_DFF pass (perform DFF optimizations).

3.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..

3.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.6.9. Finished fast OPT passes. (There is nothing left to do.)

3.7. Executing FSM pass (extract and optimize FSM).

3.7.1. Executing FSM_DETECT pass (finding FSMs in design).

3.7.2. Executing FSM_EXTRACT pass (extracting FSM from design).

3.7.3. Executing FSM_OPT pass (simple optimizations of FSMs).

3.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..

3.7.5. Executing FSM_OPT pass (simple optimizations of FSMs).

3.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

3.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

3.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

3.8. Executing OPT pass (performing simple optimizations).

3.8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 3 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ring_modulator..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

3.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \ring_modulator.
Performed a total of 0 changes.

3.8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 3 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.8.6. Executing OPT_DFF pass (perform DFF optimizations).

3.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..

3.8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.8.9. Finished fast OPT passes. (There is nothing left to do.)

3.9. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 32) from FF cell ring_modulator.$procdff$13 ($adff).
Removed top 1 bits (of 32) from port Y of cell ring_modulator.$mul$ring_modulator.v:17$3 ($mul).
Removed top 1 bits (of 32) from wire ring_modulator.$0\product[31:0].
Removed top 8 bits (of 32) from wire ring_modulator.product.

3.10. Executing PEEPOPT pass (run peephole optimizers).

3.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

3.12. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module ring_modulator:
  creating $macc model for $mul$ring_modulator.v:17$3 ($mul).
  creating $macc cell for $mul$ring_modulator.v:17$3: $auto$alumacc.cc:382:replace_macc$16
  created 0 $alu and 1 $macc cells.

3.13. Executing SHARE pass (SAT-based resource sharing).

3.14. Executing OPT pass (performing simple optimizations).

3.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 3 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ring_modulator..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \ring_modulator.
Performed a total of 0 changes.

3.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 3 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.14.6. Executing OPT_DFF pass (perform DFF optimizations).

3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..

3.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.14.9. Finished fast OPT passes. (There is nothing left to do.)

3.15. Executing MEMORY pass.

3.15.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

3.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

3.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

3.15.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

3.15.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

3.15.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..

3.15.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

3.15.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

3.15.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..

3.15.10. Executing MEMORY_COLLECT pass (generating $mem cells).

3.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..

3.17. Executing OPT pass (performing simple optimizations).

3.17.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.17.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 3 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.17.3. Executing OPT_DFF pass (perform DFF optimizations).

3.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..

3.17.5. Finished fast OPT passes.

3.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

3.19. Executing OPT pass (performing simple optimizations).

3.19.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.19.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 3 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ring_modulator..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

3.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \ring_modulator.
Performed a total of 0 changes.

3.19.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 3 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.19.6. Executing OPT_SHARE pass.

3.19.7. Executing OPT_DFF pass (perform DFF optimizations).

3.19.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..

3.19.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.19.10. Finished fast OPT passes. (There is nothing left to do.)

3.20. Executing TECHMAP pass (map to technology primitives).

3.20.1. Executing Verilog-2005 frontend: /foss/tools/yosys/bin/../share/yosys/techmap.v
Parsing Verilog input from `/foss/tools/yosys/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.

3.20.2. Continuing TECHMAP pass.
Using extmapper maccmap for cells of type $macc_v2.
  add \signal_in * \carrier_in (16x16 bits, signed)
Using extmapper simplemap for cells of type $adff.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000011111 for cells of type $fa.
Using template $paramod$ebf89ea36a793f0f77858f212141d47c833068ad\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000011111 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~496 debug messages>

3.21. Executing OPT pass (performing simple optimizations).

3.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
<suppressed ~950 debug messages>

3.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2311 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 2191 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 2131 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 2071 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 2041 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 1999 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 1979 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 1969 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 1967 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 1965 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Computing hashes of 1964 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
<suppressed ~1041 debug messages>
Removed a total of 347 cells.

3.21.3. Executing OPT_DFF pass (perform DFF optimizations).

3.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Removed 97 unused cells and 204 unused wires.
<suppressed ~98 debug messages>

3.21.5. Finished fast OPT passes.

3.22. Executing ABC pass (technology mapping using ABC).

3.22.1. Extracting gate netlist of module `\ring_modulator' to `<abc-temp-dir>/input.blif'..

3.22.1.1. Executed ABC.
Extracted 1835 gates and 1867 wires to a netlist network with 32 inputs and 16 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 01:00:48)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_library /tmp/yosys-abc-gT90yw/stdcells.genlib 
ABC: + strash 
ABC: + dretime 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

3.22.1.2. Re-integrating ABC results.
ABC RESULTS:               AND cells:      195
ABC RESULTS:            ANDNOT cells:      548
ABC RESULTS:               MUX cells:        1
ABC RESULTS:              NAND cells:      100
ABC RESULTS:               NOR cells:       63
ABC RESULTS:               NOT cells:       22
ABC RESULTS:                OR cells:      213
ABC RESULTS:             ORNOT cells:       81
ABC RESULTS:              XNOR cells:      140
ABC RESULTS:               XOR cells:      477
ABC RESULTS:        internal signals:     1819
ABC RESULTS:           input signals:       32
ABC RESULTS:          output signals:       16
Removing temp directory.
Removing global temp directory.

3.23. Executing OPT pass (performing simple optimizations).

3.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.

3.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 1872 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Removed a total of 0 cells.

3.23.3. Executing OPT_DFF pass (perform DFF optimizations).

3.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Removed 0 unused cells and 225 unused wires.
<suppressed ~1 debug messages>

3.23.5. Finished fast OPT passes.

3.24. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `ring_modulator'. Setting top module to ring_modulator.

3.24.1. Analyzing design hierarchy..
Top module:  \ring_modulator

3.24.2. Analyzing design hierarchy..
Top module:  \ring_modulator
Removed 0 unused modules.

3.25. Printing statistics.

=== ring_modulator ===

        +----------Local Count, excluding submodules.
        | 
     1832 wires
     1961 wire bits
        6 public wires
       74 public wire bits
        5 ports
       50 port bits
     1872 cells
      548   $_ANDNOT_
      195   $_AND_
       32   $_DFF_PN0_
        1   $_MUX_
      100   $_NAND_
       63   $_NOR_
       22   $_NOT_
       81   $_ORNOT_
      213   $_OR_
      140   $_XNOR_
      477   $_XOR_

3.26. Executing CHECK pass (checking for obvious problems).
Checking module ring_modulator...
Found and reported 0 problems.

4. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell sky130_fd_sc_hd__dfxtp_1 (noninv, pins=3, area=20.02) is a direct match for cell type $_DFF_P_.
  cell sky130_fd_sc_hd__dfrtn_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_NN0_.
  cell sky130_fd_sc_hd__dfrtp_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_PN0_.
  cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
  cell sky130_fd_sc_hd__edfxtp_1 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFFE_PP_.
  cell sky130_fd_sc_hd__dfbbn_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_NNN_.
  cell sky130_fd_sc_hd__dfbbp_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_PNN_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \sky130_fd_sc_hd__dfxtp_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
    \sky130_fd_sc_hd__dfrtn_1 _DFF_NN0_ (.CLK_N( C), .D( D), .Q( Q), .RESET_B( R));
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    \sky130_fd_sc_hd__dfrtp_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
    \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    unmapped dff cell: $_DFFE_NN_
    unmapped dff cell: $_DFFE_NP_
    unmapped dff cell: $_DFFE_PN_
    \sky130_fd_sc_hd__edfxtp_1 _DFFE_PP_ (.CLK( C), .D( D), .DE( E), .Q( Q));
    \sky130_fd_sc_hd__dfbbn_1 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    \sky130_fd_sc_hd__dfbbp_1 _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

4.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
<suppressed ~24 debug messages>
Mapping DFF cells in module `\ring_modulator':
  mapped 32 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_1 cells.

5. Executing ABC pass (technology mapping using ABC).

5.1. Extracting gate netlist of module `\ring_modulator' to `<abc-temp-dir>/input.blif'..

5.1.1. Executed ABC.
Extracted 1840 gates and 1872 wires to a netlist network with 32 inputs and 16 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 01:00:48)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib 
ABC: Parsing finished successfully.  Parsing time =     0.06 sec
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__diode_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_0".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_8".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_8".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_bleeder_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__lpflow_inputisolatch_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" has 334 cells (94 skipped: 63 seq; 13 tri-state; 18 no func; 0 dont_use; 0 with 2 outputs; 0 with 3+ outputs).  Time =     0.09 sec
ABC: Memory =   19.85 MB. Time =     0.09 sec
ABC: Warning: Detected 9 multi-output cells (for example, "sky130_fd_sc_hd__fa_1").
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 
ABC: 
ABC: YOSYS_ABC_DONE 

5.1.2. Re-integrating ABC results.
ABC RESULTS:   sky130_fd_sc_hd__a211o_1 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__a211oi_1 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__a21boi_0 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__a21o_1 cells:        6
ABC RESULTS:   sky130_fd_sc_hd__a21oi_1 cells:       54
ABC RESULTS:   sky130_fd_sc_hd__a22o_1 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__a22oi_1 cells:        9
ABC RESULTS:   sky130_fd_sc_hd__a2bb2oi_1 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__a31oi_1 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__a32o_1 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__a32oi_1 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__and2_0 cells:       37
ABC RESULTS:   sky130_fd_sc_hd__and3_1 cells:       11
ABC RESULTS:   sky130_fd_sc_hd__and4_1 cells:        4
ABC RESULTS:   sky130_fd_sc_hd__clkinv_1 cells:       22
ABC RESULTS:   sky130_fd_sc_hd__lpflow_inputiso1p_1 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__lpflow_isobufsrc_1 cells:       28
ABC RESULTS:   sky130_fd_sc_hd__maj3_1 cells:      142
ABC RESULTS:   sky130_fd_sc_hd__mux2i_1 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__nand2_1 cells:      249
ABC RESULTS:   sky130_fd_sc_hd__nand2b_1 cells:       26
ABC RESULTS:   sky130_fd_sc_hd__nand3_1 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__nand4_1 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__nor2_1 cells:       97
ABC RESULTS:   sky130_fd_sc_hd__nor2b_1 cells:       15
ABC RESULTS:   sky130_fd_sc_hd__nor3_1 cells:       28
ABC RESULTS:   sky130_fd_sc_hd__nor3b_1 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__nor4_1 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__o211ai_1 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__o21a_1 cells:       10
ABC RESULTS:   sky130_fd_sc_hd__o21ai_0 cells:       39
ABC RESULTS:   sky130_fd_sc_hd__o21bai_1 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__o221ai_1 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__o22a_1 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__o22ai_1 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__o311ai_0 cells:        1
ABC RESULTS:   sky130_fd_sc_hd__o31ai_1 cells:        2
ABC RESULTS:   sky130_fd_sc_hd__o32a_1 cells:        3
ABC RESULTS:   sky130_fd_sc_hd__or3_1 cells:        5
ABC RESULTS:   sky130_fd_sc_hd__xnor2_1 cells:      254
ABC RESULTS:   sky130_fd_sc_hd__xnor3_1 cells:       48
ABC RESULTS:   sky130_fd_sc_hd__xor2_1 cells:      118
ABC RESULTS:   sky130_fd_sc_hd__xor3_1 cells:       34
ABC RESULTS:        internal signals:     1824
ABC RESULTS:           input signals:       32
ABC RESULTS:          output signals:       16
Removing temp directory.
Removing global temp directory.
Removed 0 unused cells and 1872 unused wires.

6. Printing statistics.

=== ring_modulator ===

        +----------Local Count, excluding submodules.
        | 
     1287 wires
     1416 wire bits
        6 public wires
       74 public wire bits
        5 ports
       50 port bits
     1327 cells
        1   sky130_fd_sc_hd__a211o_1
        2   sky130_fd_sc_hd__a211oi_1
        4   sky130_fd_sc_hd__a21boi_0
        6   sky130_fd_sc_hd__a21o_1
       54   sky130_fd_sc_hd__a21oi_1
        4   sky130_fd_sc_hd__a22o_1
        9   sky130_fd_sc_hd__a22oi_1
        3   sky130_fd_sc_hd__a2bb2oi_1
        3   sky130_fd_sc_hd__a31oi_1
        1   sky130_fd_sc_hd__a32o_1
        2   sky130_fd_sc_hd__a32oi_1
       37   sky130_fd_sc_hd__and2_0
       11   sky130_fd_sc_hd__and3_1
        4   sky130_fd_sc_hd__and4_1
       22   sky130_fd_sc_hd__clkinv_1
       32   sky130_fd_sc_hd__dfrtp_1
        5   sky130_fd_sc_hd__lpflow_inputiso1p_1
       28   sky130_fd_sc_hd__lpflow_isobufsrc_1
      142   sky130_fd_sc_hd__maj3_1
        3   sky130_fd_sc_hd__mux2i_1
      249   sky130_fd_sc_hd__nand2_1
       26   sky130_fd_sc_hd__nand2b_1
        5   sky130_fd_sc_hd__nand3_1
        5   sky130_fd_sc_hd__nand4_1
       97   sky130_fd_sc_hd__nor2_1
       15   sky130_fd_sc_hd__nor2b_1
       28   sky130_fd_sc_hd__nor3_1
        2   sky130_fd_sc_hd__nor3b_1
        1   sky130_fd_sc_hd__nor4_1
        3   sky130_fd_sc_hd__o211ai_1
       10   sky130_fd_sc_hd__o21a_1
       39   sky130_fd_sc_hd__o21ai_0
        2   sky130_fd_sc_hd__o21bai_1
        1   sky130_fd_sc_hd__o221ai_1
        5   sky130_fd_sc_hd__o22a_1
        1   sky130_fd_sc_hd__o22ai_1
        1   sky130_fd_sc_hd__o311ai_0
        2   sky130_fd_sc_hd__o31ai_1
        3   sky130_fd_sc_hd__o32a_1
        5   sky130_fd_sc_hd__or3_1
      254   sky130_fd_sc_hd__xnor2_1
       48   sky130_fd_sc_hd__xnor3_1
      118   sky130_fd_sc_hd__xor2_1
       34   sky130_fd_sc_hd__xor3_1

7. Executing Verilog backend.

7.1. Executing BMUXMAP pass.

7.2. Executing DEMUXMAP pass.
Dumping module `\ring_modulator'.

End of script. Logfile hash: 41fbf024c3, CPU: user 0.24s system 0.02s, MEM: 62.48 MB peak
Yosys 0.62 (git sha1 7326bb7d6, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
Time spent: 66% 2x abc (0 sec), 7% 1x dfflibmap (0 sec), ...
/foss/designs/ring_modulator > 

=== ring_modulator ===

        +----------Local Count, excluding submodules.
        | 
     1287 wires
     1416 wire bits
        6 public wires
       74 public wire bits
        5 ports
       50 port bits
     1327 cells
        1   sky130_fd_sc_hd__a211o_1
        2   sky130_fd_sc_hd__a211oi_1
        4   sky130_fd_sc_hd__a21boi_0
        6   sky130_fd_sc_hd__a21o_1
       54   sky130_fd_sc_hd__a21oi_1
        4   sky130_fd_sc_hd__a22o_1
        9   sky130_fd_sc_hd__a22oi_1
        3   sky130_fd_sc_hd__a2bb2oi_1
        3   sky130_fd_sc_hd__a31oi_1
        1   sky130_fd_sc_hd__a32o_1
        2   sky130_fd_sc_hd__a32oi_1
       37   sky130_fd_sc_hd__and2_0
       11   sky130_fd_sc_hd__and3_1
        4   sky130_fd_sc_hd__and4_1
       22   sky130_fd_sc_hd__clkinv_1
       32   sky130_fd_sc_hd__dfrtp_1
        5   sky130_fd_sc_hd__lpflow_inputiso1p_1
       28   sky130_fd_sc_hd__lpflow_isobufsrc_1
      142   sky130_fd_sc_hd__maj3_1
        3   sky130_fd_sc_hd__mux2i_1
      249   sky130_fd_sc_hd__nand2_1
       26   sky130_fd_sc_hd__nand2b_1
        5   sky130_fd_sc_hd__nand3_1
        5   sky130_fd_sc_hd__nand4_1
       97   sky130_fd_sc_hd__nor2_1
       15   sky130_fd_sc_hd__nor2b_1
       28   sky130_fd_sc_hd__nor3_1
        2   sky130_fd_sc_hd__nor3b_1
        1   sky130_fd_sc_hd__nor4_1
        3   sky130_fd_sc_hd__o211ai_1
       10   sky130_fd_sc_hd__o21a_1
       39   sky130_fd_sc_hd__o21ai_0
        2   sky130_fd_sc_hd__o21bai_1
        1   sky130_fd_sc_hd__o221ai_1
        5   sky130_fd_sc_hd__o22a_1
        1   sky130_fd_sc_hd__o22ai_1
        1   sky130_fd_sc_hd__o311ai_0
        2   sky130_fd_sc_hd__o31ai_1
        3   sky130_fd_sc_hd__o32a_1
        5   sky130_fd_sc_hd__or3_1
      254   sky130_fd_sc_hd__xnor2_1
       48   sky130_fd_sc_hd__xnor3_1
      118   sky130_fd_sc_hd__xor2_1
       34   sky130_fd_sc_hd__xor3_1

After reviewing this week’s documentation, I understand the Yosys run as a concrete example of the standard synthesis flow: parsing my Verilog, elaborating the hierarchy (so the tool knows which module is the top and how everything connects), then doing logic optimization, and finally technology mapping to the Sky130 standard-cell library.

In my log, Yosys clearly identifies ring_modulator as the top module, converts my always @(posedge clk or negedge rst_n) block into flip-flops with an asynchronous reset, and then hands the combinational logic (dominated by the 16×16 signed multiply) to abc so it can be expressed as real sky130_fd_sc_hd__* cells. This matches the course’s description of “RTL → generic netlist → mapped netlist → optimized netlist,” with Yosys producing a technology-independent representation first and then abc doing the library-aware mapping step.

Following the “What to check after synthesis” guidance from the notebook, I focused on the main sanity checks: warnings, latch inference, and the cell/flip-flop counts in the stat report. My run shows no obvious structural issues (the check pass reports 0 problems), and the final mapped statistics show a fairly large design for such a small module because the multiplier dominates the gate count. That aligns with the course’s rule-of-thumb that arithmetic multiplication is expensive in standard cells and can quickly push the design into the “1000+ cells” range, which is also why the documentation emphasizes using the cell count as an early feasibility/fit metric (e.g., Tiny Tapeout tile sizing guidance). In my case, seeing the mapped sky130_fd_sc_hd__* breakdown gives me a realistic baseline before moving on to place & route and STA, and it helps explain why pipelining or reducing bit-width would be the first knobs to turn if timing or area become tight.

Here can see the ring_modulator_synth.v file output:

ring_modulator_synth.v

/* Generated by Yosys 0.62 (git sha1 7326bb7d6, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3) */

module ring_modulator(clk, rst_n, signal_in, carrier_in, mod_out);
  input clk;
  wire clk;
  input rst_n;
  wire rst_n;
  input [15:0] signal_in;
  wire [15:0] signal_in;
  input [15:0] carrier_in;
  wire [15:0] carrier_in;
  output [15:0] mod_out;
  wire [15:0] mod_out;
  wire _0000_;
  wire _0001_;
  wire _0002_;
  wire _0003_;
  wire _0004_;
  wire _0005_;
  wire _0006_;
  wire _0007_;
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  wire _0846_;
  wire _0847_;
  wire _0848_;
  wire _0849_;
  wire _0850_;
  wire _0851_;
  wire _0852_;
  wire _0853_;
  wire _0854_;
  wire _0855_;
  wire _0856_;
  wire _0857_;
  wire _0858_;
  wire _0859_;
  wire _0860_;
  wire _0861_;
  wire _0862_;
  wire _0863_;
  wire _0864_;
  wire _0865_;
  wire _0866_;
  wire _0867_;
  wire _0868_;
  wire _0869_;
  wire _0870_;
  wire _0871_;
  wire _0872_;
  wire _0873_;
  wire _0874_;
  wire _0875_;
  wire _0876_;
  wire _0877_;
  wire _0878_;
  wire _0879_;
  wire _0880_;
  wire _0881_;
  wire _0882_;
  wire _0883_;
  wire _0884_;
  wire _0885_;
  wire _0886_;
  wire _0887_;
  wire _0888_;
  wire _0889_;
  wire _0890_;
  wire _0891_;
  wire _0892_;
  wire _0893_;
  wire _0894_;
  wire _0895_;
  wire _0896_;
  wire _0897_;
  wire _0898_;
  wire _0899_;
  wire _0900_;
  wire _0901_;
  wire _0902_;
  wire _0903_;
  wire _0904_;
  wire _0905_;
  wire _0906_;
  wire _0907_;
  wire _0908_;
  wire _0909_;
  wire _0910_;
  wire _0911_;
  wire _0912_;
  wire _0913_;
  wire _0914_;
  wire _0915_;
  wire _0916_;
  wire _0917_;
  wire _0918_;
  wire _0919_;
  wire _0920_;
  wire _0921_;
  wire _0922_;
  wire _0923_;
  wire _0924_;
  wire _0925_;
  wire _0926_;
  wire _0927_;
  wire _0928_;
  wire _0929_;
  wire _0930_;
  wire _0931_;
  wire _0932_;
  wire _0933_;
  wire _0934_;
  wire _0935_;
  wire _0936_;
  wire _0937_;
  wire _0938_;
  wire _0939_;
  wire _0940_;
  wire _0941_;
  wire _0942_;
  wire _0943_;
  wire _0944_;
  wire _0945_;
  wire _0946_;
  wire _0947_;
  wire _0948_;
  wire _0949_;
  wire _0950_;
  wire _0951_;
  wire _0952_;
  wire _0953_;
  wire _0954_;
  wire _0955_;
  wire _0956_;
  wire _0957_;
  wire _0958_;
  wire _0959_;
  wire _0960_;
  wire _0961_;
  wire _0962_;
  wire _0963_;
  wire _0964_;
  wire _0965_;
  wire _0966_;
  wire _0967_;
  wire _0968_;
  wire _0969_;
  wire _0970_;
  wire _0971_;
  wire _0972_;
  wire _0973_;
  wire _0974_;
  wire _0975_;
  wire _0976_;
  wire _0977_;
  wire _0978_;
  wire _0979_;
  wire _0980_;
  wire _0981_;
  wire _0982_;
  wire _0983_;
  wire _0984_;
  wire _0985_;
  wire _0986_;
  wire _0987_;
  wire _0988_;
  wire _0989_;
  wire _0990_;
  wire _0991_;
  wire _0992_;
  wire _0993_;
  wire _0994_;
  wire _0995_;
  wire _0996_;
  wire _0997_;
  wire _0998_;
  wire _0999_;
  wire _1000_;
  wire _1001_;
  wire _1002_;
  wire _1003_;
  wire _1004_;
  wire _1005_;
  wire _1006_;
  wire _1007_;
  wire _1008_;
  wire _1009_;
  wire _1010_;
  wire _1011_;
  wire _1012_;
  wire _1013_;
  wire _1014_;
  wire _1015_;
  wire _1016_;
  wire _1017_;
  wire _1018_;
  wire _1019_;
  wire _1020_;
  wire _1021_;
  wire _1022_;
  wire _1023_;
  wire _1024_;
  wire _1025_;
  wire _1026_;
  wire _1027_;
  wire _1028_;
  wire _1029_;
  wire _1030_;
  wire _1031_;
  wire _1032_;
  wire _1033_;
  wire _1034_;
  wire _1035_;
  wire _1036_;
  wire _1037_;
  wire _1038_;
  wire _1039_;
  wire _1040_;
  wire _1041_;
  wire _1042_;
  wire _1043_;
  wire _1044_;
  wire _1045_;
  wire _1046_;
  wire _1047_;
  wire _1048_;
  wire _1049_;
  wire _1050_;
  wire _1051_;
  wire _1052_;
  wire _1053_;
  wire _1054_;
  wire _1055_;
  wire _1056_;
  wire _1057_;
  wire _1058_;
  wire _1059_;
  wire _1060_;
  wire _1061_;
  wire _1062_;
  wire _1063_;
  wire _1064_;
  wire _1065_;
  wire _1066_;
  wire _1067_;
  wire _1068_;
  wire _1069_;
  wire _1070_;
  wire _1071_;
  wire _1072_;
  wire _1073_;
  wire _1074_;
  wire _1075_;
  wire _1076_;
  wire _1077_;
  wire _1078_;
  wire _1079_;
  wire _1080_;
  wire _1081_;
  wire _1082_;
  wire _1083_;
  wire _1084_;
  wire _1085_;
  wire _1086_;
  wire _1087_;
  wire _1088_;
  wire _1089_;
  wire _1090_;
  wire _1091_;
  wire _1092_;
  wire _1093_;
  wire _1094_;
  wire _1095_;
  wire _1096_;
  wire _1097_;
  wire _1098_;
  wire _1099_;
  wire _1100_;
  wire _1101_;
  wire _1102_;
  wire _1103_;
  wire _1104_;
  wire _1105_;
  wire _1106_;
  wire _1107_;
  wire _1108_;
  wire _1109_;
  wire _1110_;
  wire _1111_;
  wire _1112_;
  wire _1113_;
  wire _1114_;
  wire _1115_;
  wire _1116_;
  wire _1117_;
  wire _1118_;
  wire _1119_;
  wire _1120_;
  wire _1121_;
  wire _1122_;
  wire _1123_;
  wire _1124_;
  wire _1125_;
  wire _1126_;
  wire _1127_;
  wire _1128_;
  wire _1129_;
  wire _1130_;
  wire _1131_;
  wire _1132_;
  wire _1133_;
  wire _1134_;
  wire _1135_;
  wire _1136_;
  wire _1137_;
  wire _1138_;
  wire _1139_;
  wire _1140_;
  wire _1141_;
  wire _1142_;
  wire _1143_;
  wire _1144_;
  wire _1145_;
  wire _1146_;
  wire _1147_;
  wire _1148_;
  wire _1149_;
  wire _1150_;
  wire _1151_;
  wire _1152_;
  wire _1153_;
  wire _1154_;
  wire _1155_;
  wire _1156_;
  wire _1157_;
  wire _1158_;
  wire _1159_;
  wire _1160_;
  wire _1161_;
  wire _1162_;
  wire _1163_;
  wire _1164_;
  wire _1165_;
  wire _1166_;
  wire _1167_;
  wire _1168_;
  wire _1169_;
  wire _1170_;
  wire _1171_;
  wire _1172_;
  wire _1173_;
  wire _1174_;
  wire _1175_;
  wire _1176_;
  wire _1177_;
  wire _1178_;
  wire _1179_;
  wire _1180_;
  wire _1181_;
  wire _1182_;
  wire _1183_;
  wire _1184_;
  wire _1185_;
  wire _1186_;
  wire _1187_;
  wire _1188_;
  wire _1189_;
  wire _1190_;
  wire _1191_;
  wire _1192_;
  wire _1193_;
  wire _1194_;
  wire _1195_;
  wire _1196_;
  wire _1197_;
  wire _1198_;
  wire _1199_;
  wire _1200_;
  wire _1201_;
  wire _1202_;
  wire _1203_;
  wire _1204_;
  wire _1205_;
  wire _1206_;
  wire _1207_;
  wire _1208_;
  wire _1209_;
  wire _1210_;
  wire _1211_;
  wire _1212_;
  wire _1213_;
  wire _1214_;
  wire _1215_;
  wire _1216_;
  wire _1217_;
  wire _1218_;
  wire _1219_;
  wire _1220_;
  wire _1221_;
  wire _1222_;
  wire _1223_;
  wire _1224_;
  wire _1225_;
  wire _1226_;
  wire _1227_;
  wire _1228_;
  wire _1229_;
  wire _1230_;
  wire _1231_;
  wire _1232_;
  wire _1233_;
  wire _1234_;
  wire _1235_;
  wire _1236_;
  wire _1237_;
  wire _1238_;
  wire _1239_;
  wire _1240_;
  wire _1241_;
  wire _1242_;
  wire _1243_;
  wire _1244_;
  wire _1245_;
  wire _1246_;
  wire _1247_;
  wire _1248_;
  wire _1249_;
  wire _1250_;
  wire _1251_;
  wire _1252_;
  wire _1253_;
  wire _1254_;
  wire _1255_;
  wire _1256_;
  wire _1257_;
  wire _1258_;
  wire _1259_;
  wire _1260_;
  wire _1261_;
  wire _1262_;
  wire _1263_;
  wire _1264_;
  wire _1265_;
  wire _1266_;
  wire _1267_;
  wire _1268_;
  wire _1269_;
  wire _1270_;
  wire _1271_;
  wire _1272_;
  wire _1273_;
  wire _1274_;
  wire _1275_;
  wire _1276_;
  wire _1277_;
  wire _1278_;
  wire [30:0] _1279_;
  wire [31:0] _1280_;
  wire [23:0] product;
  sky130_fd_sc_hd__clkinv_1 _1281_ (
    .A(carrier_in[15]),
    .Y(_0726_)
  );
  sky130_fd_sc_hd__a22o_1 _1282_ (
    .A1(signal_in[0]),
    .A2(carrier_in[11]),
    .B1(carrier_in[10]),
    .B2(signal_in[1]),
    .X(_0737_)
  );
  sky130_fd_sc_hd__nand2_1 _1283_ (
    .A(signal_in[1]),
    .B(carrier_in[11]),
    .Y(_0748_)
  );
  sky130_fd_sc_hd__nand2_1 _1284_ (
    .A(signal_in[0]),
    .B(carrier_in[10]),
    .Y(_0759_)
  );
  sky130_fd_sc_hd__nor2_1 _1285_ (
    .A(_0748_),
    .B(_0759_),
    .Y(_0770_)
  );
  sky130_fd_sc_hd__nand4_1 _1286_ (
    .A(signal_in[1]),
    .B(signal_in[0]),
    .C(carrier_in[11]),
    .D(carrier_in[10]),
    .Y(_0780_)
  );
  sky130_fd_sc_hd__nand2_1 _1287_ (
    .A(_0737_),
    .B(_0780_),
    .Y(_0791_)
  );
  sky130_fd_sc_hd__nand2_1 _1288_ (
    .A(signal_in[1]),
    .B(carrier_in[9]),
    .Y(_0802_)
  );
  sky130_fd_sc_hd__nand2_1 _1289_ (
    .A(signal_in[2]),
    .B(carrier_in[8]),
    .Y(_0813_)
  );
  sky130_fd_sc_hd__nand2_1 _1290_ (
    .A(signal_in[2]),
    .B(carrier_in[9]),
    .Y(_0824_)
  );
  sky130_fd_sc_hd__nand2_1 _1291_ (
    .A(signal_in[3]),
    .B(carrier_in[7]),
    .Y(_0835_)
  );
  sky130_fd_sc_hd__maj3_1 _1292_ (
    .A(_0802_),
    .B(_0813_),
    .C(_0835_),
    .X(_0846_)
  );
  sky130_fd_sc_hd__nand2_1 _1293_ (
    .A(signal_in[3]),
    .B(carrier_in[8]),
    .Y(_0856_)
  );
  sky130_fd_sc_hd__nand2_1 _1294_ (
    .A(signal_in[3]),
    .B(carrier_in[9]),
    .Y(_0867_)
  );
  sky130_fd_sc_hd__nand2_1 _1295_ (
    .A(signal_in[4]),
    .B(carrier_in[7]),
    .Y(_0878_)
  );
  sky130_fd_sc_hd__xnor3_1 _1296_ (
    .A(_0824_),
    .B(_0856_),
    .C(_0878_),
    .X(_0889_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1297_ (
    .A(_0889_),
    .SLEEP(_0846_),
    .X(_0900_)
  );
  sky130_fd_sc_hd__xnor2_1 _1298_ (
    .A(_0846_),
    .B(_0889_),
    .Y(_0911_)
  );
  sky130_fd_sc_hd__nand3_1 _1299_ (
    .A(_0737_),
    .B(_0780_),
    .C(_0911_),
    .Y(_0922_)
  );
  sky130_fd_sc_hd__clkinv_1 _1300_ (
    .A(_0922_),
    .Y(_0932_)
  );
  sky130_fd_sc_hd__nand2_1 _1301_ (
    .A(signal_in[0]),
    .B(carrier_in[12]),
    .Y(_0943_)
  );
  sky130_fd_sc_hd__nand2_1 _1302_ (
    .A(signal_in[1]),
    .B(carrier_in[12]),
    .Y(_0954_)
  );
  sky130_fd_sc_hd__xor2_1 _1303_ (
    .A(_0748_),
    .B(_0943_),
    .X(_0965_)
  );
  sky130_fd_sc_hd__nand2_1 _1304_ (
    .A(signal_in[2]),
    .B(carrier_in[10]),
    .Y(_0976_)
  );
  sky130_fd_sc_hd__xnor2_1 _1305_ (
    .A(_0965_),
    .B(_0976_),
    .Y(_0987_)
  );
  sky130_fd_sc_hd__maj3_1 _1306_ (
    .A(_0824_),
    .B(_0856_),
    .C(_0878_),
    .X(_0998_)
  );
  sky130_fd_sc_hd__nand2_1 _1307_ (
    .A(signal_in[4]),
    .B(carrier_in[8]),
    .Y(_1008_)
  );
  sky130_fd_sc_hd__nand2_1 _1308_ (
    .A(signal_in[4]),
    .B(carrier_in[9]),
    .Y(_1019_)
  );
  sky130_fd_sc_hd__nand2_1 _1309_ (
    .A(signal_in[5]),
    .B(carrier_in[7]),
    .Y(_1030_)
  );
  sky130_fd_sc_hd__xnor3_1 _1310_ (
    .A(_0867_),
    .B(_1008_),
    .C(_1030_),
    .X(_1041_)
  );
  sky130_fd_sc_hd__nand2_1 _1311_ (
    .A(_0770_),
    .B(_1041_),
    .Y(_1052_)
  );
  sky130_fd_sc_hd__nor2_1 _1312_ (
    .A(_0770_),
    .B(_1041_),
    .Y(_1063_)
  );
  sky130_fd_sc_hd__xnor2_1 _1313_ (
    .A(_0780_),
    .B(_1041_),
    .Y(_1074_)
  );
  sky130_fd_sc_hd__xnor2_1 _1314_ (
    .A(_0998_),
    .B(_1074_),
    .Y(_1084_)
  );
  sky130_fd_sc_hd__nand2_1 _1315_ (
    .A(_0987_),
    .B(_1084_),
    .Y(_1095_)
  );
  sky130_fd_sc_hd__xor2_1 _1316_ (
    .A(_0987_),
    .B(_1084_),
    .X(_1106_)
  );
  sky130_fd_sc_hd__xnor2_1 _1317_ (
    .A(_0932_),
    .B(_1106_),
    .Y(_1117_)
  );
  sky130_fd_sc_hd__nand2_1 _1318_ (
    .A(signal_in[5]),
    .B(carrier_in[5]),
    .Y(_1128_)
  );
  sky130_fd_sc_hd__nand2_1 _1319_ (
    .A(signal_in[4]),
    .B(carrier_in[6]),
    .Y(_1139_)
  );
  sky130_fd_sc_hd__nand2_1 _1320_ (
    .A(signal_in[5]),
    .B(carrier_in[6]),
    .Y(_1149_)
  );
  sky130_fd_sc_hd__nand2_1 _1321_ (
    .A(signal_in[4]),
    .B(carrier_in[5]),
    .Y(_1160_)
  );
  sky130_fd_sc_hd__nand2_1 _1322_ (
    .A(signal_in[6]),
    .B(carrier_in[4]),
    .Y(_1171_)
  );
  sky130_fd_sc_hd__maj3_1 _1323_ (
    .A(_1128_),
    .B(_1139_),
    .C(_1171_),
    .X(_1182_)
  );
  sky130_fd_sc_hd__clkinv_1 _1324_ (
    .A(_1182_),
    .Y(_1193_)
  );
  sky130_fd_sc_hd__nand2_1 _1325_ (
    .A(signal_in[6]),
    .B(carrier_in[5]),
    .Y(_1204_)
  );
  sky130_fd_sc_hd__nand2_1 _1326_ (
    .A(signal_in[6]),
    .B(carrier_in[6]),
    .Y(_1214_)
  );
  sky130_fd_sc_hd__nand2_1 _1327_ (
    .A(signal_in[7]),
    .B(carrier_in[4]),
    .Y(_1225_)
  );
  sky130_fd_sc_hd__xnor3_1 _1328_ (
    .A(_1149_),
    .B(_1204_),
    .C(_1225_),
    .X(_1236_)
  );
  sky130_fd_sc_hd__xor2_1 _1329_ (
    .A(_1182_),
    .B(_1236_),
    .X(_1247_)
  );
  sky130_fd_sc_hd__nand2_1 _1330_ (
    .A(signal_in[10]),
    .B(carrier_in[1]),
    .Y(_1258_)
  );
  sky130_fd_sc_hd__nand2_1 _1331_ (
    .A(signal_in[9]),
    .B(carrier_in[2]),
    .Y(_1269_)
  );
  sky130_fd_sc_hd__nand2_1 _1332_ (
    .A(signal_in[8]),
    .B(carrier_in[3]),
    .Y(_0000_)
  );
  sky130_fd_sc_hd__nand2_1 _1333_ (
    .A(signal_in[8]),
    .B(carrier_in[2]),
    .Y(_0011_)
  );
  sky130_fd_sc_hd__xor2_1 _1334_ (
    .A(_1269_),
    .B(_0000_),
    .X(_0022_)
  );
  sky130_fd_sc_hd__xnor2_1 _1335_ (
    .A(_1258_),
    .B(_0022_),
    .Y(_0033_)
  );
  sky130_fd_sc_hd__maj3_1 _1336_ (
    .A(_1193_),
    .B(_1236_),
    .C(_0033_),
    .X(_0044_)
  );
  sky130_fd_sc_hd__maj3_1 _1337_ (
    .A(_1149_),
    .B(_1204_),
    .C(_1225_),
    .X(_0055_)
  );
  sky130_fd_sc_hd__nand2_1 _1338_ (
    .A(signal_in[7]),
    .B(carrier_in[5]),
    .Y(_0065_)
  );
  sky130_fd_sc_hd__nand2_1 _1339_ (
    .A(signal_in[7]),
    .B(carrier_in[6]),
    .Y(_0076_)
  );
  sky130_fd_sc_hd__xnor2_1 _1340_ (
    .A(_1214_),
    .B(_0065_),
    .Y(_0087_)
  );
  sky130_fd_sc_hd__nand2_1 _1341_ (
    .A(signal_in[8]),
    .B(carrier_in[4]),
    .Y(_0098_)
  );
  sky130_fd_sc_hd__xnor2_1 _1342_ (
    .A(_0087_),
    .B(_0098_),
    .Y(_0109_)
  );
  sky130_fd_sc_hd__nand2_1 _1343_ (
    .A(signal_in[11]),
    .B(carrier_in[1]),
    .Y(_0119_)
  );
  sky130_fd_sc_hd__nand2_1 _1344_ (
    .A(signal_in[10]),
    .B(carrier_in[3]),
    .Y(_0130_)
  );
  sky130_fd_sc_hd__a22o_1 _1345_ (
    .A1(signal_in[9]),
    .A2(carrier_in[3]),
    .B1(carrier_in[2]),
    .B2(signal_in[10]),
    .X(_0141_)
  );
  sky130_fd_sc_hd__o21ai_0 _1346_ (
    .A1(_1269_),
    .A2(_0130_),
    .B1(_0141_),
    .Y(_0152_)
  );
  sky130_fd_sc_hd__xnor2_1 _1347_ (
    .A(_0119_),
    .B(_0152_),
    .Y(_0163_)
  );
  sky130_fd_sc_hd__xnor3_1 _1348_ (
    .A(_0055_),
    .B(_0109_),
    .C(_0163_),
    .X(_0173_)
  );
  sky130_fd_sc_hd__xnor2_1 _1349_ (
    .A(_0900_),
    .B(_0173_),
    .Y(_0184_)
  );
  sky130_fd_sc_hd__xnor2_1 _1350_ (
    .A(_0044_),
    .B(_0184_),
    .Y(_0195_)
  );
  sky130_fd_sc_hd__maj3_1 _1351_ (
    .A(_0932_),
    .B(_1106_),
    .C(_0195_),
    .X(_0206_)
  );
  sky130_fd_sc_hd__nand2_1 _1352_ (
    .A(carrier_in[13]),
    .B(signal_in[0]),
    .Y(_0217_)
  );
  sky130_fd_sc_hd__nand2_1 _1353_ (
    .A(signal_in[3]),
    .B(carrier_in[10]),
    .Y(_0227_)
  );
  sky130_fd_sc_hd__nand2_1 _1354_ (
    .A(signal_in[2]),
    .B(carrier_in[11]),
    .Y(_0238_)
  );
  sky130_fd_sc_hd__nand2_1 _1355_ (
    .A(signal_in[2]),
    .B(carrier_in[12]),
    .Y(_0249_)
  );
  sky130_fd_sc_hd__xor3_1 _1356_ (
    .A(_0954_),
    .B(_0227_),
    .C(_0238_),
    .X(_0260_)
  );
  sky130_fd_sc_hd__nor2_1 _1357_ (
    .A(_0217_),
    .B(_0260_),
    .Y(_0271_)
  );
  sky130_fd_sc_hd__xor2_1 _1358_ (
    .A(_0217_),
    .B(_0260_),
    .X(_0281_)
  );
  sky130_fd_sc_hd__maj3_1 _1359_ (
    .A(_0867_),
    .B(_1008_),
    .C(_1030_),
    .X(_0292_)
  );
  sky130_fd_sc_hd__nand2_1 _1360_ (
    .A(signal_in[5]),
    .B(carrier_in[8]),
    .Y(_0303_)
  );
  sky130_fd_sc_hd__nand2_1 _1361_ (
    .A(signal_in[5]),
    .B(carrier_in[9]),
    .Y(_0314_)
  );
  sky130_fd_sc_hd__nand2_1 _1362_ (
    .A(signal_in[6]),
    .B(carrier_in[7]),
    .Y(_0324_)
  );
  sky130_fd_sc_hd__xor3_1 _1363_ (
    .A(_1019_),
    .B(_0303_),
    .C(_0324_),
    .X(_0335_)
  );
  sky130_fd_sc_hd__maj3_1 _1364_ (
    .A(_0748_),
    .B(_0943_),
    .C(_0976_),
    .X(_0346_)
  );
  sky130_fd_sc_hd__xnor2_1 _1365_ (
    .A(_0335_),
    .B(_0346_),
    .Y(_0356_)
  );
  sky130_fd_sc_hd__xor2_1 _1366_ (
    .A(_0292_),
    .B(_0356_),
    .X(_0367_)
  );
  sky130_fd_sc_hd__nand2_1 _1367_ (
    .A(_0281_),
    .B(_0367_),
    .Y(_0371_)
  );
  sky130_fd_sc_hd__xnor2_1 _1368_ (
    .A(_0281_),
    .B(_0367_),
    .Y(_0372_)
  );
  sky130_fd_sc_hd__xor2_1 _1369_ (
    .A(_1095_),
    .B(_0372_),
    .X(_0373_)
  );
  sky130_fd_sc_hd__maj3_1 _1370_ (
    .A(_0055_),
    .B(_0109_),
    .C(_0163_),
    .X(_0374_)
  );
  sky130_fd_sc_hd__maj3_1 _1371_ (
    .A(_1214_),
    .B(_0065_),
    .C(_0098_),
    .X(_0375_)
  );
  sky130_fd_sc_hd__nand2_1 _1372_ (
    .A(signal_in[8]),
    .B(carrier_in[5]),
    .Y(_0376_)
  );
  sky130_fd_sc_hd__nand2_1 _1373_ (
    .A(signal_in[8]),
    .B(carrier_in[6]),
    .Y(_0377_)
  );
  sky130_fd_sc_hd__nand2_1 _1374_ (
    .A(signal_in[9]),
    .B(carrier_in[4]),
    .Y(_0378_)
  );
  sky130_fd_sc_hd__xnor3_1 _1375_ (
    .A(_0076_),
    .B(_0376_),
    .C(_0378_),
    .X(_0379_)
  );
  sky130_fd_sc_hd__clkinv_1 _1376_ (
    .A(_0379_),
    .Y(_0380_)
  );
  sky130_fd_sc_hd__xor2_1 _1377_ (
    .A(_0375_),
    .B(_0379_),
    .X(_0381_)
  );
  sky130_fd_sc_hd__nand2_1 _1378_ (
    .A(signal_in[12]),
    .B(carrier_in[1]),
    .Y(_0382_)
  );
  sky130_fd_sc_hd__nand2_1 _1379_ (
    .A(signal_in[11]),
    .B(carrier_in[2]),
    .Y(_0383_)
  );
  sky130_fd_sc_hd__nand2_1 _1380_ (
    .A(signal_in[11]),
    .B(carrier_in[3]),
    .Y(_0384_)
  );
  sky130_fd_sc_hd__xnor2_1 _1381_ (
    .A(_0130_),
    .B(_0383_),
    .Y(_0385_)
  );
  sky130_fd_sc_hd__xnor2_1 _1382_ (
    .A(_0382_),
    .B(_0385_),
    .Y(_0386_)
  );
  sky130_fd_sc_hd__xnor2_1 _1383_ (
    .A(_0381_),
    .B(_0386_),
    .Y(_0387_)
  );
  sky130_fd_sc_hd__o21a_1 _1384_ (
    .A1(_0998_),
    .A2(_1063_),
    .B1(_1052_),
    .X(_0388_)
  );
  sky130_fd_sc_hd__xor3_1 _1385_ (
    .A(_0374_),
    .B(_0387_),
    .C(_0388_),
    .X(_0389_)
  );
  sky130_fd_sc_hd__xnor2_1 _1386_ (
    .A(_0373_),
    .B(_0389_),
    .Y(_0390_)
  );
  sky130_fd_sc_hd__xnor2_1 _1387_ (
    .A(_0206_),
    .B(_0390_),
    .Y(_0391_)
  );
  sky130_fd_sc_hd__nand2_1 _1388_ (
    .A(signal_in[12]),
    .B(carrier_in[0]),
    .Y(_0392_)
  );
  sky130_fd_sc_hd__maj3_1 _1389_ (
    .A(_1258_),
    .B(_1269_),
    .C(_0000_),
    .X(_0393_)
  );
  sky130_fd_sc_hd__nor2_1 _1390_ (
    .A(_0392_),
    .B(_0393_),
    .Y(_0394_)
  );
  sky130_fd_sc_hd__nand2_1 _1391_ (
    .A(signal_in[13]),
    .B(carrier_in[0]),
    .Y(_0395_)
  );
  sky130_fd_sc_hd__o22a_1 _1392_ (
    .A1(_1269_),
    .A2(_0130_),
    .B1(_0152_),
    .B2(_0119_),
    .X(_0396_)
  );
  sky130_fd_sc_hd__nor2_1 _1393_ (
    .A(_0395_),
    .B(_0396_),
    .Y(_0397_)
  );
  sky130_fd_sc_hd__xnor2_1 _1394_ (
    .A(_0395_),
    .B(_0396_),
    .Y(_0398_)
  );
  sky130_fd_sc_hd__maj3_1 _1395_ (
    .A(_0900_),
    .B(_0044_),
    .C(_0173_),
    .X(_0399_)
  );
  sky130_fd_sc_hd__nand2b_1 _1396_ (
    .A_N(_0398_),
    .B(_0399_),
    .Y(_0400_)
  );
  sky130_fd_sc_hd__xor2_1 _1397_ (
    .A(_0398_),
    .B(_0399_),
    .X(_0401_)
  );
  sky130_fd_sc_hd__xnor2_1 _1398_ (
    .A(_0394_),
    .B(_0401_),
    .Y(_0402_)
  );
  sky130_fd_sc_hd__maj3_1 _1399_ (
    .A(_0206_),
    .B(_0390_),
    .C(_0402_),
    .X(_0403_)
  );
  sky130_fd_sc_hd__maj3_1 _1400_ (
    .A(_1095_),
    .B(_0372_),
    .C(_0389_),
    .X(_0404_)
  );
  sky130_fd_sc_hd__a22oi_1 _1401_ (
    .A1(signal_in[1]),
    .A2(carrier_in[13]),
    .B1(signal_in[0]),
    .B2(carrier_in[14]),
    .Y(_0405_)
  );
  sky130_fd_sc_hd__nand2_1 _1402_ (
    .A(signal_in[1]),
    .B(carrier_in[14]),
    .Y(_0406_)
  );
  sky130_fd_sc_hd__and4_1 _1403_ (
    .A(signal_in[1]),
    .B(carrier_in[14]),
    .C(carrier_in[13]),
    .D(signal_in[0]),
    .X(_0407_)
  );
  sky130_fd_sc_hd__nor2_1 _1404_ (
    .A(_0405_),
    .B(_0407_),
    .Y(_0408_)
  );
  sky130_fd_sc_hd__nand2_1 _1405_ (
    .A(signal_in[4]),
    .B(carrier_in[10]),
    .Y(_0409_)
  );
  sky130_fd_sc_hd__nand2_1 _1406_ (
    .A(signal_in[3]),
    .B(carrier_in[11]),
    .Y(_0410_)
  );
  sky130_fd_sc_hd__and2_0 _1407_ (
    .A(carrier_in[12]),
    .B(signal_in[3]),
    .X(_0411_)
  );
  sky130_fd_sc_hd__xnor3_1 _1408_ (
    .A(_0249_),
    .B(_0409_),
    .C(_0410_),
    .X(_0412_)
  );
  sky130_fd_sc_hd__nand2_1 _1409_ (
    .A(_0408_),
    .B(_0412_),
    .Y(_0413_)
  );
  sky130_fd_sc_hd__xnor2_1 _1410_ (
    .A(_0408_),
    .B(_0412_),
    .Y(_0414_)
  );
  sky130_fd_sc_hd__nor3_1 _1411_ (
    .A(_0217_),
    .B(_0260_),
    .C(_0414_),
    .Y(_0415_)
  );
  sky130_fd_sc_hd__xnor2_1 _1412_ (
    .A(_0271_),
    .B(_0414_),
    .Y(_0416_)
  );
  sky130_fd_sc_hd__maj3_1 _1413_ (
    .A(_1019_),
    .B(_0303_),
    .C(_0324_),
    .X(_0417_)
  );
  sky130_fd_sc_hd__nand2_1 _1414_ (
    .A(signal_in[6]),
    .B(carrier_in[8]),
    .Y(_0418_)
  );
  sky130_fd_sc_hd__nand2_1 _1415_ (
    .A(carrier_in[9]),
    .B(signal_in[6]),
    .Y(_0419_)
  );
  sky130_fd_sc_hd__xnor2_1 _1416_ (
    .A(_0314_),
    .B(_0418_),
    .Y(_0420_)
  );
  sky130_fd_sc_hd__nand2_1 _1417_ (
    .A(signal_in[7]),
    .B(carrier_in[7]),
    .Y(_0421_)
  );
  sky130_fd_sc_hd__xnor3_1 _1418_ (
    .A(_0314_),
    .B(_0418_),
    .C(_0421_),
    .X(_0422_)
  );
  sky130_fd_sc_hd__xnor2_1 _1419_ (
    .A(_0420_),
    .B(_0421_),
    .Y(_0423_)
  );
  sky130_fd_sc_hd__maj3_1 _1420_ (
    .A(_0954_),
    .B(_0227_),
    .C(_0238_),
    .X(_0424_)
  );
  sky130_fd_sc_hd__xnor2_1 _1421_ (
    .A(_0422_),
    .B(_0424_),
    .Y(_0425_)
  );
  sky130_fd_sc_hd__xnor2_1 _1422_ (
    .A(_0417_),
    .B(_0425_),
    .Y(_0426_)
  );
  sky130_fd_sc_hd__xnor2_1 _1423_ (
    .A(_0416_),
    .B(_0426_),
    .Y(_0427_)
  );
  sky130_fd_sc_hd__maj3_1 _1424_ (
    .A(_0375_),
    .B(_0380_),
    .C(_0386_),
    .X(_0428_)
  );
  sky130_fd_sc_hd__maj3_1 _1425_ (
    .A(_0076_),
    .B(_0376_),
    .C(_0378_),
    .X(_0429_)
  );
  sky130_fd_sc_hd__nand2_1 _1426_ (
    .A(signal_in[9]),
    .B(carrier_in[5]),
    .Y(_0430_)
  );
  sky130_fd_sc_hd__nand2_1 _1427_ (
    .A(carrier_in[6]),
    .B(signal_in[9]),
    .Y(_0431_)
  );
  sky130_fd_sc_hd__nand2_1 _1428_ (
    .A(signal_in[10]),
    .B(carrier_in[4]),
    .Y(_0432_)
  );
  sky130_fd_sc_hd__xnor3_1 _1429_ (
    .A(_0377_),
    .B(_0430_),
    .C(_0432_),
    .X(_0433_)
  );
  sky130_fd_sc_hd__clkinv_1 _1430_ (
    .A(_0433_),
    .Y(_0434_)
  );
  sky130_fd_sc_hd__xor2_1 _1431_ (
    .A(_0429_),
    .B(_0433_),
    .X(_0435_)
  );
  sky130_fd_sc_hd__nand2_1 _1432_ (
    .A(signal_in[13]),
    .B(carrier_in[1]),
    .Y(_0436_)
  );
  sky130_fd_sc_hd__nand2_1 _1433_ (
    .A(signal_in[12]),
    .B(carrier_in[2]),
    .Y(_0437_)
  );
  sky130_fd_sc_hd__nand2_1 _1434_ (
    .A(carrier_in[3]),
    .B(signal_in[12]),
    .Y(_0438_)
  );
  sky130_fd_sc_hd__xnor2_1 _1435_ (
    .A(_0384_),
    .B(_0437_),
    .Y(_0439_)
  );
  sky130_fd_sc_hd__xnor2_1 _1436_ (
    .A(_0436_),
    .B(_0439_),
    .Y(_0440_)
  );
  sky130_fd_sc_hd__xnor2_1 _1437_ (
    .A(_0435_),
    .B(_0440_),
    .Y(_0441_)
  );
  sky130_fd_sc_hd__maj3_1 _1438_ (
    .A(_0292_),
    .B(_0335_),
    .C(_0346_),
    .X(_0442_)
  );
  sky130_fd_sc_hd__xor3_1 _1439_ (
    .A(_0428_),
    .B(_0441_),
    .C(_0442_),
    .X(_0443_)
  );
  sky130_fd_sc_hd__xnor3_1 _1440_ (
    .A(_0371_),
    .B(_0427_),
    .C(_0443_),
    .X(_0444_)
  );
  sky130_fd_sc_hd__nand2b_1 _1441_ (
    .A_N(_0404_),
    .B(_0444_),
    .Y(_0445_)
  );
  sky130_fd_sc_hd__xnor2_1 _1442_ (
    .A(_0404_),
    .B(_0444_),
    .Y(_0446_)
  );
  sky130_fd_sc_hd__nand2_1 _1443_ (
    .A(signal_in[14]),
    .B(carrier_in[0]),
    .Y(_0447_)
  );
  sky130_fd_sc_hd__maj3_1 _1444_ (
    .A(_0130_),
    .B(_0382_),
    .C(_0383_),
    .X(_0448_)
  );
  sky130_fd_sc_hd__nor2_1 _1445_ (
    .A(_0447_),
    .B(_0448_),
    .Y(_0449_)
  );
  sky130_fd_sc_hd__xnor2_1 _1446_ (
    .A(_0447_),
    .B(_0448_),
    .Y(_0450_)
  );
  sky130_fd_sc_hd__maj3_1 _1447_ (
    .A(_0374_),
    .B(_0387_),
    .C(_0388_),
    .X(_0451_)
  );
  sky130_fd_sc_hd__xnor2_1 _1448_ (
    .A(_0450_),
    .B(_0451_),
    .Y(_0452_)
  );
  sky130_fd_sc_hd__xnor2_1 _1449_ (
    .A(_0397_),
    .B(_0452_),
    .Y(_0453_)
  );
  sky130_fd_sc_hd__nand2_1 _1450_ (
    .A(_0446_),
    .B(_0453_),
    .Y(_0454_)
  );
  sky130_fd_sc_hd__xor2_1 _1451_ (
    .A(_0446_),
    .B(_0453_),
    .X(_0455_)
  );
  sky130_fd_sc_hd__xnor2_1 _1452_ (
    .A(_0403_),
    .B(_0455_),
    .Y(_0456_)
  );
  sky130_fd_sc_hd__o31ai_1 _1453_ (
    .A1(_0392_),
    .A2(_0393_),
    .A3(_0401_),
    .B1(_0400_),
    .Y(_0457_)
  );
  sky130_fd_sc_hd__maj3_1 _1454_ (
    .A(_0403_),
    .B(_0455_),
    .C(_0457_),
    .X(_0458_)
  );
  sky130_fd_sc_hd__o32a_1 _1455_ (
    .A1(_0395_),
    .A2(_0396_),
    .A3(_0452_),
    .B1(_0451_),
    .B2(_0450_),
    .X(_0459_)
  );
  sky130_fd_sc_hd__nand2_1 _1456_ (
    .A(_0445_),
    .B(_0454_),
    .Y(_0460_)
  );
  sky130_fd_sc_hd__nand2_1 _1457_ (
    .A(carrier_in[0]),
    .B(signal_in[15]),
    .Y(_0461_)
  );
  sky130_fd_sc_hd__maj3_1 _1458_ (
    .A(_0384_),
    .B(_0436_),
    .C(_0437_),
    .X(_0462_)
  );
  sky130_fd_sc_hd__xor2_1 _1459_ (
    .A(_0461_),
    .B(_0462_),
    .X(_0463_)
  );
  sky130_fd_sc_hd__xnor2_1 _1460_ (
    .A(_0726_),
    .B(_0463_),
    .Y(_0464_)
  );
  sky130_fd_sc_hd__clkinv_1 _1461_ (
    .A(_0464_),
    .Y(_0465_)
  );
  sky130_fd_sc_hd__maj3_1 _1462_ (
    .A(_0428_),
    .B(_0441_),
    .C(_0442_),
    .X(_0466_)
  );
  sky130_fd_sc_hd__xnor2_1 _1463_ (
    .A(_0464_),
    .B(_0466_),
    .Y(_0467_)
  );
  sky130_fd_sc_hd__nand2_1 _1464_ (
    .A(_0449_),
    .B(_0467_),
    .Y(_0468_)
  );
  sky130_fd_sc_hd__xor2_1 _1465_ (
    .A(_0449_),
    .B(_0467_),
    .X(_0469_)
  );
  sky130_fd_sc_hd__maj3_1 _1466_ (
    .A(_0371_),
    .B(_0427_),
    .C(_0443_),
    .X(_0470_)
  );
  sky130_fd_sc_hd__maj3_1 _1467_ (
    .A(_0429_),
    .B(_0434_),
    .C(_0440_),
    .X(_0471_)
  );
  sky130_fd_sc_hd__nand2_1 _1468_ (
    .A(carrier_in[1]),
    .B(signal_in[14]),
    .Y(_0472_)
  );
  sky130_fd_sc_hd__nand2_1 _1469_ (
    .A(carrier_in[2]),
    .B(signal_in[13]),
    .Y(_0473_)
  );
  sky130_fd_sc_hd__xor2_1 _1470_ (
    .A(_0438_),
    .B(_0473_),
    .X(_0474_)
  );
  sky130_fd_sc_hd__xnor2_1 _1471_ (
    .A(_0472_),
    .B(_0474_),
    .Y(_0475_)
  );
  sky130_fd_sc_hd__maj3_1 _1472_ (
    .A(_0377_),
    .B(_0430_),
    .C(_0432_),
    .X(_0476_)
  );
  sky130_fd_sc_hd__nand2_1 _1473_ (
    .A(carrier_in[4]),
    .B(signal_in[11]),
    .Y(_0477_)
  );
  sky130_fd_sc_hd__nand2_1 _1474_ (
    .A(carrier_in[5]),
    .B(signal_in[10]),
    .Y(_0478_)
  );
  sky130_fd_sc_hd__nand2_1 _1475_ (
    .A(carrier_in[6]),
    .B(signal_in[10]),
    .Y(_0479_)
  );
  sky130_fd_sc_hd__xnor3_1 _1476_ (
    .A(_0431_),
    .B(_0477_),
    .C(_0478_),
    .X(_0480_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1477_ (
    .A(_0480_),
    .SLEEP(_0476_),
    .X(_0481_)
  );
  sky130_fd_sc_hd__xnor2_1 _1478_ (
    .A(_0476_),
    .B(_0480_),
    .Y(_0482_)
  );
  sky130_fd_sc_hd__xnor2_1 _1479_ (
    .A(_0475_),
    .B(_0482_),
    .Y(_0483_)
  );
  sky130_fd_sc_hd__maj3_1 _1480_ (
    .A(_0417_),
    .B(_0423_),
    .C(_0424_),
    .X(_0484_)
  );
  sky130_fd_sc_hd__xor3_1 _1481_ (
    .A(_0471_),
    .B(_0483_),
    .C(_0484_),
    .X(_0485_)
  );
  sky130_fd_sc_hd__a21oi_1 _1482_ (
    .A1(_0416_),
    .A2(_0426_),
    .B1(_0415_),
    .Y(_0486_)
  );
  sky130_fd_sc_hd__o22a_1 _1483_ (
    .A1(_0303_),
    .A2(_0419_),
    .B1(_0420_),
    .B2(_0421_),
    .X(_0487_)
  );
  sky130_fd_sc_hd__and2_0 _1484_ (
    .A(carrier_in[7]),
    .B(signal_in[8]),
    .X(_0488_)
  );
  sky130_fd_sc_hd__and2_0 _1485_ (
    .A(carrier_in[8]),
    .B(signal_in[7]),
    .X(_0489_)
  );
  sky130_fd_sc_hd__nand2_1 _1486_ (
    .A(carrier_in[9]),
    .B(signal_in[7]),
    .Y(_0490_)
  );
  sky130_fd_sc_hd__xnor2_1 _1487_ (
    .A(_0419_),
    .B(_0489_),
    .Y(_0491_)
  );
  sky130_fd_sc_hd__xnor3_1 _1488_ (
    .A(_0419_),
    .B(_0488_),
    .C(_0489_),
    .X(_0492_)
  );
  sky130_fd_sc_hd__xnor2_1 _1489_ (
    .A(_0488_),
    .B(_0491_),
    .Y(_0493_)
  );
  sky130_fd_sc_hd__maj3_1 _1490_ (
    .A(_0249_),
    .B(_0409_),
    .C(_0410_),
    .X(_0494_)
  );
  sky130_fd_sc_hd__xnor2_1 _1491_ (
    .A(_0492_),
    .B(_0494_),
    .Y(_0495_)
  );
  sky130_fd_sc_hd__xnor2_1 _1492_ (
    .A(_0487_),
    .B(_0495_),
    .Y(_0496_)
  );
  sky130_fd_sc_hd__and2_0 _1493_ (
    .A(carrier_in[10]),
    .B(signal_in[5]),
    .X(_0497_)
  );
  sky130_fd_sc_hd__and2_0 _1494_ (
    .A(carrier_in[11]),
    .B(signal_in[4]),
    .X(_0498_)
  );
  sky130_fd_sc_hd__nand2_1 _1495_ (
    .A(carrier_in[12]),
    .B(signal_in[4]),
    .Y(_0499_)
  );
  sky130_fd_sc_hd__xor3_1 _1496_ (
    .A(_0411_),
    .B(_0497_),
    .C(_0498_),
    .X(_0500_)
  );
  sky130_fd_sc_hd__nand2_1 _1497_ (
    .A(carrier_in[13]),
    .B(signal_in[2]),
    .Y(_0501_)
  );
  sky130_fd_sc_hd__nand2b_1 _1498_ (
    .A_N(signal_in[0]),
    .B(carrier_in[15]),
    .Y(_0502_)
  );
  sky130_fd_sc_hd__xnor3_1 _1499_ (
    .A(_0406_),
    .B(_0501_),
    .C(_0502_),
    .X(_0503_)
  );
  sky130_fd_sc_hd__xor3_1 _1500_ (
    .A(_0407_),
    .B(_0500_),
    .C(_0503_),
    .X(_0504_)
  );
  sky130_fd_sc_hd__xnor2_1 _1501_ (
    .A(_0413_),
    .B(_0504_),
    .Y(_0505_)
  );
  sky130_fd_sc_hd__xnor2_1 _1502_ (
    .A(_0496_),
    .B(_0505_),
    .Y(_0506_)
  );
  sky130_fd_sc_hd__xnor2_1 _1503_ (
    .A(_0486_),
    .B(_0506_),
    .Y(_0507_)
  );
  sky130_fd_sc_hd__xnor2_1 _1504_ (
    .A(_0485_),
    .B(_0507_),
    .Y(_0508_)
  );
  sky130_fd_sc_hd__xnor3_1 _1505_ (
    .A(_0470_),
    .B(_0485_),
    .C(_0507_),
    .X(_0509_)
  );
  sky130_fd_sc_hd__nand2_1 _1506_ (
    .A(_0469_),
    .B(_0509_),
    .Y(_0510_)
  );
  sky130_fd_sc_hd__xor2_1 _1507_ (
    .A(_0469_),
    .B(_0509_),
    .X(_0511_)
  );
  sky130_fd_sc_hd__nand2_1 _1508_ (
    .A(_0460_),
    .B(_0511_),
    .Y(_0512_)
  );
  sky130_fd_sc_hd__xnor2_1 _1509_ (
    .A(_0460_),
    .B(_0511_),
    .Y(_0513_)
  );
  sky130_fd_sc_hd__xnor2_1 _1510_ (
    .A(_0459_),
    .B(_0513_),
    .Y(_0514_)
  );
  sky130_fd_sc_hd__nand2b_1 _1511_ (
    .A_N(_0514_),
    .B(_0458_),
    .Y(_0515_)
  );
  sky130_fd_sc_hd__xor2_1 _1512_ (
    .A(_0458_),
    .B(_0514_),
    .X(_0516_)
  );
  sky130_fd_sc_hd__xnor2_1 _1513_ (
    .A(_0791_),
    .B(_0911_),
    .Y(_0517_)
  );
  sky130_fd_sc_hd__nand4_1 _1514_ (
    .A(signal_in[1]),
    .B(signal_in[0]),
    .C(carrier_in[9]),
    .D(carrier_in[8]),
    .Y(_0518_)
  );
  sky130_fd_sc_hd__nand2_1 _1515_ (
    .A(signal_in[2]),
    .B(carrier_in[7]),
    .Y(_0519_)
  );
  sky130_fd_sc_hd__a22oi_1 _1516_ (
    .A1(signal_in[0]),
    .A2(carrier_in[9]),
    .B1(carrier_in[8]),
    .B2(signal_in[1]),
    .Y(_0520_)
  );
  sky130_fd_sc_hd__a22o_1 _1517_ (
    .A1(signal_in[0]),
    .A2(carrier_in[9]),
    .B1(carrier_in[8]),
    .B2(signal_in[1]),
    .X(_0521_)
  );
  sky130_fd_sc_hd__nor3b_1 _1518_ (
    .A(_0519_),
    .B(_0520_),
    .C_N(_0518_),
    .Y(_0522_)
  );
  sky130_fd_sc_hd__o21ai_0 _1519_ (
    .A1(_0519_),
    .A2(_0520_),
    .B1(_0518_),
    .Y(_0523_)
  );
  sky130_fd_sc_hd__xnor3_1 _1520_ (
    .A(_0802_),
    .B(_0813_),
    .C(_0835_),
    .X(_0524_)
  );
  sky130_fd_sc_hd__and2_0 _1521_ (
    .A(_0523_),
    .B(_0524_),
    .X(_0525_)
  );
  sky130_fd_sc_hd__xor2_1 _1522_ (
    .A(_0523_),
    .B(_0524_),
    .X(_0526_)
  );
  sky130_fd_sc_hd__nor2b_1 _1523_ (
    .A(_0759_),
    .B_N(_0526_),
    .Y(_0527_)
  );
  sky130_fd_sc_hd__xor2_1 _1524_ (
    .A(_0517_),
    .B(_0527_),
    .X(_0528_)
  );
  sky130_fd_sc_hd__nand2_1 _1525_ (
    .A(signal_in[3]),
    .B(carrier_in[6]),
    .Y(_0529_)
  );
  sky130_fd_sc_hd__and2_0 _1526_ (
    .A(signal_in[3]),
    .B(carrier_in[5]),
    .X(_0530_)
  );
  sky130_fd_sc_hd__nand2_1 _1527_ (
    .A(signal_in[5]),
    .B(carrier_in[4]),
    .Y(_0531_)
  );
  sky130_fd_sc_hd__maj3_1 _1528_ (
    .A(_1160_),
    .B(_0529_),
    .C(_0531_),
    .X(_0532_)
  );
  sky130_fd_sc_hd__xnor3_1 _1529_ (
    .A(_1128_),
    .B(_1139_),
    .C(_1171_),
    .X(_0533_)
  );
  sky130_fd_sc_hd__nand2b_1 _1530_ (
    .A_N(_0532_),
    .B(_0533_),
    .Y(_0534_)
  );
  sky130_fd_sc_hd__xnor2_1 _1531_ (
    .A(_0532_),
    .B(_0533_),
    .Y(_0535_)
  );
  sky130_fd_sc_hd__and2_0 _1532_ (
    .A(signal_in[9]),
    .B(carrier_in[1]),
    .X(_0536_)
  );
  sky130_fd_sc_hd__and2_0 _1533_ (
    .A(signal_in[7]),
    .B(carrier_in[3]),
    .X(_0537_)
  );
  sky130_fd_sc_hd__nand2_1 _1534_ (
    .A(signal_in[7]),
    .B(carrier_in[2]),
    .Y(_0538_)
  );
  sky130_fd_sc_hd__xnor2_1 _1535_ (
    .A(_0011_),
    .B(_0537_),
    .Y(_0539_)
  );
  sky130_fd_sc_hd__xnor3_1 _1536_ (
    .A(_0011_),
    .B(_0536_),
    .C(_0537_),
    .X(_0540_)
  );
  sky130_fd_sc_hd__a21boi_0 _1537_ (
    .A1(_0535_),
    .A2(_0540_),
    .B1_N(_0534_),
    .Y(_0541_)
  );
  sky130_fd_sc_hd__xnor2_1 _1538_ (
    .A(_1247_),
    .B(_0033_),
    .Y(_0542_)
  );
  sky130_fd_sc_hd__nand2_1 _1539_ (
    .A(_0525_),
    .B(_0542_),
    .Y(_0543_)
  );
  sky130_fd_sc_hd__nor2_1 _1540_ (
    .A(_0525_),
    .B(_0542_),
    .Y(_0544_)
  );
  sky130_fd_sc_hd__xnor3_1 _1541_ (
    .A(_0525_),
    .B(_0541_),
    .C(_0542_),
    .X(_0545_)
  );
  sky130_fd_sc_hd__maj3_1 _1542_ (
    .A(_0517_),
    .B(_0527_),
    .C(_0545_),
    .X(_0546_)
  );
  sky130_fd_sc_hd__xnor2_1 _1543_ (
    .A(_1117_),
    .B(_0195_),
    .Y(_0547_)
  );
  sky130_fd_sc_hd__xnor2_1 _1544_ (
    .A(_0546_),
    .B(_0547_),
    .Y(_0548_)
  );
  sky130_fd_sc_hd__nand2_1 _1545_ (
    .A(signal_in[11]),
    .B(carrier_in[0]),
    .Y(_0549_)
  );
  sky130_fd_sc_hd__a2bb2oi_1 _1546_ (
    .A1_N(_0000_),
    .A2_N(_0538_),
    .B1(_0539_),
    .B2(_0536_),
    .Y(_0550_)
  );
  sky130_fd_sc_hd__nor2_1 _1547_ (
    .A(_0549_),
    .B(_0550_),
    .Y(_0551_)
  );
  sky130_fd_sc_hd__xor2_1 _1548_ (
    .A(_0392_),
    .B(_0393_),
    .X(_0552_)
  );
  sky130_fd_sc_hd__o21ai_0 _1549_ (
    .A1(_0541_),
    .A2(_0544_),
    .B1(_0543_),
    .Y(_0553_)
  );
  sky130_fd_sc_hd__xor3_1 _1550_ (
    .A(_0551_),
    .B(_0552_),
    .C(_0553_),
    .X(_0554_)
  );
  sky130_fd_sc_hd__maj3_1 _1551_ (
    .A(_0546_),
    .B(_0547_),
    .C(_0554_),
    .X(_0555_)
  );
  sky130_fd_sc_hd__xnor2_1 _1552_ (
    .A(_0391_),
    .B(_0402_),
    .Y(_0556_)
  );
  sky130_fd_sc_hd__maj3_1 _1553_ (
    .A(_0551_),
    .B(_0552_),
    .C(_0553_),
    .X(_0557_)
  );
  sky130_fd_sc_hd__xnor2_1 _1554_ (
    .A(_0555_),
    .B(_0556_),
    .Y(_0558_)
  );
  sky130_fd_sc_hd__maj3_1 _1555_ (
    .A(_0555_),
    .B(_0556_),
    .C(_0557_),
    .X(_0559_)
  );
  sky130_fd_sc_hd__xnor2_1 _1556_ (
    .A(_0456_),
    .B(_0457_),
    .Y(_0560_)
  );
  sky130_fd_sc_hd__nor2_1 _1557_ (
    .A(_0559_),
    .B(_0560_),
    .Y(_0561_)
  );
  sky130_fd_sc_hd__nand2_1 _1558_ (
    .A(signal_in[0]),
    .B(carrier_in[7]),
    .Y(_0562_)
  );
  sky130_fd_sc_hd__nand4_1 _1559_ (
    .A(signal_in[1]),
    .B(signal_in[0]),
    .C(carrier_in[8]),
    .D(carrier_in[7]),
    .Y(_0563_)
  );
  sky130_fd_sc_hd__a21boi_0 _1560_ (
    .A1(_0518_),
    .A2(_0521_),
    .B1_N(_0519_),
    .Y(_0564_)
  );
  sky130_fd_sc_hd__nor3_1 _1561_ (
    .A(_0522_),
    .B(_0563_),
    .C(_0564_),
    .Y(_0565_)
  );
  sky130_fd_sc_hd__o21ai_0 _1562_ (
    .A1(_0522_),
    .A2(_0564_),
    .B1(_0563_),
    .Y(_0566_)
  );
  sky130_fd_sc_hd__nor2b_1 _1563_ (
    .A(_0565_),
    .B_N(_0566_),
    .Y(_0567_)
  );
  sky130_fd_sc_hd__and2_0 _1564_ (
    .A(signal_in[2]),
    .B(carrier_in[5]),
    .X(_0568_)
  );
  sky130_fd_sc_hd__and2_0 _1565_ (
    .A(signal_in[1]),
    .B(carrier_in[6]),
    .X(_0569_)
  );
  sky130_fd_sc_hd__and2_0 _1566_ (
    .A(signal_in[2]),
    .B(carrier_in[6]),
    .X(_0570_)
  );
  sky130_fd_sc_hd__nand2_1 _1567_ (
    .A(signal_in[1]),
    .B(carrier_in[5]),
    .Y(_0571_)
  );
  sky130_fd_sc_hd__and2_0 _1568_ (
    .A(signal_in[3]),
    .B(carrier_in[4]),
    .X(_0572_)
  );
  sky130_fd_sc_hd__maj3_1 _1569_ (
    .A(_0568_),
    .B(_0569_),
    .C(_0572_),
    .X(_0573_)
  );
  sky130_fd_sc_hd__and2_0 _1570_ (
    .A(signal_in[4]),
    .B(carrier_in[4]),
    .X(_0574_)
  );
  sky130_fd_sc_hd__xor3_1 _1571_ (
    .A(_0530_),
    .B(_0570_),
    .C(_0574_),
    .X(_0575_)
  );
  sky130_fd_sc_hd__nand2_1 _1572_ (
    .A(signal_in[7]),
    .B(carrier_in[1]),
    .Y(_0576_)
  );
  sky130_fd_sc_hd__and2_0 _1573_ (
    .A(signal_in[6]),
    .B(carrier_in[2]),
    .X(_0577_)
  );
  sky130_fd_sc_hd__nand2_1 _1574_ (
    .A(signal_in[6]),
    .B(carrier_in[2]),
    .Y(_0578_)
  );
  sky130_fd_sc_hd__nand2_1 _1575_ (
    .A(signal_in[5]),
    .B(carrier_in[3]),
    .Y(_0579_)
  );
  sky130_fd_sc_hd__nand2_1 _1576_ (
    .A(signal_in[6]),
    .B(carrier_in[3]),
    .Y(_0580_)
  );
  sky130_fd_sc_hd__nand2_1 _1577_ (
    .A(signal_in[5]),
    .B(carrier_in[2]),
    .Y(_0581_)
  );
  sky130_fd_sc_hd__xnor3_1 _1578_ (
    .A(_0576_),
    .B(_0578_),
    .C(_0579_),
    .X(_0582_)
  );
  sky130_fd_sc_hd__maj3_1 _1579_ (
    .A(_0573_),
    .B(_0575_),
    .C(_0582_),
    .X(_0583_)
  );
  sky130_fd_sc_hd__maj3_1 _1580_ (
    .A(_0530_),
    .B(_0570_),
    .C(_0574_),
    .X(_0584_)
  );
  sky130_fd_sc_hd__xnor3_1 _1581_ (
    .A(_1160_),
    .B(_0529_),
    .C(_0531_),
    .X(_0585_)
  );
  sky130_fd_sc_hd__and2_0 _1582_ (
    .A(signal_in[8]),
    .B(carrier_in[1]),
    .X(_0586_)
  );
  sky130_fd_sc_hd__nand2_1 _1583_ (
    .A(_0538_),
    .B(_0580_),
    .Y(_0587_)
  );
  sky130_fd_sc_hd__xor3_1 _1584_ (
    .A(_0538_),
    .B(_0580_),
    .C(_0586_),
    .X(_0588_)
  );
  sky130_fd_sc_hd__xor3_1 _1585_ (
    .A(_0584_),
    .B(_0585_),
    .C(_0588_),
    .X(_0589_)
  );
  sky130_fd_sc_hd__nand2_1 _1586_ (
    .A(_0583_),
    .B(_0589_),
    .Y(_0590_)
  );
  sky130_fd_sc_hd__xor2_1 _1587_ (
    .A(_0583_),
    .B(_0589_),
    .X(_0591_)
  );
  sky130_fd_sc_hd__and2_0 _1588_ (
    .A(_0567_),
    .B(_0591_),
    .X(_0592_)
  );
  sky130_fd_sc_hd__xor2_1 _1589_ (
    .A(_0759_),
    .B(_0526_),
    .X(_0593_)
  );
  sky130_fd_sc_hd__maj3_1 _1590_ (
    .A(_0584_),
    .B(_0585_),
    .C(_0588_),
    .X(_0594_)
  );
  sky130_fd_sc_hd__xnor3_1 _1591_ (
    .A(_0532_),
    .B(_0533_),
    .C(_0540_),
    .X(_0595_)
  );
  sky130_fd_sc_hd__xor3_1 _1592_ (
    .A(_0565_),
    .B(_0594_),
    .C(_0595_),
    .X(_0596_)
  );
  sky130_fd_sc_hd__nor2b_1 _1593_ (
    .A(_0593_),
    .B_N(_0596_),
    .Y(_0597_)
  );
  sky130_fd_sc_hd__xnor2_1 _1594_ (
    .A(_0593_),
    .B(_0596_),
    .Y(_0598_)
  );
  sky130_fd_sc_hd__nand2_1 _1595_ (
    .A(signal_in[9]),
    .B(carrier_in[0]),
    .Y(_0599_)
  );
  sky130_fd_sc_hd__maj3_1 _1596_ (
    .A(_0576_),
    .B(_0578_),
    .C(_0579_),
    .X(_0600_)
  );
  sky130_fd_sc_hd__nor2_1 _1597_ (
    .A(_0599_),
    .B(_0600_),
    .Y(_0601_)
  );
  sky130_fd_sc_hd__nand2_1 _1598_ (
    .A(signal_in[10]),
    .B(carrier_in[0]),
    .Y(_0602_)
  );
  sky130_fd_sc_hd__a22oi_1 _1599_ (
    .A1(_0537_),
    .A2(_0577_),
    .B1(_0586_),
    .B2(_0587_),
    .Y(_0603_)
  );
  sky130_fd_sc_hd__nor2_1 _1600_ (
    .A(_0602_),
    .B(_0603_),
    .Y(_0604_)
  );
  sky130_fd_sc_hd__xor2_1 _1601_ (
    .A(_0602_),
    .B(_0603_),
    .X(_0605_)
  );
  sky130_fd_sc_hd__clkinv_1 _1602_ (
    .A(_0605_),
    .Y(_0606_)
  );
  sky130_fd_sc_hd__nor2_1 _1603_ (
    .A(_0590_),
    .B(_0606_),
    .Y(_0607_)
  );
  sky130_fd_sc_hd__nand2_1 _1604_ (
    .A(_0590_),
    .B(_0606_),
    .Y(_0608_)
  );
  sky130_fd_sc_hd__xnor3_1 _1605_ (
    .A(_0590_),
    .B(_0601_),
    .C(_0605_),
    .X(_0609_)
  );
  sky130_fd_sc_hd__maj3_1 _1606_ (
    .A(_0592_),
    .B(_0598_),
    .C(_0609_),
    .X(_0610_)
  );
  sky130_fd_sc_hd__clkinv_1 _1607_ (
    .A(_0610_),
    .Y(_0611_)
  );
  sky130_fd_sc_hd__xnor2_1 _1608_ (
    .A(_0528_),
    .B(_0545_),
    .Y(_0612_)
  );
  sky130_fd_sc_hd__clkinv_1 _1609_ (
    .A(_0612_),
    .Y(_0613_)
  );
  sky130_fd_sc_hd__xnor2_1 _1610_ (
    .A(_0597_),
    .B(_0612_),
    .Y(_0614_)
  );
  sky130_fd_sc_hd__xnor2_1 _1611_ (
    .A(_0549_),
    .B(_0550_),
    .Y(_0615_)
  );
  sky130_fd_sc_hd__clkinv_1 _1612_ (
    .A(_0615_),
    .Y(_0616_)
  );
  sky130_fd_sc_hd__maj3_1 _1613_ (
    .A(_0565_),
    .B(_0594_),
    .C(_0595_),
    .X(_0617_)
  );
  sky130_fd_sc_hd__xnor2_1 _1614_ (
    .A(_0615_),
    .B(_0617_),
    .Y(_0618_)
  );
  sky130_fd_sc_hd__xor2_1 _1615_ (
    .A(_0604_),
    .B(_0618_),
    .X(_0619_)
  );
  sky130_fd_sc_hd__xnor2_1 _1616_ (
    .A(_0614_),
    .B(_0619_),
    .Y(_0620_)
  );
  sky130_fd_sc_hd__xnor2_1 _1617_ (
    .A(_0610_),
    .B(_0620_),
    .Y(_0621_)
  );
  sky130_fd_sc_hd__a21oi_1 _1618_ (
    .A1(_0601_),
    .A2(_0608_),
    .B1(_0607_),
    .Y(_0622_)
  );
  sky130_fd_sc_hd__maj3_1 _1619_ (
    .A(_0611_),
    .B(_0620_),
    .C(_0622_),
    .X(_0623_)
  );
  sky130_fd_sc_hd__maj3_1 _1620_ (
    .A(_0597_),
    .B(_0613_),
    .C(_0619_),
    .X(_0624_)
  );
  sky130_fd_sc_hd__xnor2_1 _1621_ (
    .A(_0548_),
    .B(_0554_),
    .Y(_0625_)
  );
  sky130_fd_sc_hd__maj3_1 _1622_ (
    .A(_0604_),
    .B(_0616_),
    .C(_0617_),
    .X(_0626_)
  );
  sky130_fd_sc_hd__xnor3_1 _1623_ (
    .A(_0624_),
    .B(_0625_),
    .C(_0626_),
    .X(_0627_)
  );
  sky130_fd_sc_hd__nor2_1 _1624_ (
    .A(_0623_),
    .B(_0627_),
    .Y(_0628_)
  );
  sky130_fd_sc_hd__and4_1 _1625_ (
    .A(signal_in[1]),
    .B(signal_in[0]),
    .C(carrier_in[5]),
    .D(carrier_in[4]),
    .X(_0629_)
  );
  sky130_fd_sc_hd__nand2_1 _1626_ (
    .A(signal_in[0]),
    .B(carrier_in[6]),
    .Y(_0630_)
  );
  sky130_fd_sc_hd__nand4_1 _1627_ (
    .A(signal_in[1]),
    .B(signal_in[0]),
    .C(carrier_in[6]),
    .D(carrier_in[5]),
    .Y(_0631_)
  );
  sky130_fd_sc_hd__a22oi_1 _1628_ (
    .A1(signal_in[0]),
    .A2(carrier_in[6]),
    .B1(carrier_in[5]),
    .B2(signal_in[1]),
    .Y(_0632_)
  );
  sky130_fd_sc_hd__nand2_1 _1629_ (
    .A(signal_in[2]),
    .B(carrier_in[4]),
    .Y(_0633_)
  );
  sky130_fd_sc_hd__xnor3_1 _1630_ (
    .A(_0571_),
    .B(_0630_),
    .C(_0633_),
    .X(_0634_)
  );
  sky130_fd_sc_hd__nand2_1 _1631_ (
    .A(signal_in[5]),
    .B(carrier_in[1]),
    .Y(_0635_)
  );
  sky130_fd_sc_hd__nand2_1 _1632_ (
    .A(signal_in[4]),
    .B(carrier_in[2]),
    .Y(_0636_)
  );
  sky130_fd_sc_hd__nand2_1 _1633_ (
    .A(signal_in[3]),
    .B(carrier_in[3]),
    .Y(_0637_)
  );
  sky130_fd_sc_hd__nand2_1 _1634_ (
    .A(signal_in[4]),
    .B(carrier_in[3]),
    .Y(_0638_)
  );
  sky130_fd_sc_hd__nand2_1 _1635_ (
    .A(signal_in[3]),
    .B(carrier_in[2]),
    .Y(_0639_)
  );
  sky130_fd_sc_hd__xnor3_1 _1636_ (
    .A(_0635_),
    .B(_0636_),
    .C(_0637_),
    .X(_0640_)
  );
  sky130_fd_sc_hd__maj3_1 _1637_ (
    .A(_0629_),
    .B(_0634_),
    .C(_0640_),
    .X(_0641_)
  );
  sky130_fd_sc_hd__o21ai_0 _1638_ (
    .A1(_0632_),
    .A2(_0633_),
    .B1(_0631_),
    .Y(_0642_)
  );
  sky130_fd_sc_hd__xor3_1 _1639_ (
    .A(_0568_),
    .B(_0569_),
    .C(_0572_),
    .X(_0643_)
  );
  sky130_fd_sc_hd__and2_0 _1640_ (
    .A(signal_in[6]),
    .B(carrier_in[1]),
    .X(_0644_)
  );
  sky130_fd_sc_hd__nand2_1 _1641_ (
    .A(_0581_),
    .B(_0638_),
    .Y(_0645_)
  );
  sky130_fd_sc_hd__xor3_1 _1642_ (
    .A(_0581_),
    .B(_0638_),
    .C(_0644_),
    .X(_0646_)
  );
  sky130_fd_sc_hd__xor3_1 _1643_ (
    .A(_0642_),
    .B(_0643_),
    .C(_0646_),
    .X(_0647_)
  );
  sky130_fd_sc_hd__nand2_1 _1644_ (
    .A(_0641_),
    .B(_0647_),
    .Y(_0648_)
  );
  sky130_fd_sc_hd__clkinv_1 _1645_ (
    .A(_0648_),
    .Y(_0649_)
  );
  sky130_fd_sc_hd__xnor2_1 _1646_ (
    .A(_0641_),
    .B(_0647_),
    .Y(_0650_)
  );
  sky130_fd_sc_hd__nor2_1 _1647_ (
    .A(_0562_),
    .B(_0650_),
    .Y(_0651_)
  );
  sky130_fd_sc_hd__a22o_1 _1648_ (
    .A1(signal_in[0]),
    .A2(carrier_in[8]),
    .B1(carrier_in[7]),
    .B2(signal_in[1]),
    .X(_0652_)
  );
  sky130_fd_sc_hd__nand2_1 _1649_ (
    .A(_0563_),
    .B(_0652_),
    .Y(_0653_)
  );
  sky130_fd_sc_hd__maj3_1 _1650_ (
    .A(_0642_),
    .B(_0643_),
    .C(_0646_),
    .X(_0654_)
  );
  sky130_fd_sc_hd__xor3_1 _1651_ (
    .A(_0573_),
    .B(_0575_),
    .C(_0582_),
    .X(_0655_)
  );
  sky130_fd_sc_hd__and2_0 _1652_ (
    .A(_0654_),
    .B(_0655_),
    .X(_0656_)
  );
  sky130_fd_sc_hd__xor2_1 _1653_ (
    .A(_0654_),
    .B(_0655_),
    .X(_0657_)
  );
  sky130_fd_sc_hd__nor2b_1 _1654_ (
    .A(_0653_),
    .B_N(_0657_),
    .Y(_0658_)
  );
  sky130_fd_sc_hd__xnor2_1 _1655_ (
    .A(_0653_),
    .B(_0657_),
    .Y(_0659_)
  );
  sky130_fd_sc_hd__nand2_1 _1656_ (
    .A(signal_in[7]),
    .B(carrier_in[0]),
    .Y(_0660_)
  );
  sky130_fd_sc_hd__maj3_1 _1657_ (
    .A(_0635_),
    .B(_0636_),
    .C(_0637_),
    .X(_0661_)
  );
  sky130_fd_sc_hd__nor2_1 _1658_ (
    .A(_0660_),
    .B(_0661_),
    .Y(_0662_)
  );
  sky130_fd_sc_hd__nand2_1 _1659_ (
    .A(signal_in[8]),
    .B(carrier_in[0]),
    .Y(_0663_)
  );
  sky130_fd_sc_hd__a2bb2oi_1 _1660_ (
    .A1_N(_0579_),
    .A2_N(_0636_),
    .B1(_0644_),
    .B2(_0645_),
    .Y(_0664_)
  );
  sky130_fd_sc_hd__nor2_1 _1661_ (
    .A(_0663_),
    .B(_0664_),
    .Y(_0665_)
  );
  sky130_fd_sc_hd__xor2_1 _1662_ (
    .A(_0663_),
    .B(_0664_),
    .X(_0666_)
  );
  sky130_fd_sc_hd__xnor3_1 _1663_ (
    .A(_0648_),
    .B(_0662_),
    .C(_0666_),
    .X(_0667_)
  );
  sky130_fd_sc_hd__maj3_1 _1664_ (
    .A(_0651_),
    .B(_0659_),
    .C(_0667_),
    .X(_0668_)
  );
  sky130_fd_sc_hd__xor2_1 _1665_ (
    .A(_0567_),
    .B(_0591_),
    .X(_0669_)
  );
  sky130_fd_sc_hd__xor2_1 _1666_ (
    .A(_0599_),
    .B(_0600_),
    .X(_0670_)
  );
  sky130_fd_sc_hd__xor3_1 _1667_ (
    .A(_0656_),
    .B(_0665_),
    .C(_0670_),
    .X(_0671_)
  );
  sky130_fd_sc_hd__xor3_1 _1668_ (
    .A(_0658_),
    .B(_0669_),
    .C(_0671_),
    .X(_0672_)
  );
  sky130_fd_sc_hd__maj3_1 _1669_ (
    .A(_0649_),
    .B(_0662_),
    .C(_0666_),
    .X(_0673_)
  );
  sky130_fd_sc_hd__maj3_1 _1670_ (
    .A(_0668_),
    .B(_0672_),
    .C(_0673_),
    .X(_0674_)
  );
  sky130_fd_sc_hd__maj3_1 _1671_ (
    .A(_0656_),
    .B(_0665_),
    .C(_0670_),
    .X(_0675_)
  );
  sky130_fd_sc_hd__maj3_1 _1672_ (
    .A(_0658_),
    .B(_0669_),
    .C(_0671_),
    .X(_0676_)
  );
  sky130_fd_sc_hd__xor3_1 _1673_ (
    .A(_0592_),
    .B(_0598_),
    .C(_0609_),
    .X(_0677_)
  );
  sky130_fd_sc_hd__xnor2_1 _1674_ (
    .A(_0676_),
    .B(_0677_),
    .Y(_0678_)
  );
  sky130_fd_sc_hd__xnor2_1 _1675_ (
    .A(_0675_),
    .B(_0678_),
    .Y(_0679_)
  );
  sky130_fd_sc_hd__nor2_1 _1676_ (
    .A(_0674_),
    .B(_0679_),
    .Y(_0680_)
  );
  sky130_fd_sc_hd__a22oi_1 _1677_ (
    .A1(signal_in[0]),
    .A2(carrier_in[5]),
    .B1(carrier_in[4]),
    .B2(signal_in[1]),
    .Y(_0681_)
  );
  sky130_fd_sc_hd__nor2_1 _1678_ (
    .A(_0629_),
    .B(_0681_),
    .Y(_0682_)
  );
  sky130_fd_sc_hd__nand2_1 _1679_ (
    .A(signal_in[4]),
    .B(carrier_in[1]),
    .Y(_0683_)
  );
  sky130_fd_sc_hd__nand2_1 _1680_ (
    .A(signal_in[2]),
    .B(carrier_in[3]),
    .Y(_0684_)
  );
  sky130_fd_sc_hd__nand2_1 _1681_ (
    .A(signal_in[2]),
    .B(carrier_in[2]),
    .Y(_0685_)
  );
  sky130_fd_sc_hd__xor3_1 _1682_ (
    .A(_0639_),
    .B(_0683_),
    .C(_0684_),
    .X(_0686_)
  );
  sky130_fd_sc_hd__or3_1 _1683_ (
    .A(_0629_),
    .B(_0681_),
    .C(_0686_),
    .X(_0687_)
  );
  sky130_fd_sc_hd__xnor3_1 _1684_ (
    .A(_0629_),
    .B(_0634_),
    .C(_0640_),
    .X(_0688_)
  );
  sky130_fd_sc_hd__nor2_1 _1685_ (
    .A(_0687_),
    .B(_0688_),
    .Y(_0689_)
  );
  sky130_fd_sc_hd__xnor2_1 _1686_ (
    .A(_0687_),
    .B(_0688_),
    .Y(_0690_)
  );
  sky130_fd_sc_hd__nand2_1 _1687_ (
    .A(signal_in[5]),
    .B(carrier_in[0]),
    .Y(_0691_)
  );
  sky130_fd_sc_hd__nand2_1 _1688_ (
    .A(signal_in[1]),
    .B(carrier_in[3]),
    .Y(_0692_)
  );
  sky130_fd_sc_hd__nand2_1 _1689_ (
    .A(signal_in[1]),
    .B(carrier_in[2]),
    .Y(_0693_)
  );
  sky130_fd_sc_hd__nand2_1 _1690_ (
    .A(signal_in[3]),
    .B(carrier_in[1]),
    .Y(_0694_)
  );
  sky130_fd_sc_hd__maj3_1 _1691_ (
    .A(_0685_),
    .B(_0692_),
    .C(_0694_),
    .X(_0695_)
  );
  sky130_fd_sc_hd__nor2_1 _1692_ (
    .A(_0691_),
    .B(_0695_),
    .Y(_0696_)
  );
  sky130_fd_sc_hd__xnor3_1 _1693_ (
    .A(_0685_),
    .B(_0692_),
    .C(_0694_),
    .X(_0697_)
  );
  sky130_fd_sc_hd__nand3_1 _1694_ (
    .A(signal_in[0]),
    .B(carrier_in[4]),
    .C(_0697_),
    .Y(_0698_)
  );
  sky130_fd_sc_hd__xor2_1 _1695_ (
    .A(_0682_),
    .B(_0686_),
    .X(_0699_)
  );
  sky130_fd_sc_hd__nor2_1 _1696_ (
    .A(_0698_),
    .B(_0699_),
    .Y(_0700_)
  );
  sky130_fd_sc_hd__nand2_1 _1697_ (
    .A(signal_in[6]),
    .B(carrier_in[0]),
    .Y(_0701_)
  );
  sky130_fd_sc_hd__maj3_1 _1698_ (
    .A(_0639_),
    .B(_0683_),
    .C(_0684_),
    .X(_0702_)
  );
  sky130_fd_sc_hd__nor2_1 _1699_ (
    .A(_0701_),
    .B(_0702_),
    .Y(_0703_)
  );
  sky130_fd_sc_hd__xor2_1 _1700_ (
    .A(_0701_),
    .B(_0702_),
    .X(_0704_)
  );
  sky130_fd_sc_hd__xnor3_1 _1701_ (
    .A(_0696_),
    .B(_0700_),
    .C(_0704_),
    .X(_0705_)
  );
  sky130_fd_sc_hd__nor2_1 _1702_ (
    .A(_0690_),
    .B(_0705_),
    .Y(_0706_)
  );
  sky130_fd_sc_hd__xnor2_1 _1703_ (
    .A(_0562_),
    .B(_0650_),
    .Y(_0707_)
  );
  sky130_fd_sc_hd__xor2_1 _1704_ (
    .A(_0660_),
    .B(_0661_),
    .X(_0708_)
  );
  sky130_fd_sc_hd__xnor3_1 _1705_ (
    .A(_0689_),
    .B(_0703_),
    .C(_0708_),
    .X(_0709_)
  );
  sky130_fd_sc_hd__nor2_1 _1706_ (
    .A(_0707_),
    .B(_0709_),
    .Y(_0710_)
  );
  sky130_fd_sc_hd__xor2_1 _1707_ (
    .A(_0707_),
    .B(_0709_),
    .X(_0711_)
  );
  sky130_fd_sc_hd__maj3_1 _1708_ (
    .A(_0696_),
    .B(_0700_),
    .C(_0704_),
    .X(_0712_)
  );
  sky130_fd_sc_hd__maj3_1 _1709_ (
    .A(_0706_),
    .B(_0711_),
    .C(_0712_),
    .X(_0713_)
  );
  sky130_fd_sc_hd__xor3_1 _1710_ (
    .A(_0651_),
    .B(_0659_),
    .C(_0667_),
    .X(_0714_)
  );
  sky130_fd_sc_hd__maj3_1 _1711_ (
    .A(_0689_),
    .B(_0703_),
    .C(_0708_),
    .X(_0715_)
  );
  sky130_fd_sc_hd__xor3_1 _1712_ (
    .A(_0710_),
    .B(_0714_),
    .C(_0715_),
    .X(_0716_)
  );
  sky130_fd_sc_hd__nand2_1 _1713_ (
    .A(_0713_),
    .B(_0716_),
    .Y(_0717_)
  );
  sky130_fd_sc_hd__nand2_1 _1714_ (
    .A(signal_in[4]),
    .B(carrier_in[0]),
    .Y(_0718_)
  );
  sky130_fd_sc_hd__nand2_1 _1715_ (
    .A(signal_in[0]),
    .B(carrier_in[3]),
    .Y(_0719_)
  );
  sky130_fd_sc_hd__nand2_1 _1716_ (
    .A(signal_in[2]),
    .B(carrier_in[1]),
    .Y(_0720_)
  );
  sky130_fd_sc_hd__xor2_1 _1717_ (
    .A(_0693_),
    .B(_0719_),
    .X(_0721_)
  );
  sky130_fd_sc_hd__maj3_1 _1718_ (
    .A(_0693_),
    .B(_0719_),
    .C(_0720_),
    .X(_0722_)
  );
  sky130_fd_sc_hd__lpflow_inputiso1p_1 _1719_ (
    .A(_0718_),
    .SLEEP(_0722_),
    .X(_0723_)
  );
  sky130_fd_sc_hd__xnor2_1 _1720_ (
    .A(_0691_),
    .B(_0695_),
    .Y(_0724_)
  );
  sky130_fd_sc_hd__xnor2_1 _1721_ (
    .A(_0698_),
    .B(_0699_),
    .Y(_0725_)
  );
  sky130_fd_sc_hd__xor2_1 _1722_ (
    .A(_0723_),
    .B(_0724_),
    .X(_0727_)
  );
  sky130_fd_sc_hd__maj3_1 _1723_ (
    .A(_0723_),
    .B(_0724_),
    .C(_0725_),
    .X(_0728_)
  );
  sky130_fd_sc_hd__xnor2_1 _1724_ (
    .A(_0725_),
    .B(_0727_),
    .Y(_0729_)
  );
  sky130_fd_sc_hd__nand2_1 _1725_ (
    .A(signal_in[3]),
    .B(carrier_in[0]),
    .Y(_0730_)
  );
  sky130_fd_sc_hd__nand4_1 _1726_ (
    .A(signal_in[1]),
    .B(signal_in[0]),
    .C(carrier_in[2]),
    .D(carrier_in[1]),
    .Y(_0731_)
  );
  sky130_fd_sc_hd__lpflow_inputiso1p_1 _1727_ (
    .A(_0730_),
    .SLEEP(_0731_),
    .X(_0732_)
  );
  sky130_fd_sc_hd__nand2_1 _1728_ (
    .A(_0718_),
    .B(_0722_),
    .Y(_0733_)
  );
  sky130_fd_sc_hd__nand2_1 _1729_ (
    .A(_0723_),
    .B(_0733_),
    .Y(_0734_)
  );
  sky130_fd_sc_hd__nor2_1 _1730_ (
    .A(_0732_),
    .B(_0734_),
    .Y(_0735_)
  );
  sky130_fd_sc_hd__a21oi_1 _1731_ (
    .A1(signal_in[0]),
    .A2(carrier_in[4]),
    .B1(_0697_),
    .Y(_0736_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1732_ (
    .A(_0698_),
    .SLEEP(_0736_),
    .X(_0738_)
  );
  sky130_fd_sc_hd__xnor2_1 _1733_ (
    .A(_0720_),
    .B(_0721_),
    .Y(_0739_)
  );
  sky130_fd_sc_hd__xor2_1 _1734_ (
    .A(_0730_),
    .B(_0731_),
    .X(_0740_)
  );
  sky130_fd_sc_hd__a21oi_1 _1735_ (
    .A1(signal_in[0]),
    .A2(_0731_),
    .B1(signal_in[2]),
    .Y(_0741_)
  );
  sky130_fd_sc_hd__a32oi_1 _1736_ (
    .A1(signal_in[2]),
    .A2(signal_in[0]),
    .A3(carrier_in[2]),
    .B1(carrier_in[1]),
    .B2(signal_in[1]),
    .Y(_0742_)
  );
  sky130_fd_sc_hd__nor3b_1 _1737_ (
    .A(_0741_),
    .B(_0742_),
    .C_N(carrier_in[0]),
    .Y(_0743_)
  );
  sky130_fd_sc_hd__maj3_1 _1738_ (
    .A(_0739_),
    .B(_0740_),
    .C(_0743_),
    .X(_0744_)
  );
  sky130_fd_sc_hd__nand2_1 _1739_ (
    .A(_0732_),
    .B(_0734_),
    .Y(_0745_)
  );
  sky130_fd_sc_hd__a31oi_1 _1740_ (
    .A1(_0735_),
    .A2(_0738_),
    .A3(_0744_),
    .B1(_0729_),
    .Y(_0746_)
  );
  sky130_fd_sc_hd__nor3_1 _1741_ (
    .A(_0735_),
    .B(_0738_),
    .C(_0744_),
    .Y(_0747_)
  );
  sky130_fd_sc_hd__a21oi_1 _1742_ (
    .A1(_0738_),
    .A2(_0744_),
    .B1(_0745_),
    .Y(_0749_)
  );
  sky130_fd_sc_hd__nor3_1 _1743_ (
    .A(_0746_),
    .B(_0747_),
    .C(_0749_),
    .Y(_0750_)
  );
  sky130_fd_sc_hd__xnor2_1 _1744_ (
    .A(_0690_),
    .B(_0705_),
    .Y(_0751_)
  );
  sky130_fd_sc_hd__nand2_1 _1745_ (
    .A(_0728_),
    .B(_0751_),
    .Y(_0752_)
  );
  sky130_fd_sc_hd__xor3_1 _1746_ (
    .A(_0706_),
    .B(_0711_),
    .C(_0712_),
    .X(_0753_)
  );
  sky130_fd_sc_hd__nor2_1 _1747_ (
    .A(_0728_),
    .B(_0751_),
    .Y(_0754_)
  );
  sky130_fd_sc_hd__o211ai_1 _1748_ (
    .A1(_0750_),
    .A2(_0754_),
    .B1(_0753_),
    .C1(_0752_),
    .Y(_0755_)
  );
  sky130_fd_sc_hd__maj3_1 _1749_ (
    .A(_0710_),
    .B(_0714_),
    .C(_0715_),
    .X(_0756_)
  );
  sky130_fd_sc_hd__xor3_1 _1750_ (
    .A(_0668_),
    .B(_0672_),
    .C(_0673_),
    .X(_0757_)
  );
  sky130_fd_sc_hd__o22ai_1 _1751_ (
    .A1(_0713_),
    .A2(_0716_),
    .B1(_0756_),
    .B2(_0757_),
    .Y(_0758_)
  );
  sky130_fd_sc_hd__a21o_1 _1752_ (
    .A1(_0717_),
    .A2(_0755_),
    .B1(_0758_),
    .X(_0760_)
  );
  sky130_fd_sc_hd__maj3_1 _1753_ (
    .A(_0675_),
    .B(_0676_),
    .C(_0677_),
    .X(_0761_)
  );
  sky130_fd_sc_hd__xnor2_1 _1754_ (
    .A(_0621_),
    .B(_0622_),
    .Y(_0762_)
  );
  sky130_fd_sc_hd__a22oi_1 _1755_ (
    .A1(_0674_),
    .A2(_0679_),
    .B1(_0756_),
    .B2(_0757_),
    .Y(_0763_)
  );
  sky130_fd_sc_hd__a21oi_1 _1756_ (
    .A1(_0760_),
    .A2(_0763_),
    .B1(_0680_),
    .Y(_0764_)
  );
  sky130_fd_sc_hd__maj3_1 _1757_ (
    .A(_0761_),
    .B(_0762_),
    .C(_0764_),
    .X(_0765_)
  );
  sky130_fd_sc_hd__maj3_1 _1758_ (
    .A(_0624_),
    .B(_0625_),
    .C(_0626_),
    .X(_0766_)
  );
  sky130_fd_sc_hd__xnor2_1 _1759_ (
    .A(_0557_),
    .B(_0558_),
    .Y(_0767_)
  );
  sky130_fd_sc_hd__nand2_1 _1760_ (
    .A(_0623_),
    .B(_0627_),
    .Y(_0768_)
  );
  sky130_fd_sc_hd__o221ai_1 _1761_ (
    .A1(_0628_),
    .A2(_0765_),
    .B1(_0766_),
    .B2(_0767_),
    .C1(_0768_),
    .Y(_0769_)
  );
  sky130_fd_sc_hd__a22oi_1 _1762_ (
    .A1(_0559_),
    .A2(_0560_),
    .B1(_0766_),
    .B2(_0767_),
    .Y(_0771_)
  );
  sky130_fd_sc_hd__a21oi_1 _1763_ (
    .A1(_0769_),
    .A2(_0771_),
    .B1(_0561_),
    .Y(_0772_)
  );
  sky130_fd_sc_hd__a211o_1 _1764_ (
    .A1(_0769_),
    .A2(_0771_),
    .B1(_0516_),
    .C1(_0561_),
    .X(_0773_)
  );
  sky130_fd_sc_hd__xnor2_1 _1765_ (
    .A(_0516_),
    .B(_0772_),
    .Y(_1279_[15])
  );
  sky130_fd_sc_hd__and2_0 _1766_ (
    .A(_0515_),
    .B(_0773_),
    .X(_0774_)
  );
  sky130_fd_sc_hd__o21ai_0 _1767_ (
    .A1(_0459_),
    .A2(_0513_),
    .B1(_0512_),
    .Y(_0775_)
  );
  sky130_fd_sc_hd__o21ai_0 _1768_ (
    .A1(_0465_),
    .A2(_0466_),
    .B1(_0468_),
    .Y(_0776_)
  );
  sky130_fd_sc_hd__o21ai_0 _1769_ (
    .A1(_0470_),
    .A2(_0508_),
    .B1(_0510_),
    .Y(_0777_)
  );
  sky130_fd_sc_hd__maj3_1 _1770_ (
    .A(_0726_),
    .B(_0461_),
    .C(_0462_),
    .X(_0778_)
  );
  sky130_fd_sc_hd__maj3_1 _1771_ (
    .A(_0438_),
    .B(_0472_),
    .C(_0473_),
    .X(_0779_)
  );
  sky130_fd_sc_hd__xnor2_1 _1772_ (
    .A(_0461_),
    .B(_0779_),
    .Y(_0781_)
  );
  sky130_fd_sc_hd__maj3_1 _1773_ (
    .A(_0471_),
    .B(_0483_),
    .C(_0484_),
    .X(_0782_)
  );
  sky130_fd_sc_hd__nor2_1 _1774_ (
    .A(_0781_),
    .B(_0782_),
    .Y(_0783_)
  );
  sky130_fd_sc_hd__xnor2_1 _1775_ (
    .A(_0781_),
    .B(_0782_),
    .Y(_0784_)
  );
  sky130_fd_sc_hd__nor2_1 _1776_ (
    .A(_0778_),
    .B(_0784_),
    .Y(_0785_)
  );
  sky130_fd_sc_hd__xnor2_1 _1777_ (
    .A(_0778_),
    .B(_0784_),
    .Y(_0786_)
  );
  sky130_fd_sc_hd__maj3_1 _1778_ (
    .A(_0485_),
    .B(_0486_),
    .C(_0506_),
    .X(_0787_)
  );
  sky130_fd_sc_hd__a21oi_1 _1779_ (
    .A1(_0475_),
    .A2(_0482_),
    .B1(_0481_),
    .Y(_0788_)
  );
  sky130_fd_sc_hd__nand2_1 _1780_ (
    .A(carrier_in[1]),
    .B(signal_in[15]),
    .Y(_0789_)
  );
  sky130_fd_sc_hd__and4_1 _1781_ (
    .A(carrier_in[3]),
    .B(carrier_in[2]),
    .C(signal_in[13]),
    .D(signal_in[14]),
    .X(_0790_)
  );
  sky130_fd_sc_hd__a22oi_1 _1782_ (
    .A1(carrier_in[3]),
    .A2(signal_in[13]),
    .B1(signal_in[14]),
    .B2(carrier_in[2]),
    .Y(_0792_)
  );
  sky130_fd_sc_hd__nor2_1 _1783_ (
    .A(_0790_),
    .B(_0792_),
    .Y(_0793_)
  );
  sky130_fd_sc_hd__xnor2_1 _1784_ (
    .A(_0789_),
    .B(_0793_),
    .Y(_0794_)
  );
  sky130_fd_sc_hd__maj3_1 _1785_ (
    .A(_0431_),
    .B(_0477_),
    .C(_0478_),
    .X(_0795_)
  );
  sky130_fd_sc_hd__nand2_1 _1786_ (
    .A(carrier_in[4]),
    .B(signal_in[12]),
    .Y(_0796_)
  );
  sky130_fd_sc_hd__nand2_1 _1787_ (
    .A(carrier_in[5]),
    .B(signal_in[11]),
    .Y(_0797_)
  );
  sky130_fd_sc_hd__nand2_1 _1788_ (
    .A(carrier_in[6]),
    .B(signal_in[11]),
    .Y(_0798_)
  );
  sky130_fd_sc_hd__xnor3_1 _1789_ (
    .A(_0479_),
    .B(_0796_),
    .C(_0797_),
    .X(_0799_)
  );
  sky130_fd_sc_hd__nand2b_1 _1790_ (
    .A_N(_0795_),
    .B(_0799_),
    .Y(_0800_)
  );
  sky130_fd_sc_hd__xnor2_1 _1791_ (
    .A(_0795_),
    .B(_0799_),
    .Y(_0801_)
  );
  sky130_fd_sc_hd__nand2_1 _1792_ (
    .A(_0794_),
    .B(_0801_),
    .Y(_0803_)
  );
  sky130_fd_sc_hd__xnor2_1 _1793_ (
    .A(_0794_),
    .B(_0801_),
    .Y(_0804_)
  );
  sky130_fd_sc_hd__maj3_1 _1794_ (
    .A(_0487_),
    .B(_0493_),
    .C(_0494_),
    .X(_0805_)
  );
  sky130_fd_sc_hd__xnor2_1 _1795_ (
    .A(_0804_),
    .B(_0805_),
    .Y(_0806_)
  );
  sky130_fd_sc_hd__xnor2_1 _1796_ (
    .A(_0788_),
    .B(_0806_),
    .Y(_0807_)
  );
  sky130_fd_sc_hd__a32o_1 _1797_ (
    .A1(_0408_),
    .A2(_0412_),
    .A3(_0504_),
    .B1(_0505_),
    .B2(_0496_),
    .X(_0808_)
  );
  sky130_fd_sc_hd__a2bb2oi_1 _1798_ (
    .A1_N(_0418_),
    .A2_N(_0490_),
    .B1(_0491_),
    .B2(_0488_),
    .Y(_0809_)
  );
  sky130_fd_sc_hd__nand2_1 _1799_ (
    .A(carrier_in[7]),
    .B(signal_in[9]),
    .Y(_0810_)
  );
  sky130_fd_sc_hd__nand2_1 _1800_ (
    .A(carrier_in[8]),
    .B(signal_in[8]),
    .Y(_0811_)
  );
  sky130_fd_sc_hd__nand2_1 _1801_ (
    .A(carrier_in[9]),
    .B(signal_in[8]),
    .Y(_0812_)
  );
  sky130_fd_sc_hd__xnor3_1 _1802_ (
    .A(_0490_),
    .B(_0810_),
    .C(_0811_),
    .X(_0814_)
  );
  sky130_fd_sc_hd__maj3_1 _1803_ (
    .A(_0411_),
    .B(_0497_),
    .C(_0498_),
    .X(_0815_)
  );
  sky130_fd_sc_hd__nand2_1 _1804_ (
    .A(_0814_),
    .B(_0815_),
    .Y(_0816_)
  );
  sky130_fd_sc_hd__nor2_1 _1805_ (
    .A(_0814_),
    .B(_0815_),
    .Y(_0817_)
  );
  sky130_fd_sc_hd__xor2_1 _1806_ (
    .A(_0814_),
    .B(_0815_),
    .X(_0818_)
  );
  sky130_fd_sc_hd__xnor2_1 _1807_ (
    .A(_0809_),
    .B(_0818_),
    .Y(_0819_)
  );
  sky130_fd_sc_hd__maj3_1 _1808_ (
    .A(_0407_),
    .B(_0500_),
    .C(_0503_),
    .X(_0820_)
  );
  sky130_fd_sc_hd__nand2_1 _1809_ (
    .A(carrier_in[10]),
    .B(signal_in[6]),
    .Y(_0821_)
  );
  sky130_fd_sc_hd__nand2_1 _1810_ (
    .A(carrier_in[11]),
    .B(signal_in[5]),
    .Y(_0822_)
  );
  sky130_fd_sc_hd__nand2_1 _1811_ (
    .A(carrier_in[12]),
    .B(signal_in[5]),
    .Y(_0823_)
  );
  sky130_fd_sc_hd__xor3_1 _1812_ (
    .A(_0499_),
    .B(_0821_),
    .C(_0822_),
    .X(_0825_)
  );
  sky130_fd_sc_hd__maj3_1 _1813_ (
    .A(_0406_),
    .B(_0501_),
    .C(_0502_),
    .X(_0826_)
  );
  sky130_fd_sc_hd__nand2_1 _1814_ (
    .A(carrier_in[13]),
    .B(signal_in[3]),
    .Y(_0827_)
  );
  sky130_fd_sc_hd__nand2_1 _1815_ (
    .A(carrier_in[14]),
    .B(signal_in[2]),
    .Y(_0828_)
  );
  sky130_fd_sc_hd__nand2b_1 _1816_ (
    .A_N(signal_in[1]),
    .B(carrier_in[15]),
    .Y(_0829_)
  );
  sky130_fd_sc_hd__xor3_1 _1817_ (
    .A(_0827_),
    .B(_0828_),
    .C(_0829_),
    .X(_0830_)
  );
  sky130_fd_sc_hd__xnor3_1 _1818_ (
    .A(_0825_),
    .B(_0826_),
    .C(_0830_),
    .X(_0831_)
  );
  sky130_fd_sc_hd__and2_0 _1819_ (
    .A(_0820_),
    .B(_0831_),
    .X(_0832_)
  );
  sky130_fd_sc_hd__xor2_1 _1820_ (
    .A(_0820_),
    .B(_0831_),
    .X(_0833_)
  );
  sky130_fd_sc_hd__xnor2_1 _1821_ (
    .A(_0819_),
    .B(_0833_),
    .Y(_0834_)
  );
  sky130_fd_sc_hd__nand2b_1 _1822_ (
    .A_N(_0834_),
    .B(_0808_),
    .Y(_0836_)
  );
  sky130_fd_sc_hd__xor2_1 _1823_ (
    .A(_0808_),
    .B(_0834_),
    .X(_0837_)
  );
  sky130_fd_sc_hd__xnor2_1 _1824_ (
    .A(_0807_),
    .B(_0837_),
    .Y(_0838_)
  );
  sky130_fd_sc_hd__nor2_1 _1825_ (
    .A(_0787_),
    .B(_0838_),
    .Y(_0839_)
  );
  sky130_fd_sc_hd__xnor3_1 _1826_ (
    .A(_0787_),
    .B(_0807_),
    .C(_0837_),
    .X(_0840_)
  );
  sky130_fd_sc_hd__nor2b_1 _1827_ (
    .A(_0786_),
    .B_N(_0840_),
    .Y(_0841_)
  );
  sky130_fd_sc_hd__xor2_1 _1828_ (
    .A(_0786_),
    .B(_0840_),
    .X(_0842_)
  );
  sky130_fd_sc_hd__nand2b_1 _1829_ (
    .A_N(_0842_),
    .B(_0777_),
    .Y(_0843_)
  );
  sky130_fd_sc_hd__xnor2_1 _1830_ (
    .A(_0777_),
    .B(_0842_),
    .Y(_0844_)
  );
  sky130_fd_sc_hd__nand2_1 _1831_ (
    .A(_0776_),
    .B(_0844_),
    .Y(_0845_)
  );
  sky130_fd_sc_hd__xor2_1 _1832_ (
    .A(_0776_),
    .B(_0844_),
    .X(_0847_)
  );
  sky130_fd_sc_hd__and2_0 _1833_ (
    .A(_0775_),
    .B(_0847_),
    .X(_0848_)
  );
  sky130_fd_sc_hd__xnor2_1 _1834_ (
    .A(_0775_),
    .B(_0847_),
    .Y(_0849_)
  );
  sky130_fd_sc_hd__lpflow_inputiso1p_1 _1835_ (
    .A(_0774_),
    .SLEEP(_0849_),
    .X(_0850_)
  );
  sky130_fd_sc_hd__xor2_1 _1836_ (
    .A(_0774_),
    .B(_0849_),
    .X(_1279_[16])
  );
  sky130_fd_sc_hd__nand2b_1 _1837_ (
    .A_N(_0848_),
    .B(_0850_),
    .Y(_0851_)
  );
  sky130_fd_sc_hd__nor2_1 _1838_ (
    .A(_0783_),
    .B(_0785_),
    .Y(_0852_)
  );
  sky130_fd_sc_hd__nor2_1 _1839_ (
    .A(_0839_),
    .B(_0841_),
    .Y(_0853_)
  );
  sky130_fd_sc_hd__a31oi_1 _1840_ (
    .A1(carrier_in[1]),
    .A2(signal_in[15]),
    .A3(_0793_),
    .B1(_0790_),
    .Y(_0854_)
  );
  sky130_fd_sc_hd__nor2_1 _1841_ (
    .A(_0461_),
    .B(_0854_),
    .Y(_0855_)
  );
  sky130_fd_sc_hd__xnor2_1 _1842_ (
    .A(_0461_),
    .B(_0854_),
    .Y(_0857_)
  );
  sky130_fd_sc_hd__maj3_1 _1843_ (
    .A(_0788_),
    .B(_0804_),
    .C(_0805_),
    .X(_0858_)
  );
  sky130_fd_sc_hd__nor2_1 _1844_ (
    .A(_0857_),
    .B(_0858_),
    .Y(_0859_)
  );
  sky130_fd_sc_hd__xnor2_1 _1845_ (
    .A(_0857_),
    .B(_0858_),
    .Y(_0860_)
  );
  sky130_fd_sc_hd__nor3_1 _1846_ (
    .A(_0461_),
    .B(_0779_),
    .C(_0860_),
    .Y(_0861_)
  );
  sky130_fd_sc_hd__o21a_1 _1847_ (
    .A1(_0461_),
    .A2(_0779_),
    .B1(_0860_),
    .X(_0862_)
  );
  sky130_fd_sc_hd__nor2_1 _1848_ (
    .A(_0861_),
    .B(_0862_),
    .Y(_0863_)
  );
  sky130_fd_sc_hd__o21ai_0 _1849_ (
    .A1(_0807_),
    .A2(_0837_),
    .B1(_0836_),
    .Y(_0864_)
  );
  sky130_fd_sc_hd__nand2_1 _1850_ (
    .A(_0800_),
    .B(_0803_),
    .Y(_0865_)
  );
  sky130_fd_sc_hd__a22oi_1 _1851_ (
    .A1(carrier_in[3]),
    .A2(signal_in[14]),
    .B1(signal_in[15]),
    .B2(carrier_in[2]),
    .Y(_0866_)
  );
  sky130_fd_sc_hd__and3_1 _1852_ (
    .A(carrier_in[3]),
    .B(carrier_in[2]),
    .C(signal_in[15]),
    .X(_0868_)
  );
  sky130_fd_sc_hd__and4_1 _1853_ (
    .A(carrier_in[3]),
    .B(carrier_in[2]),
    .C(signal_in[14]),
    .D(signal_in[15]),
    .X(_0869_)
  );
  sky130_fd_sc_hd__nor3_1 _1854_ (
    .A(_0789_),
    .B(_0866_),
    .C(_0869_),
    .Y(_0870_)
  );
  sky130_fd_sc_hd__o21ai_0 _1855_ (
    .A1(_0866_),
    .A2(_0869_),
    .B1(_0789_),
    .Y(_0871_)
  );
  sky130_fd_sc_hd__nor2b_1 _1856_ (
    .A(_0870_),
    .B_N(_0871_),
    .Y(_0872_)
  );
  sky130_fd_sc_hd__maj3_1 _1857_ (
    .A(_0479_),
    .B(_0796_),
    .C(_0797_),
    .X(_0873_)
  );
  sky130_fd_sc_hd__nand2_1 _1858_ (
    .A(carrier_in[4]),
    .B(signal_in[13]),
    .Y(_0874_)
  );
  sky130_fd_sc_hd__nand2_1 _1859_ (
    .A(carrier_in[5]),
    .B(signal_in[12]),
    .Y(_0875_)
  );
  sky130_fd_sc_hd__nand2_1 _1860_ (
    .A(carrier_in[6]),
    .B(signal_in[12]),
    .Y(_0876_)
  );
  sky130_fd_sc_hd__xnor3_1 _1861_ (
    .A(_0798_),
    .B(_0874_),
    .C(_0875_),
    .X(_0877_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1862_ (
    .A(_0877_),
    .SLEEP(_0873_),
    .X(_0879_)
  );
  sky130_fd_sc_hd__xnor2_1 _1863_ (
    .A(_0873_),
    .B(_0877_),
    .Y(_0880_)
  );
  sky130_fd_sc_hd__xor2_1 _1864_ (
    .A(_0872_),
    .B(_0880_),
    .X(_0881_)
  );
  sky130_fd_sc_hd__o21a_1 _1865_ (
    .A1(_0809_),
    .A2(_0817_),
    .B1(_0816_),
    .X(_0882_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1866_ (
    .A(_0881_),
    .SLEEP(_0882_),
    .X(_0883_)
  );
  sky130_fd_sc_hd__xor2_1 _1867_ (
    .A(_0881_),
    .B(_0882_),
    .X(_0884_)
  );
  sky130_fd_sc_hd__a21oi_1 _1868_ (
    .A1(_0800_),
    .A2(_0803_),
    .B1(_0884_),
    .Y(_0885_)
  );
  sky130_fd_sc_hd__xor2_1 _1869_ (
    .A(_0865_),
    .B(_0884_),
    .X(_0886_)
  );
  sky130_fd_sc_hd__a21oi_1 _1870_ (
    .A1(_0819_),
    .A2(_0833_),
    .B1(_0832_),
    .Y(_0887_)
  );
  sky130_fd_sc_hd__maj3_1 _1871_ (
    .A(_0490_),
    .B(_0810_),
    .C(_0811_),
    .X(_0888_)
  );
  sky130_fd_sc_hd__nand2_1 _1872_ (
    .A(carrier_in[7]),
    .B(signal_in[10]),
    .Y(_0890_)
  );
  sky130_fd_sc_hd__nand2_1 _1873_ (
    .A(carrier_in[8]),
    .B(signal_in[9]),
    .Y(_0891_)
  );
  sky130_fd_sc_hd__nand2_1 _1874_ (
    .A(carrier_in[9]),
    .B(signal_in[9]),
    .Y(_0892_)
  );
  sky130_fd_sc_hd__xnor2_1 _1875_ (
    .A(_0812_),
    .B(_0891_),
    .Y(_0893_)
  );
  sky130_fd_sc_hd__xnor3_1 _1876_ (
    .A(_0812_),
    .B(_0890_),
    .C(_0891_),
    .X(_0894_)
  );
  sky130_fd_sc_hd__xnor2_1 _1877_ (
    .A(_0890_),
    .B(_0893_),
    .Y(_0895_)
  );
  sky130_fd_sc_hd__maj3_1 _1878_ (
    .A(_0499_),
    .B(_0821_),
    .C(_0822_),
    .X(_0896_)
  );
  sky130_fd_sc_hd__xnor2_1 _1879_ (
    .A(_0894_),
    .B(_0896_),
    .Y(_0897_)
  );
  sky130_fd_sc_hd__xnor2_1 _1880_ (
    .A(_0888_),
    .B(_0897_),
    .Y(_0898_)
  );
  sky130_fd_sc_hd__maj3_1 _1881_ (
    .A(_0825_),
    .B(_0826_),
    .C(_0830_),
    .X(_0899_)
  );
  sky130_fd_sc_hd__nand2_1 _1882_ (
    .A(carrier_in[10]),
    .B(signal_in[7]),
    .Y(_0901_)
  );
  sky130_fd_sc_hd__nand2_1 _1883_ (
    .A(carrier_in[11]),
    .B(signal_in[6]),
    .Y(_0902_)
  );
  sky130_fd_sc_hd__nand2_1 _1884_ (
    .A(carrier_in[12]),
    .B(signal_in[6]),
    .Y(_0903_)
  );
  sky130_fd_sc_hd__xor3_1 _1885_ (
    .A(_0823_),
    .B(_0901_),
    .C(_0902_),
    .X(_0904_)
  );
  sky130_fd_sc_hd__maj3_1 _1886_ (
    .A(_0827_),
    .B(_0828_),
    .C(_0829_),
    .X(_0905_)
  );
  sky130_fd_sc_hd__and2_0 _1887_ (
    .A(carrier_in[13]),
    .B(signal_in[4]),
    .X(_0906_)
  );
  sky130_fd_sc_hd__and2_0 _1888_ (
    .A(carrier_in[14]),
    .B(signal_in[3]),
    .X(_0907_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1889_ (
    .A(carrier_in[15]),
    .SLEEP(signal_in[2]),
    .X(_0908_)
  );
  sky130_fd_sc_hd__xnor3_1 _1890_ (
    .A(_0906_),
    .B(_0907_),
    .C(_0908_),
    .X(_0909_)
  );
  sky130_fd_sc_hd__xnor3_1 _1891_ (
    .A(_0904_),
    .B(_0905_),
    .C(_0909_),
    .X(_0910_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1892_ (
    .A(_0910_),
    .SLEEP(_0899_),
    .X(_0912_)
  );
  sky130_fd_sc_hd__xnor2_1 _1893_ (
    .A(_0899_),
    .B(_0910_),
    .Y(_0913_)
  );
  sky130_fd_sc_hd__xnor2_1 _1894_ (
    .A(_0898_),
    .B(_0913_),
    .Y(_0914_)
  );
  sky130_fd_sc_hd__lpflow_inputiso1p_1 _1895_ (
    .A(_0887_),
    .SLEEP(_0914_),
    .X(_0915_)
  );
  sky130_fd_sc_hd__xnor2_1 _1896_ (
    .A(_0887_),
    .B(_0914_),
    .Y(_0916_)
  );
  sky130_fd_sc_hd__xnor2_1 _1897_ (
    .A(_0886_),
    .B(_0916_),
    .Y(_0917_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1898_ (
    .A(_0864_),
    .SLEEP(_0917_),
    .X(_0918_)
  );
  sky130_fd_sc_hd__xnor2_1 _1899_ (
    .A(_0864_),
    .B(_0917_),
    .Y(_0919_)
  );
  sky130_fd_sc_hd__and2_0 _1900_ (
    .A(_0863_),
    .B(_0919_),
    .X(_0920_)
  );
  sky130_fd_sc_hd__xor2_1 _1901_ (
    .A(_0863_),
    .B(_0919_),
    .X(_0921_)
  );
  sky130_fd_sc_hd__o21ai_0 _1902_ (
    .A1(_0839_),
    .A2(_0841_),
    .B1(_0921_),
    .Y(_0923_)
  );
  sky130_fd_sc_hd__xnor2_1 _1903_ (
    .A(_0853_),
    .B(_0921_),
    .Y(_0924_)
  );
  sky130_fd_sc_hd__o21ai_0 _1904_ (
    .A1(_0783_),
    .A2(_0785_),
    .B1(_0924_),
    .Y(_0925_)
  );
  sky130_fd_sc_hd__xor2_1 _1905_ (
    .A(_0852_),
    .B(_0924_),
    .X(_0926_)
  );
  sky130_fd_sc_hd__a21oi_1 _1906_ (
    .A1(_0843_),
    .A2(_0845_),
    .B1(_0926_),
    .Y(_0927_)
  );
  sky130_fd_sc_hd__nand3_1 _1907_ (
    .A(_0843_),
    .B(_0845_),
    .C(_0926_),
    .Y(_0928_)
  );
  sky130_fd_sc_hd__nand2b_1 _1908_ (
    .A_N(_0927_),
    .B(_0928_),
    .Y(_0929_)
  );
  sky130_fd_sc_hd__xnor2_1 _1909_ (
    .A(_0851_),
    .B(_0929_),
    .Y(_1279_[17])
  );
  sky130_fd_sc_hd__a211oi_1 _1910_ (
    .A1(_0515_),
    .A2(_0773_),
    .B1(_0849_),
    .C1(_0929_),
    .Y(_0930_)
  );
  sky130_fd_sc_hd__a21oi_1 _1911_ (
    .A1(_0848_),
    .A2(_0928_),
    .B1(_0927_),
    .Y(_0931_)
  );
  sky130_fd_sc_hd__clkinv_1 _1912_ (
    .A(_0931_),
    .Y(_0933_)
  );
  sky130_fd_sc_hd__o21ai_0 _1913_ (
    .A1(_0850_),
    .A2(_0929_),
    .B1(_0931_),
    .Y(_0934_)
  );
  sky130_fd_sc_hd__and2_0 _1914_ (
    .A(_0923_),
    .B(_0925_),
    .X(_0935_)
  );
  sky130_fd_sc_hd__nor2_1 _1915_ (
    .A(_0918_),
    .B(_0920_),
    .Y(_0936_)
  );
  sky130_fd_sc_hd__nor2_1 _1916_ (
    .A(_0869_),
    .B(_0870_),
    .Y(_0937_)
  );
  sky130_fd_sc_hd__nor2_1 _1917_ (
    .A(_0461_),
    .B(_0937_),
    .Y(_0938_)
  );
  sky130_fd_sc_hd__xnor2_1 _1918_ (
    .A(_0461_),
    .B(_0937_),
    .Y(_0939_)
  );
  sky130_fd_sc_hd__nor2_1 _1919_ (
    .A(_0883_),
    .B(_0885_),
    .Y(_0940_)
  );
  sky130_fd_sc_hd__xnor2_1 _1920_ (
    .A(_0939_),
    .B(_0940_),
    .Y(_0941_)
  );
  sky130_fd_sc_hd__xnor2_1 _1921_ (
    .A(_0855_),
    .B(_0941_),
    .Y(_0942_)
  );
  sky130_fd_sc_hd__o21ai_0 _1922_ (
    .A1(_0886_),
    .A2(_0916_),
    .B1(_0915_),
    .Y(_0944_)
  );
  sky130_fd_sc_hd__a21oi_1 _1923_ (
    .A1(_0872_),
    .A2(_0880_),
    .B1(_0879_),
    .Y(_0945_)
  );
  sky130_fd_sc_hd__o21ai_0 _1924_ (
    .A1(carrier_in[3]),
    .A2(carrier_in[2]),
    .B1(signal_in[15]),
    .Y(_0946_)
  );
  sky130_fd_sc_hd__nor2_1 _1925_ (
    .A(_0868_),
    .B(_0946_),
    .Y(_0947_)
  );
  sky130_fd_sc_hd__xnor2_1 _1926_ (
    .A(_0789_),
    .B(_0947_),
    .Y(_0948_)
  );
  sky130_fd_sc_hd__clkinv_1 _1927_ (
    .A(_0948_),
    .Y(_0949_)
  );
  sky130_fd_sc_hd__maj3_1 _1928_ (
    .A(_0798_),
    .B(_0874_),
    .C(_0875_),
    .X(_0950_)
  );
  sky130_fd_sc_hd__nand2_1 _1929_ (
    .A(carrier_in[4]),
    .B(signal_in[14]),
    .Y(_0951_)
  );
  sky130_fd_sc_hd__nand2_1 _1930_ (
    .A(carrier_in[5]),
    .B(signal_in[13]),
    .Y(_0952_)
  );
  sky130_fd_sc_hd__nand2_1 _1931_ (
    .A(carrier_in[6]),
    .B(signal_in[13]),
    .Y(_0953_)
  );
  sky130_fd_sc_hd__xnor3_1 _1932_ (
    .A(_0876_),
    .B(_0951_),
    .C(_0952_),
    .X(_0955_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1933_ (
    .A(_0955_),
    .SLEEP(_0950_),
    .X(_0956_)
  );
  sky130_fd_sc_hd__xnor2_1 _1934_ (
    .A(_0950_),
    .B(_0955_),
    .Y(_0957_)
  );
  sky130_fd_sc_hd__xnor2_1 _1935_ (
    .A(_0948_),
    .B(_0957_),
    .Y(_0958_)
  );
  sky130_fd_sc_hd__maj3_1 _1936_ (
    .A(_0888_),
    .B(_0895_),
    .C(_0896_),
    .X(_0959_)
  );
  sky130_fd_sc_hd__xor2_1 _1937_ (
    .A(_0958_),
    .B(_0959_),
    .X(_0960_)
  );
  sky130_fd_sc_hd__xnor2_1 _1938_ (
    .A(_0945_),
    .B(_0960_),
    .Y(_0961_)
  );
  sky130_fd_sc_hd__a21oi_1 _1939_ (
    .A1(_0898_),
    .A2(_0913_),
    .B1(_0912_),
    .Y(_0962_)
  );
  sky130_fd_sc_hd__o22a_1 _1940_ (
    .A1(_0811_),
    .A2(_0892_),
    .B1(_0893_),
    .B2(_0890_),
    .X(_0963_)
  );
  sky130_fd_sc_hd__nand2_1 _1941_ (
    .A(carrier_in[7]),
    .B(signal_in[11]),
    .Y(_0964_)
  );
  sky130_fd_sc_hd__nand2_1 _1942_ (
    .A(carrier_in[8]),
    .B(signal_in[10]),
    .Y(_0966_)
  );
  sky130_fd_sc_hd__nand2_1 _1943_ (
    .A(carrier_in[9]),
    .B(signal_in[10]),
    .Y(_0967_)
  );
  sky130_fd_sc_hd__xnor2_1 _1944_ (
    .A(_0892_),
    .B(_0966_),
    .Y(_0968_)
  );
  sky130_fd_sc_hd__xnor3_1 _1945_ (
    .A(_0892_),
    .B(_0964_),
    .C(_0966_),
    .X(_0969_)
  );
  sky130_fd_sc_hd__xnor2_1 _1946_ (
    .A(_0964_),
    .B(_0968_),
    .Y(_0970_)
  );
  sky130_fd_sc_hd__maj3_1 _1947_ (
    .A(_0823_),
    .B(_0901_),
    .C(_0902_),
    .X(_0971_)
  );
  sky130_fd_sc_hd__xnor2_1 _1948_ (
    .A(_0969_),
    .B(_0971_),
    .Y(_0972_)
  );
  sky130_fd_sc_hd__xnor2_1 _1949_ (
    .A(_0963_),
    .B(_0972_),
    .Y(_0973_)
  );
  sky130_fd_sc_hd__maj3_1 _1950_ (
    .A(_0904_),
    .B(_0905_),
    .C(_0909_),
    .X(_0974_)
  );
  sky130_fd_sc_hd__nand2_1 _1951_ (
    .A(carrier_in[10]),
    .B(signal_in[8]),
    .Y(_0975_)
  );
  sky130_fd_sc_hd__nand2_1 _1952_ (
    .A(carrier_in[11]),
    .B(signal_in[7]),
    .Y(_0977_)
  );
  sky130_fd_sc_hd__nand2_1 _1953_ (
    .A(carrier_in[12]),
    .B(signal_in[7]),
    .Y(_0978_)
  );
  sky130_fd_sc_hd__xnor3_1 _1954_ (
    .A(_0903_),
    .B(_0975_),
    .C(_0977_),
    .X(_0979_)
  );
  sky130_fd_sc_hd__maj3_1 _1955_ (
    .A(_0906_),
    .B(_0907_),
    .C(_0908_),
    .X(_0980_)
  );
  sky130_fd_sc_hd__nand2_1 _1956_ (
    .A(carrier_in[13]),
    .B(signal_in[5]),
    .Y(_0981_)
  );
  sky130_fd_sc_hd__nand2_1 _1957_ (
    .A(carrier_in[14]),
    .B(signal_in[4]),
    .Y(_0982_)
  );
  sky130_fd_sc_hd__nand2b_1 _1958_ (
    .A_N(signal_in[3]),
    .B(carrier_in[15]),
    .Y(_0983_)
  );
  sky130_fd_sc_hd__xnor3_1 _1959_ (
    .A(_0981_),
    .B(_0982_),
    .C(_0983_),
    .X(_0984_)
  );
  sky130_fd_sc_hd__xor3_1 _1960_ (
    .A(_0979_),
    .B(_0980_),
    .C(_0984_),
    .X(_0985_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1961_ (
    .A(_0985_),
    .SLEEP(_0974_),
    .X(_0986_)
  );
  sky130_fd_sc_hd__xnor2_1 _1962_ (
    .A(_0974_),
    .B(_0985_),
    .Y(_0988_)
  );
  sky130_fd_sc_hd__xnor2_1 _1963_ (
    .A(_0973_),
    .B(_0988_),
    .Y(_0989_)
  );
  sky130_fd_sc_hd__nor2_1 _1964_ (
    .A(_0962_),
    .B(_0989_),
    .Y(_0990_)
  );
  sky130_fd_sc_hd__xor2_1 _1965_ (
    .A(_0962_),
    .B(_0989_),
    .X(_0991_)
  );
  sky130_fd_sc_hd__and2_0 _1966_ (
    .A(_0961_),
    .B(_0991_),
    .X(_0992_)
  );
  sky130_fd_sc_hd__nor2_1 _1967_ (
    .A(_0961_),
    .B(_0991_),
    .Y(_0993_)
  );
  sky130_fd_sc_hd__nor2_1 _1968_ (
    .A(_0992_),
    .B(_0993_),
    .Y(_0994_)
  );
  sky130_fd_sc_hd__and2_0 _1969_ (
    .A(_0944_),
    .B(_0994_),
    .X(_0995_)
  );
  sky130_fd_sc_hd__xor2_1 _1970_ (
    .A(_0944_),
    .B(_0994_),
    .X(_0996_)
  );
  sky130_fd_sc_hd__xor2_1 _1971_ (
    .A(_0942_),
    .B(_0996_),
    .X(_0997_)
  );
  sky130_fd_sc_hd__o21ai_0 _1972_ (
    .A1(_0918_),
    .A2(_0920_),
    .B1(_0997_),
    .Y(_0999_)
  );
  sky130_fd_sc_hd__xnor2_1 _1973_ (
    .A(_0936_),
    .B(_0997_),
    .Y(_1000_)
  );
  sky130_fd_sc_hd__o21ai_0 _1974_ (
    .A1(_0859_),
    .A2(_0861_),
    .B1(_1000_),
    .Y(_1001_)
  );
  sky130_fd_sc_hd__or3_1 _1975_ (
    .A(_0859_),
    .B(_0861_),
    .C(_1000_),
    .X(_1002_)
  );
  sky130_fd_sc_hd__nand2_1 _1976_ (
    .A(_1001_),
    .B(_1002_),
    .Y(_1003_)
  );
  sky130_fd_sc_hd__nor2_1 _1977_ (
    .A(_0935_),
    .B(_1003_),
    .Y(_1004_)
  );
  sky130_fd_sc_hd__xor2_1 _1978_ (
    .A(_0935_),
    .B(_1003_),
    .X(_1005_)
  );
  sky130_fd_sc_hd__xor2_1 _1979_ (
    .A(_0934_),
    .B(_1005_),
    .X(_1279_[18])
  );
  sky130_fd_sc_hd__a21oi_1 _1980_ (
    .A1(_0934_),
    .A2(_1005_),
    .B1(_1004_),
    .Y(_1006_)
  );
  sky130_fd_sc_hd__o32a_1 _1981_ (
    .A1(_0461_),
    .A2(_0854_),
    .A3(_0941_),
    .B1(_0940_),
    .B2(_0939_),
    .X(_1007_)
  );
  sky130_fd_sc_hd__a21oi_1 _1982_ (
    .A1(_0942_),
    .A2(_0996_),
    .B1(_0995_),
    .Y(_1009_)
  );
  sky130_fd_sc_hd__a31oi_1 _1983_ (
    .A1(carrier_in[1]),
    .A2(signal_in[15]),
    .A3(_0947_),
    .B1(_0868_),
    .Y(_1010_)
  );
  sky130_fd_sc_hd__and2_0 _1984_ (
    .A(_0461_),
    .B(_1010_),
    .X(_1011_)
  );
  sky130_fd_sc_hd__nand2_1 _1985_ (
    .A(_0461_),
    .B(_1010_),
    .Y(_1012_)
  );
  sky130_fd_sc_hd__xnor2_1 _1986_ (
    .A(_0461_),
    .B(_1010_),
    .Y(_1013_)
  );
  sky130_fd_sc_hd__maj3_1 _1987_ (
    .A(_0945_),
    .B(_0958_),
    .C(_0959_),
    .X(_1014_)
  );
  sky130_fd_sc_hd__xnor2_1 _1988_ (
    .A(_1013_),
    .B(_1014_),
    .Y(_1015_)
  );
  sky130_fd_sc_hd__xnor2_1 _1989_ (
    .A(_0938_),
    .B(_1015_),
    .Y(_1016_)
  );
  sky130_fd_sc_hd__a21oi_1 _1990_ (
    .A1(_0948_),
    .A2(_0957_),
    .B1(_0956_),
    .Y(_1017_)
  );
  sky130_fd_sc_hd__maj3_1 _1991_ (
    .A(_0876_),
    .B(_0951_),
    .C(_0952_),
    .X(_1018_)
  );
  sky130_fd_sc_hd__nand2_1 _1992_ (
    .A(carrier_in[4]),
    .B(signal_in[15]),
    .Y(_1020_)
  );
  sky130_fd_sc_hd__nand2_1 _1993_ (
    .A(carrier_in[5]),
    .B(signal_in[14]),
    .Y(_1021_)
  );
  sky130_fd_sc_hd__nand2_1 _1994_ (
    .A(carrier_in[6]),
    .B(signal_in[14]),
    .Y(_1022_)
  );
  sky130_fd_sc_hd__xnor3_1 _1995_ (
    .A(_0953_),
    .B(_1020_),
    .C(_1021_),
    .X(_1023_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _1996_ (
    .A(_1023_),
    .SLEEP(_1018_),
    .X(_1024_)
  );
  sky130_fd_sc_hd__xnor2_1 _1997_ (
    .A(_1018_),
    .B(_1023_),
    .Y(_1025_)
  );
  sky130_fd_sc_hd__xnor2_1 _1998_ (
    .A(_0948_),
    .B(_1025_),
    .Y(_1026_)
  );
  sky130_fd_sc_hd__maj3_1 _1999_ (
    .A(_0963_),
    .B(_0970_),
    .C(_0971_),
    .X(_1027_)
  );
  sky130_fd_sc_hd__xor2_1 _2000_ (
    .A(_1026_),
    .B(_1027_),
    .X(_1028_)
  );
  sky130_fd_sc_hd__xnor2_1 _2001_ (
    .A(_1017_),
    .B(_1028_),
    .Y(_1029_)
  );
  sky130_fd_sc_hd__a21oi_1 _2002_ (
    .A1(_0973_),
    .A2(_0988_),
    .B1(_0986_),
    .Y(_1031_)
  );
  sky130_fd_sc_hd__o22a_1 _2003_ (
    .A1(_0891_),
    .A2(_0967_),
    .B1(_0968_),
    .B2(_0964_),
    .X(_1032_)
  );
  sky130_fd_sc_hd__nand2_1 _2004_ (
    .A(carrier_in[7]),
    .B(signal_in[12]),
    .Y(_1033_)
  );
  sky130_fd_sc_hd__nand2_1 _2005_ (
    .A(carrier_in[8]),
    .B(signal_in[11]),
    .Y(_1034_)
  );
  sky130_fd_sc_hd__nand2_1 _2006_ (
    .A(_0967_),
    .B(_1034_),
    .Y(_1035_)
  );
  sky130_fd_sc_hd__nand2_1 _2007_ (
    .A(carrier_in[9]),
    .B(signal_in[11]),
    .Y(_1036_)
  );
  sky130_fd_sc_hd__o21ai_0 _2008_ (
    .A1(_0966_),
    .A2(_1036_),
    .B1(_1035_),
    .Y(_1037_)
  );
  sky130_fd_sc_hd__xnor3_1 _2009_ (
    .A(_0967_),
    .B(_1033_),
    .C(_1034_),
    .X(_1038_)
  );
  sky130_fd_sc_hd__xnor2_1 _2010_ (
    .A(_1033_),
    .B(_1037_),
    .Y(_1039_)
  );
  sky130_fd_sc_hd__maj3_1 _2011_ (
    .A(_0903_),
    .B(_0975_),
    .C(_0977_),
    .X(_1040_)
  );
  sky130_fd_sc_hd__xnor2_1 _2012_ (
    .A(_1038_),
    .B(_1040_),
    .Y(_1042_)
  );
  sky130_fd_sc_hd__xnor2_1 _2013_ (
    .A(_1032_),
    .B(_1042_),
    .Y(_1043_)
  );
  sky130_fd_sc_hd__maj3_1 _2014_ (
    .A(_0979_),
    .B(_0980_),
    .C(_0984_),
    .X(_1044_)
  );
  sky130_fd_sc_hd__nand2_1 _2015_ (
    .A(carrier_in[10]),
    .B(signal_in[9]),
    .Y(_1045_)
  );
  sky130_fd_sc_hd__nand2_1 _2016_ (
    .A(carrier_in[11]),
    .B(signal_in[8]),
    .Y(_1046_)
  );
  sky130_fd_sc_hd__nand2_1 _2017_ (
    .A(carrier_in[12]),
    .B(signal_in[8]),
    .Y(_1047_)
  );
  sky130_fd_sc_hd__xnor3_1 _2018_ (
    .A(_0978_),
    .B(_1045_),
    .C(_1046_),
    .X(_1048_)
  );
  sky130_fd_sc_hd__maj3_1 _2019_ (
    .A(_0981_),
    .B(_0982_),
    .C(_0983_),
    .X(_1049_)
  );
  sky130_fd_sc_hd__nand2_1 _2020_ (
    .A(carrier_in[13]),
    .B(signal_in[6]),
    .Y(_1050_)
  );
  sky130_fd_sc_hd__nand2_1 _2021_ (
    .A(carrier_in[14]),
    .B(signal_in[5]),
    .Y(_1051_)
  );
  sky130_fd_sc_hd__nand2b_1 _2022_ (
    .A_N(signal_in[4]),
    .B(carrier_in[15]),
    .Y(_1053_)
  );
  sky130_fd_sc_hd__xnor3_1 _2023_ (
    .A(_1050_),
    .B(_1051_),
    .C(_1053_),
    .X(_1054_)
  );
  sky130_fd_sc_hd__nand2b_1 _2024_ (
    .A_N(_1049_),
    .B(_1054_),
    .Y(_1055_)
  );
  sky130_fd_sc_hd__xnor2_1 _2025_ (
    .A(_1049_),
    .B(_1054_),
    .Y(_1056_)
  );
  sky130_fd_sc_hd__xnor3_1 _2026_ (
    .A(_1048_),
    .B(_1049_),
    .C(_1054_),
    .X(_1057_)
  );
  sky130_fd_sc_hd__nand2_1 _2027_ (
    .A(_1044_),
    .B(_1057_),
    .Y(_1058_)
  );
  sky130_fd_sc_hd__xor2_1 _2028_ (
    .A(_1044_),
    .B(_1057_),
    .X(_1059_)
  );
  sky130_fd_sc_hd__nand2_1 _2029_ (
    .A(_1043_),
    .B(_1059_),
    .Y(_1060_)
  );
  sky130_fd_sc_hd__xnor2_1 _2030_ (
    .A(_1043_),
    .B(_1059_),
    .Y(_1061_)
  );
  sky130_fd_sc_hd__nor2_1 _2031_ (
    .A(_1031_),
    .B(_1061_),
    .Y(_1062_)
  );
  sky130_fd_sc_hd__xor2_1 _2032_ (
    .A(_1031_),
    .B(_1061_),
    .X(_1064_)
  );
  sky130_fd_sc_hd__xor2_1 _2033_ (
    .A(_1029_),
    .B(_1064_),
    .X(_1065_)
  );
  sky130_fd_sc_hd__o21ai_0 _2034_ (
    .A1(_0990_),
    .A2(_0992_),
    .B1(_1065_),
    .Y(_1066_)
  );
  sky130_fd_sc_hd__nor3_1 _2035_ (
    .A(_0990_),
    .B(_0992_),
    .C(_1065_),
    .Y(_1067_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2036_ (
    .A(_1066_),
    .SLEEP(_1067_),
    .X(_1068_)
  );
  sky130_fd_sc_hd__nand2_1 _2037_ (
    .A(_1016_),
    .B(_1068_),
    .Y(_1069_)
  );
  sky130_fd_sc_hd__xor2_1 _2038_ (
    .A(_1016_),
    .B(_1068_),
    .X(_1070_)
  );
  sky130_fd_sc_hd__clkinv_1 _2039_ (
    .A(_1070_),
    .Y(_1071_)
  );
  sky130_fd_sc_hd__xor2_1 _2040_ (
    .A(_1009_),
    .B(_1070_),
    .X(_1072_)
  );
  sky130_fd_sc_hd__xnor2_1 _2041_ (
    .A(_1007_),
    .B(_1072_),
    .Y(_1073_)
  );
  sky130_fd_sc_hd__a21oi_1 _2042_ (
    .A1(_0999_),
    .A2(_1001_),
    .B1(_1073_),
    .Y(_1075_)
  );
  sky130_fd_sc_hd__nand3_1 _2043_ (
    .A(_0999_),
    .B(_1001_),
    .C(_1073_),
    .Y(_1076_)
  );
  sky130_fd_sc_hd__nor2b_1 _2044_ (
    .A(_1075_),
    .B_N(_1076_),
    .Y(_1077_)
  );
  sky130_fd_sc_hd__xnor2_1 _2045_ (
    .A(_1006_),
    .B(_1077_),
    .Y(_1279_[19])
  );
  sky130_fd_sc_hd__o211ai_1 _2046_ (
    .A1(_0930_),
    .A2(_0933_),
    .B1(_1005_),
    .C1(_1077_),
    .Y(_1078_)
  );
  sky130_fd_sc_hd__a21oi_1 _2047_ (
    .A1(_1004_),
    .A2(_1076_),
    .B1(_1075_),
    .Y(_1079_)
  );
  sky130_fd_sc_hd__nand2_1 _2048_ (
    .A(_1078_),
    .B(_1079_),
    .Y(_1080_)
  );
  sky130_fd_sc_hd__maj3_1 _2049_ (
    .A(_1007_),
    .B(_1009_),
    .C(_1071_),
    .X(_1081_)
  );
  sky130_fd_sc_hd__o32a_1 _2050_ (
    .A1(_0461_),
    .A2(_0937_),
    .A3(_1015_),
    .B1(_1014_),
    .B2(_1013_),
    .X(_1082_)
  );
  sky130_fd_sc_hd__maj3_1 _2051_ (
    .A(_1017_),
    .B(_1026_),
    .C(_1027_),
    .X(_1083_)
  );
  sky130_fd_sc_hd__nor2_1 _2052_ (
    .A(_1011_),
    .B(_1083_),
    .Y(_1085_)
  );
  sky130_fd_sc_hd__xnor2_1 _2053_ (
    .A(_1012_),
    .B(_1083_),
    .Y(_1086_)
  );
  sky130_fd_sc_hd__a21oi_1 _2054_ (
    .A1(_1029_),
    .A2(_1064_),
    .B1(_1062_),
    .Y(_1087_)
  );
  sky130_fd_sc_hd__a21oi_1 _2055_ (
    .A1(_0948_),
    .A2(_1025_),
    .B1(_1024_),
    .Y(_1088_)
  );
  sky130_fd_sc_hd__maj3_1 _2056_ (
    .A(_0953_),
    .B(_1020_),
    .C(_1021_),
    .X(_1089_)
  );
  sky130_fd_sc_hd__nand2_1 _2057_ (
    .A(carrier_in[5]),
    .B(signal_in[15]),
    .Y(_1090_)
  );
  sky130_fd_sc_hd__xor2_1 _2058_ (
    .A(_1022_),
    .B(_1090_),
    .X(_1091_)
  );
  sky130_fd_sc_hd__xnor2_1 _2059_ (
    .A(_1020_),
    .B(_1091_),
    .Y(_1092_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2060_ (
    .A(_1092_),
    .SLEEP(_1089_),
    .X(_1093_)
  );
  sky130_fd_sc_hd__xnor2_1 _2061_ (
    .A(_1089_),
    .B(_1092_),
    .Y(_1094_)
  );
  sky130_fd_sc_hd__xnor2_1 _2062_ (
    .A(_0948_),
    .B(_1094_),
    .Y(_1096_)
  );
  sky130_fd_sc_hd__maj3_1 _2063_ (
    .A(_1032_),
    .B(_1039_),
    .C(_1040_),
    .X(_1097_)
  );
  sky130_fd_sc_hd__xor2_1 _2064_ (
    .A(_1096_),
    .B(_1097_),
    .X(_1098_)
  );
  sky130_fd_sc_hd__xnor2_1 _2065_ (
    .A(_1088_),
    .B(_1098_),
    .Y(_1099_)
  );
  sky130_fd_sc_hd__nand2_1 _2066_ (
    .A(_1058_),
    .B(_1060_),
    .Y(_1100_)
  );
  sky130_fd_sc_hd__o22a_1 _2067_ (
    .A1(_0966_),
    .A2(_1036_),
    .B1(_1037_),
    .B2(_1033_),
    .X(_1101_)
  );
  sky130_fd_sc_hd__nand2_1 _2068_ (
    .A(carrier_in[7]),
    .B(signal_in[13]),
    .Y(_1102_)
  );
  sky130_fd_sc_hd__nand2_1 _2069_ (
    .A(carrier_in[8]),
    .B(signal_in[12]),
    .Y(_1103_)
  );
  sky130_fd_sc_hd__nand2_1 _2070_ (
    .A(carrier_in[9]),
    .B(signal_in[12]),
    .Y(_1104_)
  );
  sky130_fd_sc_hd__xnor2_1 _2071_ (
    .A(_1036_),
    .B(_1103_),
    .Y(_1105_)
  );
  sky130_fd_sc_hd__xnor2_1 _2072_ (
    .A(_1102_),
    .B(_1105_),
    .Y(_1107_)
  );
  sky130_fd_sc_hd__maj3_1 _2073_ (
    .A(_0978_),
    .B(_1045_),
    .C(_1046_),
    .X(_1108_)
  );
  sky130_fd_sc_hd__xnor2_1 _2074_ (
    .A(_1107_),
    .B(_1108_),
    .Y(_1109_)
  );
  sky130_fd_sc_hd__xor2_1 _2075_ (
    .A(_1101_),
    .B(_1109_),
    .X(_1110_)
  );
  sky130_fd_sc_hd__a21boi_0 _2076_ (
    .A1(_1048_),
    .A2(_1056_),
    .B1_N(_1055_),
    .Y(_1111_)
  );
  sky130_fd_sc_hd__nand2_1 _2077_ (
    .A(carrier_in[10]),
    .B(signal_in[10]),
    .Y(_1112_)
  );
  sky130_fd_sc_hd__nand2_1 _2078_ (
    .A(carrier_in[11]),
    .B(signal_in[9]),
    .Y(_1113_)
  );
  sky130_fd_sc_hd__nand2_1 _2079_ (
    .A(carrier_in[12]),
    .B(signal_in[9]),
    .Y(_1114_)
  );
  sky130_fd_sc_hd__xor2_1 _2080_ (
    .A(_1047_),
    .B(_1113_),
    .X(_1115_)
  );
  sky130_fd_sc_hd__xnor2_1 _2081_ (
    .A(_1112_),
    .B(_1115_),
    .Y(_1116_)
  );
  sky130_fd_sc_hd__maj3_1 _2082_ (
    .A(_1050_),
    .B(_1051_),
    .C(_1053_),
    .X(_1118_)
  );
  sky130_fd_sc_hd__nand2_1 _2083_ (
    .A(carrier_in[13]),
    .B(signal_in[7]),
    .Y(_1119_)
  );
  sky130_fd_sc_hd__nand2_1 _2084_ (
    .A(carrier_in[14]),
    .B(signal_in[6]),
    .Y(_1120_)
  );
  sky130_fd_sc_hd__nand2b_1 _2085_ (
    .A_N(signal_in[5]),
    .B(carrier_in[15]),
    .Y(_1121_)
  );
  sky130_fd_sc_hd__xor2_1 _2086_ (
    .A(_1120_),
    .B(_1121_),
    .X(_1122_)
  );
  sky130_fd_sc_hd__xor2_1 _2087_ (
    .A(_1119_),
    .B(_1122_),
    .X(_1123_)
  );
  sky130_fd_sc_hd__nor2_1 _2088_ (
    .A(_1118_),
    .B(_1123_),
    .Y(_1124_)
  );
  sky130_fd_sc_hd__xor3_1 _2089_ (
    .A(_1118_),
    .B(_1119_),
    .C(_1122_),
    .X(_1125_)
  );
  sky130_fd_sc_hd__xor2_1 _2090_ (
    .A(_1116_),
    .B(_1125_),
    .X(_1126_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2091_ (
    .A(_1126_),
    .SLEEP(_1111_),
    .X(_1127_)
  );
  sky130_fd_sc_hd__xnor2_1 _2092_ (
    .A(_1111_),
    .B(_1126_),
    .Y(_1129_)
  );
  sky130_fd_sc_hd__xnor2_1 _2093_ (
    .A(_1110_),
    .B(_1129_),
    .Y(_1130_)
  );
  sky130_fd_sc_hd__a21oi_1 _2094_ (
    .A1(_1058_),
    .A2(_1060_),
    .B1(_1130_),
    .Y(_1131_)
  );
  sky130_fd_sc_hd__xnor2_1 _2095_ (
    .A(_1100_),
    .B(_1130_),
    .Y(_1132_)
  );
  sky130_fd_sc_hd__xor2_1 _2096_ (
    .A(_1099_),
    .B(_1132_),
    .X(_1133_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2097_ (
    .A(_1133_),
    .SLEEP(_1087_),
    .X(_1134_)
  );
  sky130_fd_sc_hd__xnor2_1 _2098_ (
    .A(_1087_),
    .B(_1133_),
    .Y(_1135_)
  );
  sky130_fd_sc_hd__xnor2_1 _2099_ (
    .A(_1086_),
    .B(_1135_),
    .Y(_1136_)
  );
  sky130_fd_sc_hd__a21oi_1 _2100_ (
    .A1(_1066_),
    .A2(_1069_),
    .B1(_1136_),
    .Y(_1137_)
  );
  sky130_fd_sc_hd__and3_1 _2101_ (
    .A(_1066_),
    .B(_1069_),
    .C(_1136_),
    .X(_1138_)
  );
  sky130_fd_sc_hd__nor2_1 _2102_ (
    .A(_1137_),
    .B(_1138_),
    .Y(_1140_)
  );
  sky130_fd_sc_hd__nor3_1 _2103_ (
    .A(_1082_),
    .B(_1137_),
    .C(_1138_),
    .Y(_1141_)
  );
  sky130_fd_sc_hd__xor2_1 _2104_ (
    .A(_1082_),
    .B(_1140_),
    .X(_1142_)
  );
  sky130_fd_sc_hd__nor2_1 _2105_ (
    .A(_1081_),
    .B(_1142_),
    .Y(_1143_)
  );
  sky130_fd_sc_hd__xor2_1 _2106_ (
    .A(_1081_),
    .B(_1142_),
    .X(_1144_)
  );
  sky130_fd_sc_hd__clkinv_1 _2107_ (
    .A(_1144_),
    .Y(_1145_)
  );
  sky130_fd_sc_hd__xnor2_1 _2108_ (
    .A(_1080_),
    .B(_1145_),
    .Y(_1279_[20])
  );
  sky130_fd_sc_hd__a21oi_1 _2109_ (
    .A1(_1080_),
    .A2(_1144_),
    .B1(_1143_),
    .Y(_1146_)
  );
  sky130_fd_sc_hd__a21o_1 _2110_ (
    .A1(_1086_),
    .A2(_1135_),
    .B1(_1134_),
    .X(_1147_)
  );
  sky130_fd_sc_hd__maj3_1 _2111_ (
    .A(_1088_),
    .B(_1096_),
    .C(_1097_),
    .X(_1148_)
  );
  sky130_fd_sc_hd__nor2_1 _2112_ (
    .A(_1011_),
    .B(_1148_),
    .Y(_1150_)
  );
  sky130_fd_sc_hd__xnor2_1 _2113_ (
    .A(_1012_),
    .B(_1148_),
    .Y(_1151_)
  );
  sky130_fd_sc_hd__a21oi_1 _2114_ (
    .A1(_1099_),
    .A2(_1132_),
    .B1(_1131_),
    .Y(_1152_)
  );
  sky130_fd_sc_hd__a21oi_1 _2115_ (
    .A1(_0948_),
    .A2(_1094_),
    .B1(_1093_),
    .Y(_1153_)
  );
  sky130_fd_sc_hd__maj3_1 _2116_ (
    .A(_1020_),
    .B(_1022_),
    .C(_1090_),
    .X(_1154_)
  );
  sky130_fd_sc_hd__o21ai_0 _2117_ (
    .A1(carrier_in[6]),
    .A2(carrier_in[5]),
    .B1(signal_in[15]),
    .Y(_1155_)
  );
  sky130_fd_sc_hd__a21oi_1 _2118_ (
    .A1(carrier_in[6]),
    .A2(carrier_in[5]),
    .B1(_1155_),
    .Y(_1156_)
  );
  sky130_fd_sc_hd__mux2i_1 _2119_ (
    .A0(_1020_),
    .A1(carrier_in[4]),
    .S(_1156_),
    .Y(_1157_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2120_ (
    .A(_1157_),
    .SLEEP(_1154_),
    .X(_1158_)
  );
  sky130_fd_sc_hd__xor2_1 _2121_ (
    .A(_1154_),
    .B(_1157_),
    .X(_1159_)
  );
  sky130_fd_sc_hd__nor2_1 _2122_ (
    .A(_0949_),
    .B(_1159_),
    .Y(_1161_)
  );
  sky130_fd_sc_hd__xnor2_1 _2123_ (
    .A(_0948_),
    .B(_1159_),
    .Y(_1162_)
  );
  sky130_fd_sc_hd__maj3_1 _2124_ (
    .A(_1101_),
    .B(_1107_),
    .C(_1108_),
    .X(_1163_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2125_ (
    .A(_1162_),
    .SLEEP(_1163_),
    .X(_1164_)
  );
  sky130_fd_sc_hd__xnor2_1 _2126_ (
    .A(_1162_),
    .B(_1163_),
    .Y(_1165_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2127_ (
    .A(_1165_),
    .SLEEP(_1153_),
    .X(_1166_)
  );
  sky130_fd_sc_hd__xor2_1 _2128_ (
    .A(_1153_),
    .B(_1165_),
    .X(_1167_)
  );
  sky130_fd_sc_hd__a21oi_1 _2129_ (
    .A1(_1110_),
    .A2(_1129_),
    .B1(_1127_),
    .Y(_1168_)
  );
  sky130_fd_sc_hd__maj3_1 _2130_ (
    .A(_1036_),
    .B(_1102_),
    .C(_1103_),
    .X(_1169_)
  );
  sky130_fd_sc_hd__nand2_1 _2131_ (
    .A(carrier_in[7]),
    .B(signal_in[14]),
    .Y(_1170_)
  );
  sky130_fd_sc_hd__nand2_1 _2132_ (
    .A(carrier_in[8]),
    .B(signal_in[13]),
    .Y(_1172_)
  );
  sky130_fd_sc_hd__nand2_1 _2133_ (
    .A(carrier_in[9]),
    .B(signal_in[13]),
    .Y(_1173_)
  );
  sky130_fd_sc_hd__nand2_1 _2134_ (
    .A(_1104_),
    .B(_1172_),
    .Y(_1174_)
  );
  sky130_fd_sc_hd__o21ai_0 _2135_ (
    .A1(_1103_),
    .A2(_1173_),
    .B1(_1174_),
    .Y(_1175_)
  );
  sky130_fd_sc_hd__xnor2_1 _2136_ (
    .A(_1170_),
    .B(_1175_),
    .Y(_1176_)
  );
  sky130_fd_sc_hd__maj3_1 _2137_ (
    .A(_1047_),
    .B(_1112_),
    .C(_1113_),
    .X(_1177_)
  );
  sky130_fd_sc_hd__xnor2_1 _2138_ (
    .A(_1176_),
    .B(_1177_),
    .Y(_1178_)
  );
  sky130_fd_sc_hd__xor2_1 _2139_ (
    .A(_1169_),
    .B(_1178_),
    .X(_1179_)
  );
  sky130_fd_sc_hd__a21oi_1 _2140_ (
    .A1(_1116_),
    .A2(_1125_),
    .B1(_1124_),
    .Y(_1180_)
  );
  sky130_fd_sc_hd__nand2_1 _2141_ (
    .A(carrier_in[10]),
    .B(signal_in[11]),
    .Y(_1181_)
  );
  sky130_fd_sc_hd__nand2_1 _2142_ (
    .A(carrier_in[11]),
    .B(signal_in[10]),
    .Y(_1183_)
  );
  sky130_fd_sc_hd__nand2_1 _2143_ (
    .A(carrier_in[12]),
    .B(signal_in[10]),
    .Y(_1184_)
  );
  sky130_fd_sc_hd__xor2_1 _2144_ (
    .A(_1114_),
    .B(_1183_),
    .X(_1185_)
  );
  sky130_fd_sc_hd__xnor2_1 _2145_ (
    .A(_1181_),
    .B(_1185_),
    .Y(_1186_)
  );
  sky130_fd_sc_hd__maj3_1 _2146_ (
    .A(_1119_),
    .B(_1120_),
    .C(_1121_),
    .X(_1187_)
  );
  sky130_fd_sc_hd__nand2_1 _2147_ (
    .A(carrier_in[13]),
    .B(signal_in[8]),
    .Y(_1188_)
  );
  sky130_fd_sc_hd__nand2_1 _2148_ (
    .A(carrier_in[14]),
    .B(signal_in[7]),
    .Y(_1189_)
  );
  sky130_fd_sc_hd__nand2b_1 _2149_ (
    .A_N(signal_in[6]),
    .B(carrier_in[15]),
    .Y(_1190_)
  );
  sky130_fd_sc_hd__xnor2_1 _2150_ (
    .A(_1189_),
    .B(_1190_),
    .Y(_1191_)
  );
  sky130_fd_sc_hd__xnor2_1 _2151_ (
    .A(_1188_),
    .B(_1191_),
    .Y(_1192_)
  );
  sky130_fd_sc_hd__nor2_1 _2152_ (
    .A(_1187_),
    .B(_1192_),
    .Y(_1194_)
  );
  sky130_fd_sc_hd__xor2_1 _2153_ (
    .A(_1187_),
    .B(_1192_),
    .X(_1195_)
  );
  sky130_fd_sc_hd__and2_0 _2154_ (
    .A(_1186_),
    .B(_1195_),
    .X(_1196_)
  );
  sky130_fd_sc_hd__xnor2_1 _2155_ (
    .A(_1186_),
    .B(_1195_),
    .Y(_1197_)
  );
  sky130_fd_sc_hd__nor2_1 _2156_ (
    .A(_1180_),
    .B(_1197_),
    .Y(_1198_)
  );
  sky130_fd_sc_hd__xor2_1 _2157_ (
    .A(_1180_),
    .B(_1197_),
    .X(_1199_)
  );
  sky130_fd_sc_hd__xnor2_1 _2158_ (
    .A(_1179_),
    .B(_1199_),
    .Y(_1200_)
  );
  sky130_fd_sc_hd__xnor2_1 _2159_ (
    .A(_1168_),
    .B(_1200_),
    .Y(_1201_)
  );
  sky130_fd_sc_hd__xnor2_1 _2160_ (
    .A(_1167_),
    .B(_1201_),
    .Y(_1202_)
  );
  sky130_fd_sc_hd__nor2_1 _2161_ (
    .A(_1152_),
    .B(_1202_),
    .Y(_1203_)
  );
  sky130_fd_sc_hd__xor2_1 _2162_ (
    .A(_1152_),
    .B(_1202_),
    .X(_1205_)
  );
  sky130_fd_sc_hd__xor2_1 _2163_ (
    .A(_1151_),
    .B(_1205_),
    .X(_1206_)
  );
  sky130_fd_sc_hd__xnor2_1 _2164_ (
    .A(_1147_),
    .B(_1206_),
    .Y(_1207_)
  );
  sky130_fd_sc_hd__xnor2_1 _2165_ (
    .A(_1085_),
    .B(_1207_),
    .Y(_1208_)
  );
  sky130_fd_sc_hd__o21a_1 _2166_ (
    .A1(_1137_),
    .A2(_1141_),
    .B1(_1208_),
    .X(_1209_)
  );
  sky130_fd_sc_hd__or3_1 _2167_ (
    .A(_1137_),
    .B(_1141_),
    .C(_1208_),
    .X(_1210_)
  );
  sky130_fd_sc_hd__nand2b_1 _2168_ (
    .A_N(_1209_),
    .B(_1210_),
    .Y(_1211_)
  );
  sky130_fd_sc_hd__xor2_1 _2169_ (
    .A(_1146_),
    .B(_1211_),
    .X(_1279_[21])
  );
  sky130_fd_sc_hd__a211oi_1 _2170_ (
    .A1(_1078_),
    .A2(_1079_),
    .B1(_1145_),
    .C1(_1211_),
    .Y(_1212_)
  );
  sky130_fd_sc_hd__a21o_1 _2171_ (
    .A1(_1143_),
    .A2(_1210_),
    .B1(_1209_),
    .X(_1213_)
  );
  sky130_fd_sc_hd__maj3_1 _2172_ (
    .A(_1085_),
    .B(_1147_),
    .C(_1206_),
    .X(_1215_)
  );
  sky130_fd_sc_hd__a21oi_1 _2173_ (
    .A1(_1151_),
    .A2(_1205_),
    .B1(_1203_),
    .Y(_1216_)
  );
  sky130_fd_sc_hd__nor2_1 _2174_ (
    .A(_1164_),
    .B(_1166_),
    .Y(_1217_)
  );
  sky130_fd_sc_hd__nor3_1 _2175_ (
    .A(_1012_),
    .B(_1164_),
    .C(_1166_),
    .Y(_1218_)
  );
  sky130_fd_sc_hd__nor2_1 _2176_ (
    .A(_1011_),
    .B(_1217_),
    .Y(_1219_)
  );
  sky130_fd_sc_hd__nor2_1 _2177_ (
    .A(_1218_),
    .B(_1219_),
    .Y(_1220_)
  );
  sky130_fd_sc_hd__maj3_1 _2178_ (
    .A(_1167_),
    .B(_1168_),
    .C(_1200_),
    .X(_1221_)
  );
  sky130_fd_sc_hd__nor2_1 _2179_ (
    .A(_1158_),
    .B(_1161_),
    .Y(_1222_)
  );
  sky130_fd_sc_hd__a21oi_1 _2180_ (
    .A1(_1020_),
    .A2(_1155_),
    .B1(_1158_),
    .Y(_1223_)
  );
  sky130_fd_sc_hd__xnor2_1 _2181_ (
    .A(_0948_),
    .B(_1223_),
    .Y(_1224_)
  );
  sky130_fd_sc_hd__clkinv_1 _2182_ (
    .A(_1224_),
    .Y(_1226_)
  );
  sky130_fd_sc_hd__maj3_1 _2183_ (
    .A(_1169_),
    .B(_1176_),
    .C(_1177_),
    .X(_1227_)
  );
  sky130_fd_sc_hd__xnor2_1 _2184_ (
    .A(_1224_),
    .B(_1227_),
    .Y(_1228_)
  );
  sky130_fd_sc_hd__xnor2_1 _2185_ (
    .A(_1222_),
    .B(_1228_),
    .Y(_1229_)
  );
  sky130_fd_sc_hd__a21oi_1 _2186_ (
    .A1(_1179_),
    .A2(_1199_),
    .B1(_1198_),
    .Y(_1230_)
  );
  sky130_fd_sc_hd__maj3_1 _2187_ (
    .A(_1104_),
    .B(_1170_),
    .C(_1172_),
    .X(_1231_)
  );
  sky130_fd_sc_hd__nand2_1 _2188_ (
    .A(carrier_in[7]),
    .B(signal_in[15]),
    .Y(_1232_)
  );
  sky130_fd_sc_hd__nand2_1 _2189_ (
    .A(carrier_in[8]),
    .B(signal_in[14]),
    .Y(_1233_)
  );
  sky130_fd_sc_hd__nand2_1 _2190_ (
    .A(carrier_in[9]),
    .B(signal_in[14]),
    .Y(_1234_)
  );
  sky130_fd_sc_hd__nand2_1 _2191_ (
    .A(_1173_),
    .B(_1233_),
    .Y(_1235_)
  );
  sky130_fd_sc_hd__o21ai_0 _2192_ (
    .A1(_1172_),
    .A2(_1234_),
    .B1(_1235_),
    .Y(_1237_)
  );
  sky130_fd_sc_hd__xnor2_1 _2193_ (
    .A(_1232_),
    .B(_1237_),
    .Y(_1238_)
  );
  sky130_fd_sc_hd__maj3_1 _2194_ (
    .A(_1114_),
    .B(_1181_),
    .C(_1183_),
    .X(_1239_)
  );
  sky130_fd_sc_hd__xnor2_1 _2195_ (
    .A(_1238_),
    .B(_1239_),
    .Y(_1240_)
  );
  sky130_fd_sc_hd__xor2_1 _2196_ (
    .A(_1231_),
    .B(_1240_),
    .X(_1241_)
  );
  sky130_fd_sc_hd__nand2_1 _2197_ (
    .A(carrier_in[10]),
    .B(signal_in[12]),
    .Y(_1242_)
  );
  sky130_fd_sc_hd__nand2_1 _2198_ (
    .A(carrier_in[11]),
    .B(signal_in[11]),
    .Y(_1243_)
  );
  sky130_fd_sc_hd__nand2_1 _2199_ (
    .A(carrier_in[12]),
    .B(signal_in[11]),
    .Y(_1244_)
  );
  sky130_fd_sc_hd__xor2_1 _2200_ (
    .A(_1184_),
    .B(_1243_),
    .X(_1245_)
  );
  sky130_fd_sc_hd__xnor2_1 _2201_ (
    .A(_1242_),
    .B(_1245_),
    .Y(_1246_)
  );
  sky130_fd_sc_hd__maj3_1 _2202_ (
    .A(_1188_),
    .B(_1189_),
    .C(_1190_),
    .X(_1248_)
  );
  sky130_fd_sc_hd__nand2_1 _2203_ (
    .A(carrier_in[13]),
    .B(signal_in[9]),
    .Y(_1249_)
  );
  sky130_fd_sc_hd__nand2_1 _2204_ (
    .A(carrier_in[14]),
    .B(signal_in[8]),
    .Y(_1250_)
  );
  sky130_fd_sc_hd__nand2b_1 _2205_ (
    .A_N(signal_in[7]),
    .B(carrier_in[15]),
    .Y(_1251_)
  );
  sky130_fd_sc_hd__xor3_1 _2206_ (
    .A(_1249_),
    .B(_1250_),
    .C(_1251_),
    .X(_1252_)
  );
  sky130_fd_sc_hd__nor2_1 _2207_ (
    .A(_1248_),
    .B(_1252_),
    .Y(_1253_)
  );
  sky130_fd_sc_hd__xor2_1 _2208_ (
    .A(_1248_),
    .B(_1252_),
    .X(_1254_)
  );
  sky130_fd_sc_hd__xor2_1 _2209_ (
    .A(_1246_),
    .B(_1254_),
    .X(_1255_)
  );
  sky130_fd_sc_hd__o21ai_0 _2210_ (
    .A1(_1194_),
    .A2(_1196_),
    .B1(_1255_),
    .Y(_1256_)
  );
  sky130_fd_sc_hd__nor3_1 _2211_ (
    .A(_1194_),
    .B(_1196_),
    .C(_1255_),
    .Y(_1257_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2212_ (
    .A(_1256_),
    .SLEEP(_1257_),
    .X(_1259_)
  );
  sky130_fd_sc_hd__nand2_1 _2213_ (
    .A(_1241_),
    .B(_1259_),
    .Y(_1260_)
  );
  sky130_fd_sc_hd__xnor2_1 _2214_ (
    .A(_1241_),
    .B(_1259_),
    .Y(_1261_)
  );
  sky130_fd_sc_hd__xnor2_1 _2215_ (
    .A(_1230_),
    .B(_1261_),
    .Y(_1262_)
  );
  sky130_fd_sc_hd__xnor2_1 _2216_ (
    .A(_1229_),
    .B(_1262_),
    .Y(_1263_)
  );
  sky130_fd_sc_hd__nor2_1 _2217_ (
    .A(_1221_),
    .B(_1263_),
    .Y(_1264_)
  );
  sky130_fd_sc_hd__xor2_1 _2218_ (
    .A(_1221_),
    .B(_1263_),
    .X(_1265_)
  );
  sky130_fd_sc_hd__xor2_1 _2219_ (
    .A(_1220_),
    .B(_1265_),
    .X(_1266_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2220_ (
    .A(_1266_),
    .SLEEP(_1216_),
    .X(_1267_)
  );
  sky130_fd_sc_hd__xnor2_1 _2221_ (
    .A(_1216_),
    .B(_1266_),
    .Y(_1268_)
  );
  sky130_fd_sc_hd__xor2_1 _2222_ (
    .A(_1150_),
    .B(_1268_),
    .X(_1270_)
  );
  sky130_fd_sc_hd__nor2_1 _2223_ (
    .A(_1215_),
    .B(_1270_),
    .Y(_1271_)
  );
  sky130_fd_sc_hd__and2_0 _2224_ (
    .A(_1215_),
    .B(_1270_),
    .X(_1272_)
  );
  sky130_fd_sc_hd__nor2_1 _2225_ (
    .A(_1271_),
    .B(_1272_),
    .Y(_1273_)
  );
  sky130_fd_sc_hd__o21a_1 _2226_ (
    .A1(_1212_),
    .A2(_1213_),
    .B1(_1273_),
    .X(_1274_)
  );
  sky130_fd_sc_hd__nor3_1 _2227_ (
    .A(_1212_),
    .B(_1213_),
    .C(_1273_),
    .Y(_1275_)
  );
  sky130_fd_sc_hd__nor2_1 _2228_ (
    .A(_1274_),
    .B(_1275_),
    .Y(_1279_[22])
  );
  sky130_fd_sc_hd__nor2_1 _2229_ (
    .A(_1272_),
    .B(_1274_),
    .Y(_1276_)
  );
  sky130_fd_sc_hd__a21oi_1 _2230_ (
    .A1(_1150_),
    .A2(_1268_),
    .B1(_1267_),
    .Y(_1277_)
  );
  sky130_fd_sc_hd__a21oi_1 _2231_ (
    .A1(_1220_),
    .A2(_1265_),
    .B1(_1264_),
    .Y(_1278_)
  );
  sky130_fd_sc_hd__maj3_1 _2232_ (
    .A(_1222_),
    .B(_1224_),
    .C(_1227_),
    .X(_0001_)
  );
  sky130_fd_sc_hd__nor2_1 _2233_ (
    .A(_1011_),
    .B(_0001_),
    .Y(_0002_)
  );
  sky130_fd_sc_hd__xnor2_1 _2234_ (
    .A(_1012_),
    .B(_0001_),
    .Y(_0003_)
  );
  sky130_fd_sc_hd__maj3_1 _2235_ (
    .A(_1229_),
    .B(_1230_),
    .C(_1261_),
    .X(_0004_)
  );
  sky130_fd_sc_hd__a21oi_1 _2236_ (
    .A1(_0948_),
    .A2(_1223_),
    .B1(_1158_),
    .Y(_0005_)
  );
  sky130_fd_sc_hd__a21o_1 _2237_ (
    .A1(_0948_),
    .A2(_1223_),
    .B1(_1158_),
    .X(_0006_)
  );
  sky130_fd_sc_hd__maj3_1 _2238_ (
    .A(_1231_),
    .B(_1238_),
    .C(_1239_),
    .X(_0007_)
  );
  sky130_fd_sc_hd__nor2_1 _2239_ (
    .A(_1224_),
    .B(_0007_),
    .Y(_0008_)
  );
  sky130_fd_sc_hd__xor2_1 _2240_ (
    .A(_1224_),
    .B(_0007_),
    .X(_0009_)
  );
  sky130_fd_sc_hd__xnor2_1 _2241_ (
    .A(_0006_),
    .B(_0009_),
    .Y(_0010_)
  );
  sky130_fd_sc_hd__maj3_1 _2242_ (
    .A(_1173_),
    .B(_1232_),
    .C(_1233_),
    .X(_0012_)
  );
  sky130_fd_sc_hd__nand2_1 _2243_ (
    .A(carrier_in[8]),
    .B(signal_in[15]),
    .Y(_0013_)
  );
  sky130_fd_sc_hd__and3_1 _2244_ (
    .A(carrier_in[9]),
    .B(carrier_in[8]),
    .C(signal_in[15]),
    .X(_0014_)
  );
  sky130_fd_sc_hd__xor2_1 _2245_ (
    .A(_1234_),
    .B(_0013_),
    .X(_0015_)
  );
  sky130_fd_sc_hd__xnor2_1 _2246_ (
    .A(_1232_),
    .B(_0015_),
    .Y(_0016_)
  );
  sky130_fd_sc_hd__clkinv_1 _2247_ (
    .A(_0016_),
    .Y(_0017_)
  );
  sky130_fd_sc_hd__maj3_1 _2248_ (
    .A(_1184_),
    .B(_1242_),
    .C(_1243_),
    .X(_0018_)
  );
  sky130_fd_sc_hd__xnor2_1 _2249_ (
    .A(_0016_),
    .B(_0018_),
    .Y(_0019_)
  );
  sky130_fd_sc_hd__xnor2_1 _2250_ (
    .A(_0012_),
    .B(_0019_),
    .Y(_0020_)
  );
  sky130_fd_sc_hd__a21oi_1 _2251_ (
    .A1(_1246_),
    .A2(_1254_),
    .B1(_1253_),
    .Y(_0021_)
  );
  sky130_fd_sc_hd__nand2_1 _2252_ (
    .A(carrier_in[10]),
    .B(signal_in[13]),
    .Y(_0023_)
  );
  sky130_fd_sc_hd__nand2_1 _2253_ (
    .A(carrier_in[11]),
    .B(signal_in[12]),
    .Y(_0024_)
  );
  sky130_fd_sc_hd__nand2_1 _2254_ (
    .A(carrier_in[12]),
    .B(signal_in[12]),
    .Y(_0025_)
  );
  sky130_fd_sc_hd__nand2_1 _2255_ (
    .A(_1244_),
    .B(_0024_),
    .Y(_0026_)
  );
  sky130_fd_sc_hd__o21ai_0 _2256_ (
    .A1(_1243_),
    .A2(_0025_),
    .B1(_0026_),
    .Y(_0027_)
  );
  sky130_fd_sc_hd__xnor2_1 _2257_ (
    .A(_0023_),
    .B(_0027_),
    .Y(_0028_)
  );
  sky130_fd_sc_hd__maj3_1 _2258_ (
    .A(_1249_),
    .B(_1250_),
    .C(_1251_),
    .X(_0029_)
  );
  sky130_fd_sc_hd__nand2_1 _2259_ (
    .A(carrier_in[13]),
    .B(signal_in[10]),
    .Y(_0030_)
  );
  sky130_fd_sc_hd__nand2_1 _2260_ (
    .A(carrier_in[14]),
    .B(signal_in[9]),
    .Y(_0031_)
  );
  sky130_fd_sc_hd__nand2b_1 _2261_ (
    .A_N(signal_in[8]),
    .B(carrier_in[15]),
    .Y(_0032_)
  );
  sky130_fd_sc_hd__xor3_1 _2262_ (
    .A(_0030_),
    .B(_0031_),
    .C(_0032_),
    .X(_0034_)
  );
  sky130_fd_sc_hd__xnor2_1 _2263_ (
    .A(_0029_),
    .B(_0034_),
    .Y(_0035_)
  );
  sky130_fd_sc_hd__xor2_1 _2264_ (
    .A(_0028_),
    .B(_0035_),
    .X(_0036_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2265_ (
    .A(_0036_),
    .SLEEP(_0021_),
    .X(_0037_)
  );
  sky130_fd_sc_hd__xnor2_1 _2266_ (
    .A(_0021_),
    .B(_0036_),
    .Y(_0038_)
  );
  sky130_fd_sc_hd__and2_0 _2267_ (
    .A(_0020_),
    .B(_0038_),
    .X(_0039_)
  );
  sky130_fd_sc_hd__xnor2_1 _2268_ (
    .A(_0020_),
    .B(_0038_),
    .Y(_0040_)
  );
  sky130_fd_sc_hd__a21oi_1 _2269_ (
    .A1(_1256_),
    .A2(_1260_),
    .B1(_0040_),
    .Y(_0041_)
  );
  sky130_fd_sc_hd__clkinv_1 _2270_ (
    .A(_0041_),
    .Y(_0042_)
  );
  sky130_fd_sc_hd__and3_1 _2271_ (
    .A(_1256_),
    .B(_1260_),
    .C(_0040_),
    .X(_0043_)
  );
  sky130_fd_sc_hd__nor2_1 _2272_ (
    .A(_0041_),
    .B(_0043_),
    .Y(_0045_)
  );
  sky130_fd_sc_hd__or3_1 _2273_ (
    .A(_0010_),
    .B(_0041_),
    .C(_0043_),
    .X(_0046_)
  );
  sky130_fd_sc_hd__xnor2_1 _2274_ (
    .A(_0010_),
    .B(_0045_),
    .Y(_0047_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2275_ (
    .A(_0047_),
    .SLEEP(_0004_),
    .X(_0048_)
  );
  sky130_fd_sc_hd__xnor2_1 _2276_ (
    .A(_0004_),
    .B(_0047_),
    .Y(_0049_)
  );
  sky130_fd_sc_hd__xor2_1 _2277_ (
    .A(_0003_),
    .B(_0049_),
    .X(_0050_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2278_ (
    .A(_0050_),
    .SLEEP(_1278_),
    .X(_0051_)
  );
  sky130_fd_sc_hd__xnor2_1 _2279_ (
    .A(_1278_),
    .B(_0050_),
    .Y(_0052_)
  );
  sky130_fd_sc_hd__xor2_1 _2280_ (
    .A(_1219_),
    .B(_0052_),
    .X(_0053_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2281_ (
    .A(_0053_),
    .SLEEP(_1277_),
    .X(_0054_)
  );
  sky130_fd_sc_hd__nand2b_1 _2282_ (
    .A_N(_0053_),
    .B(_1277_),
    .Y(_0056_)
  );
  sky130_fd_sc_hd__nor2b_1 _2283_ (
    .A(_0054_),
    .B_N(_0056_),
    .Y(_0057_)
  );
  sky130_fd_sc_hd__xnor2_1 _2284_ (
    .A(_1276_),
    .B(_0057_),
    .Y(_1279_[23])
  );
  sky130_fd_sc_hd__o31ai_1 _2285_ (
    .A1(_1272_),
    .A2(_1274_),
    .A3(_0054_),
    .B1(_0056_),
    .Y(_0058_)
  );
  sky130_fd_sc_hd__a21oi_1 _2286_ (
    .A1(_1219_),
    .A2(_0052_),
    .B1(_0051_),
    .Y(_0059_)
  );
  sky130_fd_sc_hd__a21oi_1 _2287_ (
    .A1(_0003_),
    .A2(_0049_),
    .B1(_0048_),
    .Y(_0060_)
  );
  sky130_fd_sc_hd__a21oi_1 _2288_ (
    .A1(_0006_),
    .A2(_0009_),
    .B1(_0008_),
    .Y(_0061_)
  );
  sky130_fd_sc_hd__nor2_1 _2289_ (
    .A(_1011_),
    .B(_0061_),
    .Y(_0062_)
  );
  sky130_fd_sc_hd__xnor2_1 _2290_ (
    .A(_1012_),
    .B(_0061_),
    .Y(_0063_)
  );
  sky130_fd_sc_hd__maj3_1 _2291_ (
    .A(_0012_),
    .B(_0017_),
    .C(_0018_),
    .X(_0064_)
  );
  sky130_fd_sc_hd__nor2_1 _2292_ (
    .A(_1224_),
    .B(_0064_),
    .Y(_0066_)
  );
  sky130_fd_sc_hd__xor2_1 _2293_ (
    .A(_1224_),
    .B(_0064_),
    .X(_0067_)
  );
  sky130_fd_sc_hd__xnor2_1 _2294_ (
    .A(_0006_),
    .B(_0067_),
    .Y(_0068_)
  );
  sky130_fd_sc_hd__maj3_1 _2295_ (
    .A(_1232_),
    .B(_1234_),
    .C(_0013_),
    .X(_0069_)
  );
  sky130_fd_sc_hd__o21ai_0 _2296_ (
    .A1(carrier_in[9]),
    .A2(carrier_in[8]),
    .B1(signal_in[15]),
    .Y(_0070_)
  );
  sky130_fd_sc_hd__nor2_1 _2297_ (
    .A(_0014_),
    .B(_0070_),
    .Y(_0071_)
  );
  sky130_fd_sc_hd__xnor2_1 _2298_ (
    .A(_1232_),
    .B(_0071_),
    .Y(_0072_)
  );
  sky130_fd_sc_hd__xor2_1 _2299_ (
    .A(_1232_),
    .B(_0071_),
    .X(_0073_)
  );
  sky130_fd_sc_hd__maj3_1 _2300_ (
    .A(_1244_),
    .B(_0023_),
    .C(_0024_),
    .X(_0074_)
  );
  sky130_fd_sc_hd__xnor2_1 _2301_ (
    .A(_0072_),
    .B(_0074_),
    .Y(_0075_)
  );
  sky130_fd_sc_hd__xnor2_1 _2302_ (
    .A(_0069_),
    .B(_0075_),
    .Y(_0077_)
  );
  sky130_fd_sc_hd__maj3_1 _2303_ (
    .A(_0028_),
    .B(_0029_),
    .C(_0034_),
    .X(_0078_)
  );
  sky130_fd_sc_hd__nand2_1 _2304_ (
    .A(carrier_in[10]),
    .B(signal_in[14]),
    .Y(_0079_)
  );
  sky130_fd_sc_hd__nand2_1 _2305_ (
    .A(carrier_in[11]),
    .B(signal_in[13]),
    .Y(_0080_)
  );
  sky130_fd_sc_hd__nand2_1 _2306_ (
    .A(carrier_in[12]),
    .B(signal_in[13]),
    .Y(_0081_)
  );
  sky130_fd_sc_hd__xor2_1 _2307_ (
    .A(_0025_),
    .B(_0080_),
    .X(_0082_)
  );
  sky130_fd_sc_hd__xnor2_1 _2308_ (
    .A(_0079_),
    .B(_0082_),
    .Y(_0083_)
  );
  sky130_fd_sc_hd__maj3_1 _2309_ (
    .A(_0030_),
    .B(_0031_),
    .C(_0032_),
    .X(_0084_)
  );
  sky130_fd_sc_hd__nand2_1 _2310_ (
    .A(carrier_in[13]),
    .B(signal_in[11]),
    .Y(_0085_)
  );
  sky130_fd_sc_hd__nand2_1 _2311_ (
    .A(carrier_in[14]),
    .B(signal_in[10]),
    .Y(_0086_)
  );
  sky130_fd_sc_hd__nand2b_1 _2312_ (
    .A_N(signal_in[9]),
    .B(carrier_in[15]),
    .Y(_0088_)
  );
  sky130_fd_sc_hd__xor3_1 _2313_ (
    .A(_0085_),
    .B(_0086_),
    .C(_0088_),
    .X(_0089_)
  );
  sky130_fd_sc_hd__nor2_1 _2314_ (
    .A(_0084_),
    .B(_0089_),
    .Y(_0090_)
  );
  sky130_fd_sc_hd__xor2_1 _2315_ (
    .A(_0084_),
    .B(_0089_),
    .X(_0091_)
  );
  sky130_fd_sc_hd__xnor2_1 _2316_ (
    .A(_0083_),
    .B(_0091_),
    .Y(_0092_)
  );
  sky130_fd_sc_hd__lpflow_inputiso1p_1 _2317_ (
    .A(_0078_),
    .SLEEP(_0092_),
    .X(_0093_)
  );
  sky130_fd_sc_hd__xor2_1 _2318_ (
    .A(_0078_),
    .B(_0092_),
    .X(_0094_)
  );
  sky130_fd_sc_hd__nand2_1 _2319_ (
    .A(_0077_),
    .B(_0094_),
    .Y(_0095_)
  );
  sky130_fd_sc_hd__xor2_1 _2320_ (
    .A(_0077_),
    .B(_0094_),
    .X(_0096_)
  );
  sky130_fd_sc_hd__o21a_1 _2321_ (
    .A1(_0037_),
    .A2(_0039_),
    .B1(_0096_),
    .X(_0097_)
  );
  sky130_fd_sc_hd__nor3_1 _2322_ (
    .A(_0037_),
    .B(_0039_),
    .C(_0096_),
    .Y(_0099_)
  );
  sky130_fd_sc_hd__nor2_1 _2323_ (
    .A(_0097_),
    .B(_0099_),
    .Y(_0100_)
  );
  sky130_fd_sc_hd__nor3_1 _2324_ (
    .A(_0068_),
    .B(_0097_),
    .C(_0099_),
    .Y(_0101_)
  );
  sky130_fd_sc_hd__xor2_1 _2325_ (
    .A(_0068_),
    .B(_0100_),
    .X(_0102_)
  );
  sky130_fd_sc_hd__a21o_1 _2326_ (
    .A1(_0042_),
    .A2(_0046_),
    .B1(_0102_),
    .X(_0103_)
  );
  sky130_fd_sc_hd__nand3_1 _2327_ (
    .A(_0042_),
    .B(_0046_),
    .C(_0102_),
    .Y(_0104_)
  );
  sky130_fd_sc_hd__and2_0 _2328_ (
    .A(_0103_),
    .B(_0104_),
    .X(_0105_)
  );
  sky130_fd_sc_hd__nand2_1 _2329_ (
    .A(_0063_),
    .B(_0105_),
    .Y(_0106_)
  );
  sky130_fd_sc_hd__xor2_1 _2330_ (
    .A(_0063_),
    .B(_0105_),
    .X(_0107_)
  );
  sky130_fd_sc_hd__nand2b_1 _2331_ (
    .A_N(_0060_),
    .B(_0107_),
    .Y(_0108_)
  );
  sky130_fd_sc_hd__xnor2_1 _2332_ (
    .A(_0060_),
    .B(_0107_),
    .Y(_0110_)
  );
  sky130_fd_sc_hd__nand2_1 _2333_ (
    .A(_0002_),
    .B(_0110_),
    .Y(_0111_)
  );
  sky130_fd_sc_hd__xor2_1 _2334_ (
    .A(_0002_),
    .B(_0110_),
    .X(_0112_)
  );
  sky130_fd_sc_hd__nand2b_1 _2335_ (
    .A_N(_0059_),
    .B(_0112_),
    .Y(_0113_)
  );
  sky130_fd_sc_hd__xnor2_1 _2336_ (
    .A(_0059_),
    .B(_0112_),
    .Y(_0114_)
  );
  sky130_fd_sc_hd__o311ai_0 _2337_ (
    .A1(_1272_),
    .A2(_1274_),
    .A3(_0054_),
    .B1(_0056_),
    .C1(_0114_),
    .Y(_0115_)
  );
  sky130_fd_sc_hd__xnor2_1 _2338_ (
    .A(_0058_),
    .B(_0114_),
    .Y(_1279_[24])
  );
  sky130_fd_sc_hd__nand2_1 _2339_ (
    .A(_0113_),
    .B(_0115_),
    .Y(_0116_)
  );
  sky130_fd_sc_hd__a21oi_1 _2340_ (
    .A1(_0006_),
    .A2(_0067_),
    .B1(_0066_),
    .Y(_0117_)
  );
  sky130_fd_sc_hd__nor2_1 _2341_ (
    .A(_1011_),
    .B(_0117_),
    .Y(_0118_)
  );
  sky130_fd_sc_hd__xnor2_1 _2342_ (
    .A(_1012_),
    .B(_0117_),
    .Y(_0120_)
  );
  sky130_fd_sc_hd__maj3_1 _2343_ (
    .A(_0069_),
    .B(_0073_),
    .C(_0074_),
    .X(_0121_)
  );
  sky130_fd_sc_hd__xnor2_1 _2344_ (
    .A(_1224_),
    .B(_0121_),
    .Y(_0122_)
  );
  sky130_fd_sc_hd__xnor2_1 _2345_ (
    .A(_0005_),
    .B(_0122_),
    .Y(_0123_)
  );
  sky130_fd_sc_hd__o21bai_1 _2346_ (
    .A1(_1232_),
    .A2(_0070_),
    .B1_N(_0014_),
    .Y(_0124_)
  );
  sky130_fd_sc_hd__maj3_1 _2347_ (
    .A(_0025_),
    .B(_0079_),
    .C(_0080_),
    .X(_0125_)
  );
  sky130_fd_sc_hd__nor2_1 _2348_ (
    .A(_0073_),
    .B(_0125_),
    .Y(_0126_)
  );
  sky130_fd_sc_hd__xnor2_1 _2349_ (
    .A(_0072_),
    .B(_0125_),
    .Y(_0127_)
  );
  sky130_fd_sc_hd__xnor2_1 _2350_ (
    .A(_0124_),
    .B(_0127_),
    .Y(_0128_)
  );
  sky130_fd_sc_hd__a21oi_1 _2351_ (
    .A1(_0083_),
    .A2(_0091_),
    .B1(_0090_),
    .Y(_0129_)
  );
  sky130_fd_sc_hd__nand2_1 _2352_ (
    .A(carrier_in[10]),
    .B(signal_in[15]),
    .Y(_0131_)
  );
  sky130_fd_sc_hd__nand2_1 _2353_ (
    .A(carrier_in[11]),
    .B(signal_in[14]),
    .Y(_0132_)
  );
  sky130_fd_sc_hd__nand2_1 _2354_ (
    .A(carrier_in[12]),
    .B(signal_in[14]),
    .Y(_0133_)
  );
  sky130_fd_sc_hd__nand2_1 _2355_ (
    .A(_0081_),
    .B(_0132_),
    .Y(_0134_)
  );
  sky130_fd_sc_hd__o21ai_0 _2356_ (
    .A1(_0080_),
    .A2(_0133_),
    .B1(_0134_),
    .Y(_0135_)
  );
  sky130_fd_sc_hd__xnor2_1 _2357_ (
    .A(_0131_),
    .B(_0135_),
    .Y(_0136_)
  );
  sky130_fd_sc_hd__maj3_1 _2358_ (
    .A(_0085_),
    .B(_0086_),
    .C(_0088_),
    .X(_0137_)
  );
  sky130_fd_sc_hd__nand2_1 _2359_ (
    .A(carrier_in[13]),
    .B(signal_in[12]),
    .Y(_0138_)
  );
  sky130_fd_sc_hd__nand2_1 _2360_ (
    .A(carrier_in[14]),
    .B(signal_in[11]),
    .Y(_0139_)
  );
  sky130_fd_sc_hd__nor3_1 _2361_ (
    .A(signal_in[10]),
    .B(_0726_),
    .C(_0139_),
    .Y(_0140_)
  );
  sky130_fd_sc_hd__o21a_1 _2362_ (
    .A1(signal_in[10]),
    .A2(_0726_),
    .B1(_0139_),
    .X(_0142_)
  );
  sky130_fd_sc_hd__nor2_1 _2363_ (
    .A(_0140_),
    .B(_0142_),
    .Y(_0143_)
  );
  sky130_fd_sc_hd__nor3_1 _2364_ (
    .A(_0138_),
    .B(_0140_),
    .C(_0142_),
    .Y(_0144_)
  );
  sky130_fd_sc_hd__xor2_1 _2365_ (
    .A(_0138_),
    .B(_0143_),
    .X(_0145_)
  );
  sky130_fd_sc_hd__xnor3_1 _2366_ (
    .A(_0136_),
    .B(_0137_),
    .C(_0145_),
    .X(_0146_)
  );
  sky130_fd_sc_hd__clkinv_1 _2367_ (
    .A(_0146_),
    .Y(_0147_)
  );
  sky130_fd_sc_hd__xor2_1 _2368_ (
    .A(_0129_),
    .B(_0146_),
    .X(_0148_)
  );
  sky130_fd_sc_hd__xnor2_1 _2369_ (
    .A(_0128_),
    .B(_0148_),
    .Y(_0149_)
  );
  sky130_fd_sc_hd__and3_1 _2370_ (
    .A(_0093_),
    .B(_0095_),
    .C(_0149_),
    .X(_0150_)
  );
  sky130_fd_sc_hd__a21oi_1 _2371_ (
    .A1(_0093_),
    .A2(_0095_),
    .B1(_0149_),
    .Y(_0151_)
  );
  sky130_fd_sc_hd__nor2_1 _2372_ (
    .A(_0150_),
    .B(_0151_),
    .Y(_0153_)
  );
  sky130_fd_sc_hd__nor3_1 _2373_ (
    .A(_0123_),
    .B(_0150_),
    .C(_0151_),
    .Y(_0154_)
  );
  sky130_fd_sc_hd__xnor2_1 _2374_ (
    .A(_0123_),
    .B(_0153_),
    .Y(_0155_)
  );
  sky130_fd_sc_hd__o21a_1 _2375_ (
    .A1(_0097_),
    .A2(_0101_),
    .B1(_0155_),
    .X(_0156_)
  );
  sky130_fd_sc_hd__nor3_1 _2376_ (
    .A(_0097_),
    .B(_0101_),
    .C(_0155_),
    .Y(_0157_)
  );
  sky130_fd_sc_hd__nor2_1 _2377_ (
    .A(_0156_),
    .B(_0157_),
    .Y(_0158_)
  );
  sky130_fd_sc_hd__and2_0 _2378_ (
    .A(_0120_),
    .B(_0158_),
    .X(_0159_)
  );
  sky130_fd_sc_hd__xnor2_1 _2379_ (
    .A(_0120_),
    .B(_0158_),
    .Y(_0160_)
  );
  sky130_fd_sc_hd__a21oi_1 _2380_ (
    .A1(_0103_),
    .A2(_0106_),
    .B1(_0160_),
    .Y(_0161_)
  );
  sky130_fd_sc_hd__and3_1 _2381_ (
    .A(_0103_),
    .B(_0106_),
    .C(_0160_),
    .X(_0162_)
  );
  sky130_fd_sc_hd__nor2_1 _2382_ (
    .A(_0161_),
    .B(_0162_),
    .Y(_0164_)
  );
  sky130_fd_sc_hd__nor4_1 _2383_ (
    .A(_1011_),
    .B(_0061_),
    .C(_0161_),
    .D(_0162_),
    .Y(_0165_)
  );
  sky130_fd_sc_hd__xnor2_1 _2384_ (
    .A(_0062_),
    .B(_0164_),
    .Y(_0166_)
  );
  sky130_fd_sc_hd__a21oi_1 _2385_ (
    .A1(_0108_),
    .A2(_0111_),
    .B1(_0166_),
    .Y(_0167_)
  );
  sky130_fd_sc_hd__and3_1 _2386_ (
    .A(_0108_),
    .B(_0111_),
    .C(_0166_),
    .X(_0168_)
  );
  sky130_fd_sc_hd__nor2_1 _2387_ (
    .A(_0167_),
    .B(_0168_),
    .Y(_0169_)
  );
  sky130_fd_sc_hd__a21boi_0 _2388_ (
    .A1(_0113_),
    .A2(_0115_),
    .B1_N(_0169_),
    .Y(_0170_)
  );
  sky130_fd_sc_hd__xor2_1 _2389_ (
    .A(_0116_),
    .B(_0169_),
    .X(_1279_[25])
  );
  sky130_fd_sc_hd__maj3_1 _2390_ (
    .A(_1224_),
    .B(_0005_),
    .C(_0121_),
    .X(_0171_)
  );
  sky130_fd_sc_hd__nor2_1 _2391_ (
    .A(_1011_),
    .B(_0171_),
    .Y(_0172_)
  );
  sky130_fd_sc_hd__xnor2_1 _2392_ (
    .A(_1012_),
    .B(_0171_),
    .Y(_0174_)
  );
  sky130_fd_sc_hd__a21oi_1 _2393_ (
    .A1(_0124_),
    .A2(_0127_),
    .B1(_0126_),
    .Y(_0175_)
  );
  sky130_fd_sc_hd__xor2_1 _2394_ (
    .A(_1224_),
    .B(_0175_),
    .X(_0176_)
  );
  sky130_fd_sc_hd__xnor2_1 _2395_ (
    .A(_0006_),
    .B(_0176_),
    .Y(_0177_)
  );
  sky130_fd_sc_hd__maj3_1 _2396_ (
    .A(_0128_),
    .B(_0129_),
    .C(_0147_),
    .X(_0178_)
  );
  sky130_fd_sc_hd__maj3_1 _2397_ (
    .A(_0081_),
    .B(_0131_),
    .C(_0132_),
    .X(_0179_)
  );
  sky130_fd_sc_hd__nor2_1 _2398_ (
    .A(_0073_),
    .B(_0179_),
    .Y(_0180_)
  );
  sky130_fd_sc_hd__xnor2_1 _2399_ (
    .A(_0072_),
    .B(_0179_),
    .Y(_0181_)
  );
  sky130_fd_sc_hd__xnor2_1 _2400_ (
    .A(_0124_),
    .B(_0181_),
    .Y(_0182_)
  );
  sky130_fd_sc_hd__maj3_1 _2401_ (
    .A(_0136_),
    .B(_0137_),
    .C(_0145_),
    .X(_0183_)
  );
  sky130_fd_sc_hd__nand2_1 _2402_ (
    .A(carrier_in[11]),
    .B(signal_in[15]),
    .Y(_0185_)
  );
  sky130_fd_sc_hd__and3_1 _2403_ (
    .A(carrier_in[12]),
    .B(carrier_in[11]),
    .C(signal_in[15]),
    .X(_0186_)
  );
  sky130_fd_sc_hd__xor2_1 _2404_ (
    .A(_0133_),
    .B(_0185_),
    .X(_0187_)
  );
  sky130_fd_sc_hd__xnor2_1 _2405_ (
    .A(_0131_),
    .B(_0187_),
    .Y(_0188_)
  );
  sky130_fd_sc_hd__nand2_1 _2406_ (
    .A(carrier_in[13]),
    .B(signal_in[13]),
    .Y(_0189_)
  );
  sky130_fd_sc_hd__nand2_1 _2407_ (
    .A(carrier_in[14]),
    .B(signal_in[12]),
    .Y(_0190_)
  );
  sky130_fd_sc_hd__nand2b_1 _2408_ (
    .A_N(signal_in[11]),
    .B(carrier_in[15]),
    .Y(_0191_)
  );
  sky130_fd_sc_hd__xnor3_1 _2409_ (
    .A(_0189_),
    .B(_0190_),
    .C(_0191_),
    .X(_0192_)
  );
  sky130_fd_sc_hd__nor3_1 _2410_ (
    .A(_0140_),
    .B(_0144_),
    .C(_0192_),
    .Y(_0193_)
  );
  sky130_fd_sc_hd__o21a_1 _2411_ (
    .A1(_0140_),
    .A2(_0144_),
    .B1(_0192_),
    .X(_0194_)
  );
  sky130_fd_sc_hd__nor2_1 _2412_ (
    .A(_0193_),
    .B(_0194_),
    .Y(_0196_)
  );
  sky130_fd_sc_hd__xor2_1 _2413_ (
    .A(_0188_),
    .B(_0196_),
    .X(_0197_)
  );
  sky130_fd_sc_hd__clkinv_1 _2414_ (
    .A(_0197_),
    .Y(_0198_)
  );
  sky130_fd_sc_hd__xnor2_1 _2415_ (
    .A(_0183_),
    .B(_0197_),
    .Y(_0199_)
  );
  sky130_fd_sc_hd__xor2_1 _2416_ (
    .A(_0182_),
    .B(_0199_),
    .X(_0200_)
  );
  sky130_fd_sc_hd__xor2_1 _2417_ (
    .A(_0178_),
    .B(_0200_),
    .X(_0201_)
  );
  sky130_fd_sc_hd__xnor2_1 _2418_ (
    .A(_0177_),
    .B(_0201_),
    .Y(_0202_)
  );
  sky130_fd_sc_hd__nor3_1 _2419_ (
    .A(_0151_),
    .B(_0154_),
    .C(_0202_),
    .Y(_0203_)
  );
  sky130_fd_sc_hd__o21ai_0 _2420_ (
    .A1(_0151_),
    .A2(_0154_),
    .B1(_0202_),
    .Y(_0204_)
  );
  sky130_fd_sc_hd__nor2b_1 _2421_ (
    .A(_0203_),
    .B_N(_0204_),
    .Y(_0205_)
  );
  sky130_fd_sc_hd__nand2_1 _2422_ (
    .A(_0174_),
    .B(_0205_),
    .Y(_0207_)
  );
  sky130_fd_sc_hd__xor2_1 _2423_ (
    .A(_0174_),
    .B(_0205_),
    .X(_0208_)
  );
  sky130_fd_sc_hd__o21ai_0 _2424_ (
    .A1(_0156_),
    .A2(_0159_),
    .B1(_0208_),
    .Y(_0209_)
  );
  sky130_fd_sc_hd__nor3_1 _2425_ (
    .A(_0156_),
    .B(_0159_),
    .C(_0208_),
    .Y(_0210_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2426_ (
    .A(_0209_),
    .SLEEP(_0210_),
    .X(_0211_)
  );
  sky130_fd_sc_hd__nand2_1 _2427_ (
    .A(_0118_),
    .B(_0211_),
    .Y(_0212_)
  );
  sky130_fd_sc_hd__xor2_1 _2428_ (
    .A(_0118_),
    .B(_0211_),
    .X(_0213_)
  );
  sky130_fd_sc_hd__nor3_1 _2429_ (
    .A(_0161_),
    .B(_0165_),
    .C(_0213_),
    .Y(_0214_)
  );
  sky130_fd_sc_hd__o21ai_0 _2430_ (
    .A1(_0161_),
    .A2(_0165_),
    .B1(_0213_),
    .Y(_0215_)
  );
  sky130_fd_sc_hd__nor2b_1 _2431_ (
    .A(_0214_),
    .B_N(_0215_),
    .Y(_0216_)
  );
  sky130_fd_sc_hd__o21ai_0 _2432_ (
    .A1(_0167_),
    .A2(_0170_),
    .B1(_0216_),
    .Y(_0218_)
  );
  sky130_fd_sc_hd__nor3_1 _2433_ (
    .A(_0167_),
    .B(_0170_),
    .C(_0216_),
    .Y(_0219_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2434_ (
    .A(_0218_),
    .SLEEP(_0219_),
    .X(_1279_[26])
  );
  sky130_fd_sc_hd__nand2_1 _2435_ (
    .A(_0209_),
    .B(_0212_),
    .Y(_0220_)
  );
  sky130_fd_sc_hd__maj3_1 _2436_ (
    .A(_1224_),
    .B(_0005_),
    .C(_0175_),
    .X(_0221_)
  );
  sky130_fd_sc_hd__nor2_1 _2437_ (
    .A(_1011_),
    .B(_0221_),
    .Y(_0222_)
  );
  sky130_fd_sc_hd__xnor2_1 _2438_ (
    .A(_1012_),
    .B(_0221_),
    .Y(_0223_)
  );
  sky130_fd_sc_hd__maj3_1 _2439_ (
    .A(_0177_),
    .B(_0178_),
    .C(_0200_),
    .X(_0224_)
  );
  sky130_fd_sc_hd__a21oi_1 _2440_ (
    .A1(_0124_),
    .A2(_0181_),
    .B1(_0180_),
    .Y(_0225_)
  );
  sky130_fd_sc_hd__xor2_1 _2441_ (
    .A(_1224_),
    .B(_0225_),
    .X(_0226_)
  );
  sky130_fd_sc_hd__xnor2_1 _2442_ (
    .A(_0006_),
    .B(_0226_),
    .Y(_0228_)
  );
  sky130_fd_sc_hd__maj3_1 _2443_ (
    .A(_0182_),
    .B(_0183_),
    .C(_0198_),
    .X(_0229_)
  );
  sky130_fd_sc_hd__maj3_1 _2444_ (
    .A(_0131_),
    .B(_0133_),
    .C(_0185_),
    .X(_0230_)
  );
  sky130_fd_sc_hd__nor2_1 _2445_ (
    .A(_0073_),
    .B(_0230_),
    .Y(_0231_)
  );
  sky130_fd_sc_hd__xnor2_1 _2446_ (
    .A(_0072_),
    .B(_0230_),
    .Y(_0232_)
  );
  sky130_fd_sc_hd__xnor2_1 _2447_ (
    .A(_0124_),
    .B(_0232_),
    .Y(_0233_)
  );
  sky130_fd_sc_hd__clkinv_1 _2448_ (
    .A(_0233_),
    .Y(_0234_)
  );
  sky130_fd_sc_hd__a21oi_1 _2449_ (
    .A1(_0188_),
    .A2(_0196_),
    .B1(_0194_),
    .Y(_0235_)
  );
  sky130_fd_sc_hd__o21ai_0 _2450_ (
    .A1(carrier_in[12]),
    .A2(carrier_in[11]),
    .B1(signal_in[15]),
    .Y(_0236_)
  );
  sky130_fd_sc_hd__nor2_1 _2451_ (
    .A(_0186_),
    .B(_0236_),
    .Y(_0237_)
  );
  sky130_fd_sc_hd__xnor2_1 _2452_ (
    .A(_0131_),
    .B(_0237_),
    .Y(_0239_)
  );
  sky130_fd_sc_hd__maj3_1 _2453_ (
    .A(_0189_),
    .B(_0190_),
    .C(_0191_),
    .X(_0240_)
  );
  sky130_fd_sc_hd__nand2_1 _2454_ (
    .A(carrier_in[13]),
    .B(signal_in[14]),
    .Y(_0241_)
  );
  sky130_fd_sc_hd__nand2_1 _2455_ (
    .A(carrier_in[14]),
    .B(signal_in[13]),
    .Y(_0242_)
  );
  sky130_fd_sc_hd__nor3_1 _2456_ (
    .A(signal_in[12]),
    .B(_0726_),
    .C(_0242_),
    .Y(_0243_)
  );
  sky130_fd_sc_hd__o21a_1 _2457_ (
    .A1(signal_in[12]),
    .A2(_0726_),
    .B1(_0242_),
    .X(_0244_)
  );
  sky130_fd_sc_hd__nor2_1 _2458_ (
    .A(_0243_),
    .B(_0244_),
    .Y(_0245_)
  );
  sky130_fd_sc_hd__nor3_1 _2459_ (
    .A(_0241_),
    .B(_0243_),
    .C(_0244_),
    .Y(_0246_)
  );
  sky130_fd_sc_hd__xor2_1 _2460_ (
    .A(_0241_),
    .B(_0245_),
    .X(_0247_)
  );
  sky130_fd_sc_hd__nor2_1 _2461_ (
    .A(_0240_),
    .B(_0247_),
    .Y(_0248_)
  );
  sky130_fd_sc_hd__xor2_1 _2462_ (
    .A(_0240_),
    .B(_0247_),
    .X(_0250_)
  );
  sky130_fd_sc_hd__xnor2_1 _2463_ (
    .A(_0239_),
    .B(_0250_),
    .Y(_0251_)
  );
  sky130_fd_sc_hd__xor2_1 _2464_ (
    .A(_0235_),
    .B(_0251_),
    .X(_0252_)
  );
  sky130_fd_sc_hd__nand2_1 _2465_ (
    .A(_0234_),
    .B(_0252_),
    .Y(_0253_)
  );
  sky130_fd_sc_hd__xnor2_1 _2466_ (
    .A(_0234_),
    .B(_0252_),
    .Y(_0254_)
  );
  sky130_fd_sc_hd__nor2_1 _2467_ (
    .A(_0229_),
    .B(_0254_),
    .Y(_0255_)
  );
  sky130_fd_sc_hd__xor2_1 _2468_ (
    .A(_0229_),
    .B(_0254_),
    .X(_0256_)
  );
  sky130_fd_sc_hd__nor2b_1 _2469_ (
    .A(_0228_),
    .B_N(_0256_),
    .Y(_0257_)
  );
  sky130_fd_sc_hd__xnor2_1 _2470_ (
    .A(_0228_),
    .B(_0256_),
    .Y(_0258_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2471_ (
    .A(_0258_),
    .SLEEP(_0224_),
    .X(_0259_)
  );
  sky130_fd_sc_hd__xnor2_1 _2472_ (
    .A(_0224_),
    .B(_0258_),
    .Y(_0261_)
  );
  sky130_fd_sc_hd__xnor2_1 _2473_ (
    .A(_0223_),
    .B(_0261_),
    .Y(_0262_)
  );
  sky130_fd_sc_hd__and3_1 _2474_ (
    .A(_0204_),
    .B(_0207_),
    .C(_0262_),
    .X(_0263_)
  );
  sky130_fd_sc_hd__a21oi_1 _2475_ (
    .A1(_0204_),
    .A2(_0207_),
    .B1(_0262_),
    .Y(_0264_)
  );
  sky130_fd_sc_hd__nor2_1 _2476_ (
    .A(_0263_),
    .B(_0264_),
    .Y(_0265_)
  );
  sky130_fd_sc_hd__nor2_1 _2477_ (
    .A(_0172_),
    .B(_0265_),
    .Y(_0266_)
  );
  sky130_fd_sc_hd__and2_0 _2478_ (
    .A(_0172_),
    .B(_0265_),
    .X(_0267_)
  );
  sky130_fd_sc_hd__nor2_1 _2479_ (
    .A(_0266_),
    .B(_0267_),
    .Y(_0268_)
  );
  sky130_fd_sc_hd__and2_0 _2480_ (
    .A(_0220_),
    .B(_0268_),
    .X(_0269_)
  );
  sky130_fd_sc_hd__xnor2_1 _2481_ (
    .A(_0220_),
    .B(_0268_),
    .Y(_0270_)
  );
  sky130_fd_sc_hd__a21oi_1 _2482_ (
    .A1(_0215_),
    .A2(_0218_),
    .B1(_0270_),
    .Y(_0272_)
  );
  sky130_fd_sc_hd__and3_1 _2483_ (
    .A(_0215_),
    .B(_0218_),
    .C(_0270_),
    .X(_0273_)
  );
  sky130_fd_sc_hd__nor2_1 _2484_ (
    .A(_0272_),
    .B(_0273_),
    .Y(_1279_[27])
  );
  sky130_fd_sc_hd__a21o_1 _2485_ (
    .A1(_0223_),
    .A2(_0261_),
    .B1(_0259_),
    .X(_0274_)
  );
  sky130_fd_sc_hd__maj3_1 _2486_ (
    .A(_1224_),
    .B(_0005_),
    .C(_0225_),
    .X(_0275_)
  );
  sky130_fd_sc_hd__nor2_1 _2487_ (
    .A(_1011_),
    .B(_0275_),
    .Y(_0276_)
  );
  sky130_fd_sc_hd__xnor2_1 _2488_ (
    .A(_1012_),
    .B(_0275_),
    .Y(_0277_)
  );
  sky130_fd_sc_hd__a21oi_1 _2489_ (
    .A1(_0124_),
    .A2(_0232_),
    .B1(_0231_),
    .Y(_0278_)
  );
  sky130_fd_sc_hd__xor2_1 _2490_ (
    .A(_1224_),
    .B(_0278_),
    .X(_0279_)
  );
  sky130_fd_sc_hd__xnor2_1 _2491_ (
    .A(_0006_),
    .B(_0279_),
    .Y(_0280_)
  );
  sky130_fd_sc_hd__o21ai_0 _2492_ (
    .A1(_0235_),
    .A2(_0251_),
    .B1(_0253_),
    .Y(_0282_)
  );
  sky130_fd_sc_hd__o21bai_1 _2493_ (
    .A1(_0131_),
    .A2(_0236_),
    .B1_N(_0186_),
    .Y(_0283_)
  );
  sky130_fd_sc_hd__xnor2_1 _2494_ (
    .A(_0073_),
    .B(_0283_),
    .Y(_0284_)
  );
  sky130_fd_sc_hd__xnor2_1 _2495_ (
    .A(_0124_),
    .B(_0284_),
    .Y(_0285_)
  );
  sky130_fd_sc_hd__a21oi_1 _2496_ (
    .A1(_0239_),
    .A2(_0250_),
    .B1(_0248_),
    .Y(_0286_)
  );
  sky130_fd_sc_hd__nand2_1 _2497_ (
    .A(carrier_in[13]),
    .B(signal_in[15]),
    .Y(_0287_)
  );
  sky130_fd_sc_hd__nand2_1 _2498_ (
    .A(carrier_in[14]),
    .B(signal_in[14]),
    .Y(_0288_)
  );
  sky130_fd_sc_hd__nand2b_1 _2499_ (
    .A_N(signal_in[13]),
    .B(carrier_in[15]),
    .Y(_0289_)
  );
  sky130_fd_sc_hd__xnor2_1 _2500_ (
    .A(_0288_),
    .B(_0289_),
    .Y(_0290_)
  );
  sky130_fd_sc_hd__xor2_1 _2501_ (
    .A(_0287_),
    .B(_0290_),
    .X(_0291_)
  );
  sky130_fd_sc_hd__nor3_1 _2502_ (
    .A(_0243_),
    .B(_0246_),
    .C(_0291_),
    .Y(_0293_)
  );
  sky130_fd_sc_hd__o21ai_0 _2503_ (
    .A1(_0243_),
    .A2(_0246_),
    .B1(_0291_),
    .Y(_0294_)
  );
  sky130_fd_sc_hd__nor2b_1 _2504_ (
    .A(_0293_),
    .B_N(_0294_),
    .Y(_0295_)
  );
  sky130_fd_sc_hd__nand2_1 _2505_ (
    .A(_0239_),
    .B(_0295_),
    .Y(_0296_)
  );
  sky130_fd_sc_hd__xnor2_1 _2506_ (
    .A(_0239_),
    .B(_0295_),
    .Y(_0297_)
  );
  sky130_fd_sc_hd__nor2_1 _2507_ (
    .A(_0286_),
    .B(_0297_),
    .Y(_0298_)
  );
  sky130_fd_sc_hd__xor2_1 _2508_ (
    .A(_0286_),
    .B(_0297_),
    .X(_0299_)
  );
  sky130_fd_sc_hd__nor2b_1 _2509_ (
    .A(_0285_),
    .B_N(_0299_),
    .Y(_0300_)
  );
  sky130_fd_sc_hd__xnor2_1 _2510_ (
    .A(_0285_),
    .B(_0299_),
    .Y(_0301_)
  );
  sky130_fd_sc_hd__nand2_1 _2511_ (
    .A(_0282_),
    .B(_0301_),
    .Y(_0302_)
  );
  sky130_fd_sc_hd__xnor2_1 _2512_ (
    .A(_0282_),
    .B(_0301_),
    .Y(_0304_)
  );
  sky130_fd_sc_hd__xor2_1 _2513_ (
    .A(_0280_),
    .B(_0304_),
    .X(_0305_)
  );
  sky130_fd_sc_hd__nor3_1 _2514_ (
    .A(_0255_),
    .B(_0257_),
    .C(_0305_),
    .Y(_0306_)
  );
  sky130_fd_sc_hd__o21ai_0 _2515_ (
    .A1(_0255_),
    .A2(_0257_),
    .B1(_0305_),
    .Y(_0307_)
  );
  sky130_fd_sc_hd__nor2b_1 _2516_ (
    .A(_0306_),
    .B_N(_0307_),
    .Y(_0308_)
  );
  sky130_fd_sc_hd__nand2_1 _2517_ (
    .A(_0277_),
    .B(_0308_),
    .Y(_0309_)
  );
  sky130_fd_sc_hd__xor2_1 _2518_ (
    .A(_0277_),
    .B(_0308_),
    .X(_0310_)
  );
  sky130_fd_sc_hd__xnor2_1 _2519_ (
    .A(_0274_),
    .B(_0310_),
    .Y(_0311_)
  );
  sky130_fd_sc_hd__xnor2_1 _2520_ (
    .A(_0222_),
    .B(_0311_),
    .Y(_0312_)
  );
  sky130_fd_sc_hd__nor3_1 _2521_ (
    .A(_0264_),
    .B(_0267_),
    .C(_0312_),
    .Y(_0313_)
  );
  sky130_fd_sc_hd__o21ai_0 _2522_ (
    .A1(_0264_),
    .A2(_0267_),
    .B1(_0312_),
    .Y(_0315_)
  );
  sky130_fd_sc_hd__nor2b_1 _2523_ (
    .A(_0313_),
    .B_N(_0315_),
    .Y(_0316_)
  );
  sky130_fd_sc_hd__o21ai_0 _2524_ (
    .A1(_0269_),
    .A2(_0272_),
    .B1(_0316_),
    .Y(_0317_)
  );
  sky130_fd_sc_hd__nor3_1 _2525_ (
    .A(_0269_),
    .B(_0272_),
    .C(_0316_),
    .Y(_0318_)
  );
  sky130_fd_sc_hd__lpflow_isobufsrc_1 _2526_ (
    .A(_0317_),
    .SLEEP(_0318_),
    .X(_1279_[28])
  );
  sky130_fd_sc_hd__nand2_1 _2527_ (
    .A(_0315_),
    .B(_0317_),
    .Y(_0319_)
  );
  sky130_fd_sc_hd__maj3_1 _2528_ (
    .A(_0222_),
    .B(_0274_),
    .C(_0310_),
    .X(_0320_)
  );
  sky130_fd_sc_hd__nand2_1 _2529_ (
    .A(_0307_),
    .B(_0309_),
    .Y(_0321_)
  );
  sky130_fd_sc_hd__maj3_1 _2530_ (
    .A(_1224_),
    .B(_0005_),
    .C(_0278_),
    .X(_0322_)
  );
  sky130_fd_sc_hd__xnor2_1 _2531_ (
    .A(_1012_),
    .B(_0322_),
    .Y(_0323_)
  );
  sky130_fd_sc_hd__o21ai_0 _2532_ (
    .A1(_0280_),
    .A2(_0304_),
    .B1(_0302_),
    .Y(_0325_)
  );
  sky130_fd_sc_hd__maj3_1 _2533_ (
    .A(_0072_),
    .B(_0124_),
    .C(_0283_),
    .X(_0326_)
  );
  sky130_fd_sc_hd__xnor2_1 _2534_ (
    .A(_1224_),
    .B(_0326_),
    .Y(_0327_)
  );
  sky130_fd_sc_hd__xnor2_1 _2535_ (
    .A(_0006_),
    .B(_0327_),
    .Y(_0328_)
  );
  sky130_fd_sc_hd__maj3_1 _2536_ (
    .A(_0287_),
    .B(_0288_),
    .C(_0289_),
    .X(_0329_)
  );
  sky130_fd_sc_hd__clkinv_1 _2537_ (
    .A(_0329_),
    .Y(_0330_)
  );
  sky130_fd_sc_hd__nand2_1 _2538_ (
    .A(carrier_in[14]),
    .B(signal_in[15]),
    .Y(_0331_)
  );
  sky130_fd_sc_hd__nand2b_1 _2539_ (
    .A_N(signal_in[14]),
    .B(carrier_in[15]),
    .Y(_0332_)
  );
  sky130_fd_sc_hd__xnor2_1 _2540_ (
    .A(_0331_),
    .B(_0332_),
    .Y(_0333_)
  );
  sky130_fd_sc_hd__xor2_1 _2541_ (
    .A(_0287_),
    .B(_0333_),
    .X(_0334_)
  );
  sky130_fd_sc_hd__xnor2_1 _2542_ (
    .A(_0329_),
    .B(_0334_),
    .Y(_0336_)
  );
  sky130_fd_sc_hd__xnor2_1 _2543_ (
    .A(_0239_),
    .B(_0336_),
    .Y(_0337_)
  );
  sky130_fd_sc_hd__and3_1 _2544_ (
    .A(_0294_),
    .B(_0296_),
    .C(_0337_),
    .X(_0338_)
  );
  sky130_fd_sc_hd__a21oi_1 _2545_ (
    .A1(_0294_),
    .A2(_0296_),
    .B1(_0337_),
    .Y(_0339_)
  );
  sky130_fd_sc_hd__nor2_1 _2546_ (
    .A(_0338_),
    .B(_0339_),
    .Y(_0340_)
  );
  sky130_fd_sc_hd__xnor2_1 _2547_ (
    .A(_0285_),
    .B(_0340_),
    .Y(_0341_)
  );
  sky130_fd_sc_hd__or3_1 _2548_ (
    .A(_0298_),
    .B(_0300_),
    .C(_0341_),
    .X(_0342_)
  );
  sky130_fd_sc_hd__o21ai_0 _2549_ (
    .A1(_0298_),
    .A2(_0300_),
    .B1(_0341_),
    .Y(_0343_)
  );
  sky130_fd_sc_hd__and2_0 _2550_ (
    .A(_0342_),
    .B(_0343_),
    .X(_0344_)
  );
  sky130_fd_sc_hd__xnor2_1 _2551_ (
    .A(_0328_),
    .B(_0344_),
    .Y(_0345_)
  );
  sky130_fd_sc_hd__xor3_1 _2552_ (
    .A(_0323_),
    .B(_0325_),
    .C(_0345_),
    .X(_0347_)
  );
  sky130_fd_sc_hd__xor3_1 _2553_ (
    .A(_0276_),
    .B(_0321_),
    .C(_0347_),
    .X(_0348_)
  );
  sky130_fd_sc_hd__xnor2_1 _2554_ (
    .A(_0320_),
    .B(_0348_),
    .Y(_0349_)
  );
  sky130_fd_sc_hd__xnor2_1 _2555_ (
    .A(_0319_),
    .B(_0349_),
    .Y(_1279_[29])
  );
  sky130_fd_sc_hd__maj3_1 _2556_ (
    .A(_0319_),
    .B(_0320_),
    .C(_0348_),
    .X(_0350_)
  );
  sky130_fd_sc_hd__maj3_1 _2557_ (
    .A(_0276_),
    .B(_0321_),
    .C(_0347_),
    .X(_0351_)
  );
  sky130_fd_sc_hd__maj3_1 _2558_ (
    .A(_0323_),
    .B(_0325_),
    .C(_0345_),
    .X(_0352_)
  );
  sky130_fd_sc_hd__mux2i_1 _2559_ (
    .A0(_0342_),
    .A1(_0343_),
    .S(_0328_),
    .Y(_0353_)
  );
  sky130_fd_sc_hd__maj3_1 _2560_ (
    .A(_0239_),
    .B(_0330_),
    .C(_0334_),
    .X(_0354_)
  );
  sky130_fd_sc_hd__o211ai_1 _2561_ (
    .A1(signal_in[15]),
    .A2(_0726_),
    .B1(_0287_),
    .C1(_0331_),
    .Y(_0355_)
  );
  sky130_fd_sc_hd__maj3_1 _2562_ (
    .A(_0287_),
    .B(_0331_),
    .C(_0332_),
    .X(_0357_)
  );
  sky130_fd_sc_hd__a32oi_1 _2563_ (
    .A1(carrier_in[14]),
    .A2(carrier_in[13]),
    .A3(signal_in[15]),
    .B1(_0355_),
    .B2(_0357_),
    .Y(_0358_)
  );
  sky130_fd_sc_hd__xnor2_1 _2564_ (
    .A(_0239_),
    .B(_0358_),
    .Y(_0359_)
  );
  sky130_fd_sc_hd__xnor2_1 _2565_ (
    .A(_0354_),
    .B(_0359_),
    .Y(_0360_)
  );
  sky130_fd_sc_hd__mux2i_1 _2566_ (
    .A0(_0338_),
    .A1(_0339_),
    .S(_0285_),
    .Y(_0361_)
  );
  sky130_fd_sc_hd__xnor2_1 _2567_ (
    .A(_0360_),
    .B(_0361_),
    .Y(_0362_)
  );
  sky130_fd_sc_hd__xnor2_1 _2568_ (
    .A(_0353_),
    .B(_0362_),
    .Y(_0363_)
  );
  sky130_fd_sc_hd__maj3_1 _2569_ (
    .A(_1226_),
    .B(_0006_),
    .C(_0326_),
    .X(_0364_)
  );
  sky130_fd_sc_hd__xnor2_1 _2570_ (
    .A(_1012_),
    .B(_0364_),
    .Y(_0365_)
  );
  sky130_fd_sc_hd__o21ai_0 _2571_ (
    .A1(_1011_),
    .A2(_0322_),
    .B1(_0365_),
    .Y(_0366_)
  );
  sky130_fd_sc_hd__xnor2_1 _2572_ (
    .A(_0363_),
    .B(_0366_),
    .Y(_0368_)
  );
  sky130_fd_sc_hd__xnor2_1 _2573_ (
    .A(_0352_),
    .B(_0368_),
    .Y(_0369_)
  );
  sky130_fd_sc_hd__xnor2_1 _2574_ (
    .A(_0351_),
    .B(_0369_),
    .Y(_0370_)
  );
  sky130_fd_sc_hd__xnor2_1 _2575_ (
    .A(_0350_),
    .B(_0370_),
    .Y(_1279_[30])
  );
  sky130_fd_sc_hd__dfrtp_1 _2576_ (
    .CLK(clk),
    .D(product[15]),
    .Q(mod_out[0]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2577_ (
    .CLK(clk),
    .D(product[16]),
    .Q(mod_out[1]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2578_ (
    .CLK(clk),
    .D(product[17]),
    .Q(mod_out[2]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2579_ (
    .CLK(clk),
    .D(product[18]),
    .Q(mod_out[3]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2580_ (
    .CLK(clk),
    .D(product[19]),
    .Q(mod_out[4]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2581_ (
    .CLK(clk),
    .D(product[20]),
    .Q(mod_out[5]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2582_ (
    .CLK(clk),
    .D(product[21]),
    .Q(mod_out[6]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2583_ (
    .CLK(clk),
    .D(product[22]),
    .Q(mod_out[7]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2584_ (
    .CLK(clk),
    .D(product[23]),
    .Q(mod_out[8]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2585_ (
    .CLK(clk),
    .D(_1280_[24]),
    .Q(mod_out[9]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2586_ (
    .CLK(clk),
    .D(_1280_[25]),
    .Q(mod_out[10]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2587_ (
    .CLK(clk),
    .D(_1280_[26]),
    .Q(mod_out[11]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2588_ (
    .CLK(clk),
    .D(_1280_[27]),
    .Q(mod_out[12]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2589_ (
    .CLK(clk),
    .D(_1280_[28]),
    .Q(mod_out[13]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2590_ (
    .CLK(clk),
    .D(_1280_[29]),
    .Q(mod_out[14]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2591_ (
    .CLK(clk),
    .D(_1280_[30]),
    .Q(mod_out[15]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2592_ (
    .CLK(clk),
    .D(_1279_[15]),
    .Q(product[15]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2593_ (
    .CLK(clk),
    .D(_1279_[16]),
    .Q(product[16]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2594_ (
    .CLK(clk),
    .D(_1279_[17]),
    .Q(product[17]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2595_ (
    .CLK(clk),
    .D(_1279_[18]),
    .Q(product[18]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2596_ (
    .CLK(clk),
    .D(_1279_[19]),
    .Q(product[19]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2597_ (
    .CLK(clk),
    .D(_1279_[20]),
    .Q(product[20]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2598_ (
    .CLK(clk),
    .D(_1279_[21]),
    .Q(product[21]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2599_ (
    .CLK(clk),
    .D(_1279_[22]),
    .Q(product[22]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2600_ (
    .CLK(clk),
    .D(_1279_[23]),
    .Q(product[23]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2601_ (
    .CLK(clk),
    .D(_1279_[24]),
    .Q(_1280_[24]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2602_ (
    .CLK(clk),
    .D(_1279_[25]),
    .Q(_1280_[25]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2603_ (
    .CLK(clk),
    .D(_1279_[26]),
    .Q(_1280_[26]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2604_ (
    .CLK(clk),
    .D(_1279_[27]),
    .Q(_1280_[27]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2605_ (
    .CLK(clk),
    .D(_1279_[28]),
    .Q(_1280_[28]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2606_ (
    .CLK(clk),
    .D(_1279_[29]),
    .Q(_1280_[29]),
    .RESET_B(rst_n)
  );
  sky130_fd_sc_hd__dfrtp_1 _2607_ (
    .CLK(clk),
    .D(_1279_[30]),
    .Q(_1280_[30]),
    .RESET_B(rst_n)
  );
  assign _1280_[23:0] = product;
endmodule

When Yosys synthesizes the circuit, it converts the high-level hardware description into a gate-level netlist, which is a network of logic elements such as AND, XOR, NAND gates and flip-flops. Instead of looking at the original code, the design can now be visualized as a graph of interconnected logic blocks.

In the case of the ring modulator, the inputs carrier_in and signal_in are processed through a network of logic operations and registers that eventually produce the output mod_out. This representation helps to understand how the algorithm described in Verilog is implemented using real digital components.

Within Yosys, the gate-level schema can be exported using Graphviz:

yosys

read_verilog ring_modulator.v
synth -top ring_modulator
show

This generates a window or a .dot file that can be converted into an image.

show -format png -prefix ring_modulator

Gate-level schematic generated by Yosys after synthesizing the Verilog RTL into standard logic cells.

Run place and route flow

The next step is to run the place and route flow. After generating the synthesized netlist with Yosys, I move on to the physical implementation stage, where the design is turned from a logical gate-level netlist into a real physical layout. As Andreas explained in the class, after synthesis I already have a mapped netlist made of Sky130 standard cells, but those cells still do not have physical positions on the chip. During place and route, the tool places the standard cells into rows, builds the power structure, and routes the interconnections between them. The result is a physical implementation that I can later analyze for timing and area, and finally export as GDS.

As Andreas explained in the class, the place and route flow is usually divided into several stages: floorplanning, placement, clock tree synthesis, and routing. First, I define the physical region and the basic layout constraints. Then the cells are placed in legal positions, after which the clock network is built so that the clock reaches all flip-flops with controlled skew. Finally, the signal wires are routed to connect the entire design. Once this is done, I can inspect the reports and continue with static timing analysis to see whether my ring modulator meets timing.

For my ring modulator, this means that the netlist I generated with Yosys becomes the input to the P&R tool, together with the standard-cell library and the timing constraints file (SDC). In practice, I need to make sure I have at least the synthesized Verilog netlist, the Sky130 liberty and LEF files, and a simple constraints file defining the clock, for example a 20 ns period if I want to start with a 50 MHz target. As Andreas also pointed out, these constraints are important because they guide both optimization and clock tree generation.

So, the practical sequence I follow is: first I keep the synthesized netlist from Yosys, then I prepare the SDC file, and after that I launch the physical flow in OpenROAD. Once that finishes, I check whether the design was placed and routed correctly, look at the resulting reports, and use the generated layout files for the next step of the assignment. If you want, the next thing I can write is the exact English text for your documentation explaining how I prepared the SDC and ran OpenROAD.

OpenROAD

OpenROAD is an open-source digital design tool used to convert a Verilog RTL design into a real physical chip layout. It covers the main steps of the RTL-to-GDSII flow, including floorplanning, placement, clock tree synthesis, routing, and optimization. In this way, it helps transform a logical digital circuit into a layout that can later be analyzed and exported for fabrication.

Below is a starter run_openroad.tcl for my ring_modulator project. I wrote it as a simple OpenROAD flow that reads the Sky130 HD technology files, loads my synthesized netlist, applies the clock constraint, performs floorplanning, placement, CTS, routing, and finally writes out the main reports and layout files.

I will probably need to adjust some paths depending on my local setup, especially the PDK paths, the synthesized netlist filename, and the clock port name if I change the top-level module later. But as a starting point, this gives me a clean physical-design script that matches the flow Andreas described in class.

# run_openroad.tcl - Place & Route script

# Read technology files
read_lef $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

# Read synthesized netlist (from Yosys)
read_verilog ring_modulator_synth.v
link_design ring_modulator

# Read timing constraints
read_sdc constraints.sdc

# Initialize floorplan (core utilization, aspect ratio, core-to-die margin)
initialize_floorplan -utilization 50 -aspect_ratio 1 -core_space 2

# Create power distribution network
source $::env(PDK_ROOT)/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info
pdngen

# Place standard cells
global_placement
detailed_placement

# Clock tree synthesis
clock_tree_synthesis

# Route
global_route
detailed_route

# Write outputs
write_def ring_modulator.def
write_verilog ring_modulator_pnr.v

I also need a simple constraints.sdc. For example, if I want to start with a 50 MHz target:

# Define a 50 MHz clock (20 ns period) on the 'clk' input
create_clock -name clk -period 20 [get_ports clk]
set_clock_uncertainty 0.2 [get_clocks clk]

Typical command to run it:

# From command line
openroad run_openroad.tcl

# Or interactively
openroad
openroad> source run_openroad.tcl

But i recive several errors.

[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells [ERROR IFP-0035] use -site to add placement rows. Error: run_openroad.tcl, 22 IFP-0035

I had to ask ChatGPT to help me resolve the error, because I was not sure how to fix it properly by myself. It helped me identify the issue and correct the code so I could continue the workflow.

To make the OpenROAD script work correctly, I had to modify the floorplanning and I/O placement steps. First, the initialize_floorplan command needed the -site unithd option. Without it, OpenROAD could define the die and core areas, but it could not create the standard-cell placement rows, which caused the error asking to “use -site to add placement rows.” In the SKY130 sky130_fd_sc_hd library, unithd is the correct placement site for the standard-cell rows.

OpenROAD 26Q1-990-g15af3a5c0 
Features included (+) or not (-): +GPU +GUI +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef, created 14 layers, 25 vias
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef at line 2.

[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells
[WARNING IFP-0028] Core area lower left (20.000, 20.000) snapped to (20.240, 21.760).
[INFO IFP-0001] Added 94 rows of 564 site unithd.
[INFO IFP-0100] Die BBox:  (  0.000  0.000 ) ( 300.000 300.000 ) um
[INFO IFP-0101] Core BBox: ( 20.240 21.760 ) ( 279.680 277.440 ) um
[INFO IFP-0102] Core area:                        66333.619 um^2
[INFO IFP-0103] Total instances area:             10792.851 um^2
[INFO IFP-0104] Effective utilization:                0.163
[INFO IFP-0105] Number of instances:                   1327
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: (  0.460  2.720 ) um
[INFO GPL-0004] CoreBBox: ( 20.240 21.760 ) ( 279.680 277.440 ) um
[INFO GPL-0036] Movable instances area:      10792.851 um^2
[INFO GPL-0037] Total instances area:        10792.851 um^2
[INFO GPL-0035] Pin density area adjust:       576.506 um^2
[ERROR GPL-0326] carrier_in[0] toplevel port is not placed.
Error: run_openroad.tcl, 37 GPL-0326

After fixing the floorplan, the next issue was that the top-level ports of the design were still unplaced. OpenROAD requires explicit I/O pin placement before global placement can continue, so I added a place_pins step. This command places the top-level pins on the die boundary and creates the corresponding metal shapes for them on the routing grid. In my case, I used horizontal and vertical routing layers for the pins, so OpenROAD could assign physical locations to inputs and outputs such as carrier_in[0].

I also added make_tracks after initialize_floorplan. This is useful because the floorplan step defines the geometry of the design, while the routing tracks provide the grid needed later for pin placement and routing. Once the rows, tracks, and top-level pins were properly defined, OpenROAD was able to continue with global placement and the rest of the physical design flow.

# run_openroad.tcl

set design_name ring_modulator
set top_module  ring_modulator
set netlist     "ring_modulator_synth.v"
set sdc_file    "constraints.sdc"

set out_dir "openroad_out"
file mkdir $out_dir

set pdk_root $::env(PDK_ROOT)

# Technology + standard cells
read_lef $pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
read_lef $pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
read_liberty $pdk_root/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

# Netlist
read_verilog $netlist
link_design $top_module

# Constraints
read_sdc $sdc_file

# Floorplan
initialize_floorplan \
  -die_area  "0 0 200 200" \
  -core_area "20 20 180 180" \
  -site unithd

# Recreate routing tracks after floorplan
make_tracks

# Place top-level IO pins
place_pins \
  -hor_layers met3 \
  -ver_layers met2

# Standard-cell placement
global_placement
detailed_placement

# Routing
global_route
detailed_route

# Outputs
write_def $out_dir/${design_name}.def
write_verilog $out_dir/${design_name}_pnr.v

report_design_area
report_checks
report_power

Terminal OpenRoad

/foss/designs/ring_modulator > openroad run_openroad_50Mhzs.tcl
OpenROAD 26Q1-990-g15af3a5c0 
Features included (+) or not (-): +GPU +GUI +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef, created 14 layers, 25 vias
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef at line 2.

[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells
[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.
[WARNING IFP-0028] Core area lower left (20.000, 20.000) snapped to (20.240, 21.760).
[INFO IFP-0001] Added 58 rows of 347 site unithd.
[INFO IFP-0100] Die BBox:  (  0.000  0.000 ) ( 200.000 200.000 ) um
[INFO IFP-0101] Core BBox: ( 20.240 21.760 ) ( 179.860 179.520 ) um
[INFO IFP-0102] Core area:                        25181.651 um^2
[INFO IFP-0103] Total instances area:             10792.851 um^2
[INFO IFP-0104] Effective utilization:                0.429
[INFO IFP-0105] Number of instances:                   1327
Found 0 macro blocks.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0001] Number of available slots 718
[INFO PPL-0002] Number of I/O             50
[INFO PPL-0003] Number of I/O w/sink      50
[INFO PPL-0004] Number of I/O w/o sink    0
[INFO PPL-0005] Slots per section         200
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 5850.00 um.
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: (  0.460  2.720 ) um
[INFO GPL-0004] CoreBBox: ( 20.240 21.760 ) ( 179.860 179.520 ) um
[INFO GPL-0036] Movable instances area:      10792.851 um^2
[INFO GPL-0037] Total instances area:        10792.851 um^2
[INFO GPL-0035] Pin density area adjust:       576.506 um^2
[INFO GPL-0032] ---- Initialize Region: Top-level
[INFO GPL-0006] Number of instances:              1327
[INFO GPL-0007] Movable instances:                1327
[INFO GPL-0008] Fixed instances:                     0
[INFO GPL-0009] Dummy instances:                     0
[INFO GPL-0010] Number of nets:                   1376
[INFO GPL-0011] Number of pins:                   4544
[INFO GPL-0012] Die BBox:  (  0.000  0.000 ) ( 200.000 200.000 ) um
[INFO GPL-0013] Core BBox: ( 20.240 21.760 ) ( 179.860 179.520 ) um
[INFO GPL-0016] Core area:                   25181.651 um^2
[INFO GPL-0014] Region name: top-level.
[INFO GPL-0015] Region area:                 25181.651 um^2
[INFO GPL-0017] Fixed instances area:            0.000 um^2
[INFO GPL-0018] Movable instances area:      11369.357 um^2
[INFO GPL-0019] Utilization:                    45.149 %
[INFO GPL-0020] Standard cells area:         11369.357 um^2
[INFO GPL-0021] Large instances area:            0.000 um^2
[INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
[INFO GPL-0051] Source of initial instance position counters:
    Odb location = 0    Core center = 1327  Region center = 0
[InitialPlace]  Iter: 1 conjugate gradient residual: 0.00000012 HPWL: 24479640
[InitialPlace]  Iter: 2 conjugate gradient residual: 0.00000010 HPWL: 11932617
[InitialPlace]  Iter: 3 conjugate gradient residual: 0.00000011 HPWL: 11928544
[InitialPlace]  Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 11941236
[InitialPlace]  Iter: 5 conjugate gradient residual: 0.00000010 HPWL: 11933140
[INFO GPL-0033] ---- Initialize Nesterov Region: Top-level
[INFO GPL-0023] Placement target density:       0.7000
[INFO GPL-0024] Movable insts average area:      8.568 um^2
[INFO GPL-0025] Ideal bin area:                 12.240 um^2
[INFO GPL-0026] Ideal bin count:                  2057
[INFO GPL-0027] Total bin area:              25181.651 um^2
[INFO GPL-0028] Bin count (X, Y):          32 ,     32
[INFO GPL-0029] Bin size (W * H):       4.988 *  4.930 um
[INFO GPL-0030] Number of bins:                   1024
[INFO GPL-0007] ---- Execute Nesterov Global Placement.
[INFO GPL-0031] HPWL: Half-Perimeter Wirelength
Iteration | Overflow |     HPWL (um) |  HPWL(%) |   Penalty | Group
---------------------------------------------------------------
        0 |   0.9871 |  5.067019e+03 |   +0.00% |  1.56e-15 |      
       10 |   0.9685 |  4.739293e+03 |   -6.47% |  2.54e-15 |      
       20 |   0.9686 |  4.736841e+03 |   -0.05% |  4.14e-15 |      
       30 |   0.9686 |  4.737713e+03 |   +0.02% |  6.75e-15 |      
       40 |   0.9686 |  4.737197e+03 |   -0.01% |  1.10e-14 |      
       50 |   0.9686 |  4.736066e+03 |   -0.02% |  1.79e-14 |      
       60 |   0.9686 |  4.735912e+03 |   -0.00% |  2.92e-14 |      
       70 |   0.9685 |  4.736710e+03 |   +0.02% |  4.75e-14 |      
       80 |   0.9685 |  4.738283e+03 |   +0.03% |  7.74e-14 |      
       90 |   0.9685 |  4.740634e+03 |   +0.05% |  1.26e-13 |      
      100 |   0.9684 |  4.745291e+03 |   +0.10% |  2.05e-13 |      
      110 |   0.9684 |  4.754373e+03 |   +0.19% |  3.35e-13 |      
      120 |   0.9682 |  4.770138e+03 |   +0.33% |  5.45e-13 |      
      130 |   0.9680 |  4.798578e+03 |   +0.60% |  8.88e-13 |      
      140 |   0.9676 |  4.852283e+03 |   +1.12% |  1.45e-12 |      
      150 |   0.9662 |  4.964603e+03 |   +2.31% |  2.35e-12 |      
      160 |   0.9616 |  5.221878e+03 |   +5.18% |  3.84e-12 |      
      170 |   0.9569 |  5.701178e+03 |   +9.18% |  6.25e-12 |      
      180 |   0.9449 |  6.384858e+03 |  +11.99% |  1.02e-11 |      
      190 |   0.9265 |  7.046349e+03 |  +10.36% |  1.66e-11 |      
      200 |   0.9055 |  7.691506e+03 |   +9.16% |  2.70e-11 |      
      210 |   0.8812 |  8.430799e+03 |   +9.61% |  4.40e-11 |      
      220 |   0.8518 |  9.355397e+03 |  +10.97% |  7.16e-11 |      
      230 |   0.8211 |  1.041856e+04 |  +11.36% |  1.17e-10 |      
      240 |   0.7841 |  1.140621e+04 |   +9.48% |  1.90e-10 |      
      250 |   0.7451 |  1.242977e+04 |   +8.97% |  3.09e-10 |      
      260 |   0.7052 |  1.337410e+04 |   +7.60% |  5.04e-10 |      
      270 |   0.6577 |  1.440097e+04 |   +7.68% |  8.21e-10 |      
      280 |   0.6124 |  1.533307e+04 |   +6.47% |  1.34e-09 |      
      290 |   0.5630 |  1.611453e+04 |   +5.10% |  2.18e-09 |      
      300 |   0.5065 |  1.669529e+04 |   +3.60% |  3.55e-09 |      
      310 |   0.4575 |  1.699003e+04 |   +1.77% |  5.78e-09 |      
      320 |   0.4164 |  1.737706e+04 |   +2.28% |  9.41e-09 |      
      330 |   0.3532 |  1.749215e+04 |   +0.66% |  1.53e-08 |      
      340 |   0.3126 |  1.749517e+04 |   +0.02% |  2.30e-08 |      
      350 |   0.2765 |  1.773039e+04 |   +1.34% |  3.39e-08 |      
      360 |   0.2553 |  1.798743e+04 |   +1.45% |  5.00e-08 |      
      370 |   0.2242 |  1.802507e+04 |   +0.21% |  7.36e-08 |      
      380 |   0.2025 |  1.806830e+04 |   +0.24% |  1.08e-07 |      
      390 |   0.1800 |  1.808768e+04 |   +0.11% |  1.60e-07 |      
      400 |   0.1561 |  1.809788e+04 |   +0.06% |  2.35e-07 |      
      410 |   0.1338 |  1.810114e+04 |   +0.02% |  3.47e-07 |      
      420 |   0.1165 |  1.814420e+04 |   +0.24% |  5.11e-07 |      
      429 |   0.0996 |  1.818017e+04 |          |  7.53e-07 |      
---------------------------------------------------------------
[INFO GPL-1001] Global placement finished at iteration 429
[INFO GPL-1002] Placed Cell Area            11369.3568
[INFO GPL-1003] Available Free Area         25181.6512
[INFO GPL-1004] Minimum Feasible Density        0.4600 (cell_area / free_area)
[INFO GPL-1006]   Suggested Target Densities:
[INFO GPL-1007]     - For 90% usage of free space: 0.5017
[INFO GPL-1008]     - For 80% usage of free space: 0.5644
[INFO GPL-1009]     - For 50% usage of free space: 0.9030
[INFO GPL-1014] Final placement area: 11369.36 (+0.00%)
Placement Analysis
---------------------------------
total displacement       3015.3 u
average displacement        2.3 u
max displacement           12.3 u
original HPWL           18236.6 u
legalized HPWL          21484.5 u
delta HPWL                   18 %

[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4

Units:                1000
Number of layers:     13
Number of macros:     437
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.

Design:                   ring_modulator
Die area:                 ( 0 0 ) ( 200000 200000 )
Number of track patterns: 12
Number of DEF vias:       0
Number of components:     1327
Number of terminals:      50
Number of snets:          0
Number of nets:           1376

[INFO DRT-0167] List of default vias:
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: M2M3_PR
  Layer via3
    default via: M3M4_PR
  Layer via4
    default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
[INFO DRT-0164] Number of unique instances = 78.
[INFO DRT-0168] Init region query.
[INFO DRT-0024]   Complete FR_MASTERSLICE.
[INFO DRT-0024]   Complete licon.
[INFO DRT-0024]   Complete li1.
[INFO DRT-0024]   Complete mcon.
[INFO DRT-0024]   Complete met1.
[INFO DRT-0024]   Complete via.
[INFO DRT-0024]   Complete met2.
[INFO DRT-0024]   Complete via2.
[INFO DRT-0024]   Complete met3.
[INFO DRT-0024]   Complete via3.
[INFO DRT-0024]   Complete met4.
[INFO DRT-0024]   Complete via4.
[INFO DRT-0024]   Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] licon shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 34554.
[INFO DRT-0033] mcon shape region query size = 0.
[INFO DRT-0033] met1 shape region query size = 3922.
[INFO DRT-0033] via shape region query size = 0.
[INFO DRT-0033] met2 shape region query size = 0.
[INFO DRT-0033] via2 shape region query size = 0.
[INFO DRT-0033] met3 shape region query size = 50.
[INFO DRT-0033] via3 shape region query size = 0.
[INFO DRT-0033] met4 shape region query size = 0.
[INFO DRT-0033] via4 shape region query size = 0.
[INFO DRT-0033] met5 shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0078]   Complete 636 pins.
[INFO DRT-0081]   Complete 78 unique inst patterns.
[INFO DRT-0084]   Complete 673 groups.
#scanned instances     = 1327
#unique  instances     = 78
#stdCellGenAp          = 2357
#stdCellValidPlanarAp  = 8
#stdCellValidViaAp     = 1936
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 4494
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:27, elapsed time = 00:00:27, memory = 217.70 (MB), peak = 217.66 (MB)

[INFO DRT-0157] Number of guides:     8400

[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 28 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 28 STEP 6900 ;
[INFO DRT-0028]   Complete FR_MASTERSLICE.
[INFO DRT-0028]   Complete licon.
[INFO DRT-0028]   Complete li1.
[INFO DRT-0028]   Complete mcon.
[INFO DRT-0028]   Complete met1.
[INFO DRT-0028]   Complete via.
[INFO DRT-0028]   Complete met2.
[INFO DRT-0028]   Complete via2.
[INFO DRT-0028]   Complete met3.
[INFO DRT-0028]   Complete via3.
[INFO DRT-0028]   Complete met4.
[INFO DRT-0028]   Complete via4.
[INFO DRT-0028]   Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035]   Complete FR_MASTERSLICE (guide).
[INFO DRT-0035]   Complete licon (guide).
[INFO DRT-0035]   Complete li1 (guide).
[INFO DRT-0035]   Complete mcon (guide).
[INFO DRT-0035]   Complete met1 (guide).
[INFO DRT-0035]   Complete via (guide).
[INFO DRT-0035]   Complete met2 (guide).
[INFO DRT-0035]   Complete via2 (guide).
[INFO DRT-0035]   Complete met3 (guide).
[INFO DRT-0035]   Complete via3 (guide).
[INFO DRT-0035]   Complete met4 (guide).
[INFO DRT-0035]   Complete via4 (guide).
[INFO DRT-0035]   Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] licon guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 3222.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 2550.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 1154.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 55.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 0.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 218.51 (MB), peak = 218.45 (MB)
[INFO DRT-0245] skipped writing guide updates to database.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 4376 vertical wires in 1 frboxes and 2605 horizontal wires in 1 frboxes.
[INFO DRT-0186] Done with 351 vertical wires in 1 frboxes and 775 horizontal wires in 1 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 227.74 (MB), peak = 227.70 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 227.86 (MB), peak = 227.70 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 227.86 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:04, memory = 254.52 (MB).
    Completing 30% with 90 violations.
    elapsed time = 00:00:04, memory = 254.52 (MB).
    Completing 40% with 90 violations.
    elapsed time = 00:00:10, memory = 268.52 (MB).
    Completing 50% with 90 violations.
    elapsed time = 00:00:12, memory = 272.52 (MB).
    Completing 60% with 200 violations.
    elapsed time = 00:00:13, memory = 272.52 (MB).
    Completing 70% with 200 violations.
    elapsed time = 00:00:16, memory = 288.62 (MB).
    Completing 80% with 291 violations.
    elapsed time = 00:00:17, memory = 288.62 (MB).
    Completing 90% with 291 violations.
    elapsed time = 00:00:20, memory = 291.07 (MB).
    Completing 100% with 416 violations.
    elapsed time = 00:00:21, memory = 291.07 (MB).
[INFO DRT-0199]   Number of violations = 440.
Viol/Layer        mcon   met1   met2
Cut Spacing          2      0      0
Metal Spacing        0    109     13
Recheck              0     18      6
Short                0    277     15
[INFO DRT-0267] cpu time = 00:00:21, elapsed time = 00:00:21, memory = 591.20 (MB), peak = 591.02 (MB)
Total wire length = 26355 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 13630 um.
Total wire length on LAYER met2 = 11672 um.
Total wire length on LAYER met3 = 1051 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8782.
Up-via summary (total 8782):

-----------------------
 FR_MASTERSLICE       0
            li1    4538
           met1    4160
           met2      84
           met3       0
           met4       0
-----------------------
               8782


[INFO DRT-0195] Start 1st optimization iteration.
    Completing 10% with 440 violations.
    elapsed time = 00:00:00, memory = 591.20 (MB).
    Completing 20% with 440 violations.
    elapsed time = 00:00:01, memory = 591.20 (MB).
    Completing 30% with 440 violations.
    elapsed time = 00:00:01, memory = 591.20 (MB).
    Completing 40% with 412 violations.
    elapsed time = 00:00:02, memory = 591.20 (MB).
    Completing 50% with 412 violations.
    elapsed time = 00:00:07, memory = 591.20 (MB).
    Completing 60% with 412 violations.
    elapsed time = 00:00:07, memory = 591.20 (MB).
    Completing 70% with 352 violations.
    elapsed time = 00:00:07, memory = 591.20 (MB).
    Completing 80% with 352 violations.
    elapsed time = 00:00:10, memory = 591.20 (MB).
    Completing 90% with 310 violations.
    elapsed time = 00:00:10, memory = 591.20 (MB).
    Completing 100% with 229 violations.
    elapsed time = 00:00:19, memory = 591.20 (MB).
[INFO DRT-0199]   Number of violations = 229.
Viol/Layer        mcon   met1   met2
Cut Spacing          2      0      0
Metal Spacing        0     57      0
Short                0    167      3
[INFO DRT-0267] cpu time = 00:00:19, elapsed time = 00:00:19, memory = 591.25 (MB), peak = 591.02 (MB)
Total wire length = 26108 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 13469 um.
Total wire length on LAYER met2 = 11560 um.
Total wire length on LAYER met3 = 1079 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8718.
Up-via summary (total 8718):

-----------------------
 FR_MASTERSLICE       0
            li1    4533
           met1    4098
           met2      87
           met3       0
           met4       0
-----------------------
               8718


[INFO DRT-0195] Start 2nd optimization iteration.
    Completing 10% with 229 violations.
    elapsed time = 00:00:00, memory = 591.25 (MB).
    Completing 20% with 229 violations.
    elapsed time = 00:00:02, memory = 591.25 (MB).
    Completing 30% with 229 violations.
    elapsed time = 00:00:03, memory = 591.25 (MB).
    Completing 40% with 245 violations.
    elapsed time = 00:00:03, memory = 591.25 (MB).
    Completing 50% with 245 violations.
    elapsed time = 00:00:05, memory = 591.25 (MB).
    Completing 60% with 245 violations.
    elapsed time = 00:00:07, memory = 591.25 (MB).
    Completing 70% with 264 violations.
    elapsed time = 00:00:07, memory = 591.25 (MB).
    Completing 80% with 264 violations.
    elapsed time = 00:00:11, memory = 591.25 (MB).
    Completing 90% with 254 violations.
    elapsed time = 00:00:11, memory = 591.25 (MB).
    Completing 100% with 248 violations.
    elapsed time = 00:00:19, memory = 591.25 (MB).
[INFO DRT-0199]   Number of violations = 248.
Viol/Layer        mcon   met1   met2   met3
Cut Spacing          6      0      0      0
Metal Spacing        0     41      4      1
Short                0    186     10      0
[INFO DRT-0267] cpu time = 00:00:19, elapsed time = 00:00:19, memory = 591.41 (MB), peak = 591.18 (MB)
Total wire length = 26037 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 13411 um.
Total wire length on LAYER met2 = 11536 um.
Total wire length on LAYER met3 = 1089 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8736.
Up-via summary (total 8736):

-----------------------
 FR_MASTERSLICE       0
            li1    4533
           met1    4117
           met2      86
           met3       0
           met4       0
-----------------------
               8736


[INFO DRT-0195] Start 3rd optimization iteration.
    Completing 10% with 248 violations.
    elapsed time = 00:00:00, memory = 591.41 (MB).
    Completing 20% with 248 violations.
    elapsed time = 00:00:01, memory = 591.41 (MB).
    Completing 30% with 211 violations.
    elapsed time = 00:00:01, memory = 591.41 (MB).
    Completing 40% with 211 violations.
    elapsed time = 00:00:03, memory = 591.41 (MB).
    Completing 50% with 211 violations.
    elapsed time = 00:00:04, memory = 591.41 (MB).
    Completing 60% with 108 violations.
    elapsed time = 00:00:05, memory = 591.41 (MB).
    Completing 70% with 108 violations.
    elapsed time = 00:00:07, memory = 591.41 (MB).
    Completing 80% with 81 violations.
    elapsed time = 00:00:08, memory = 591.41 (MB).
    Completing 90% with 81 violations.
    elapsed time = 00:00:09, memory = 591.41 (MB).
    Completing 100% with 12 violations.
    elapsed time = 00:00:09, memory = 591.41 (MB).
[INFO DRT-0199]   Number of violations = 12.
Viol/Layer        met1
Metal Spacing        2
Short               10
[INFO DRT-0267] cpu time = 00:00:09, elapsed time = 00:00:09, memory = 591.41 (MB), peak = 591.18 (MB)
Total wire length = 25936 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 12540 um.
Total wire length on LAYER met2 = 11494 um.
Total wire length on LAYER met3 = 1901 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8863.
Up-via summary (total 8863):

-----------------------
 FR_MASTERSLICE       0
            li1    4535
           met1    4132
           met2     196
           met3       0
           met4       0
-----------------------
               8863


[INFO DRT-0195] Start 4th guides tiles iteration.
    Completing 30% with 12 violations.
    elapsed time = 00:00:00, memory = 591.41 (MB).
    Completing 60% with 12 violations.
    elapsed time = 00:00:00, memory = 591.41 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 591.41 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 591.41 (MB), peak = 591.18 (MB)
Total wire length = 25929 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 12537 um.
Total wire length on LAYER met2 = 11492 um.
Total wire length on LAYER met3 = 1899 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8860.
Up-via summary (total 8860):

-----------------------
 FR_MASTERSLICE       0
            li1    4535
           met1    4129
           met2     196
           met3       0
           met4       0
-----------------------
               8860


[WARNING DRT-0290] Warning: no DRC report specified, skipped writing DRC report
[INFO DRT-0198] Complete detail routing.
Total wire length = 25929 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 12537 um.
Total wire length on LAYER met2 = 11492 um.
Total wire length on LAYER met3 = 1899 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8860.
Up-via summary (total 8860):

-----------------------
 FR_MASTERSLICE       0
            li1    4535
           met1    4129
           met2     196
           met3       0
           met4       0
-----------------------
               8860


[INFO DRT-0267] cpu time = 00:01:11, elapsed time = 00:01:11, memory = 591.46 (MB), peak = 591.36 (MB)

[INFO DRT-0180] Post processing.
Design area 10793 um^2 43% utilization.
Startpoint: carrier_in[5] (input port clocked by clk)
Endpoint: _2607_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   5.00    5.00 ^ input external delay
   0.00    5.00 ^ carrier_in[5] (in)
   0.13    5.13 ^ _1564_/X (sky130_fd_sc_hd__and2_0)
   0.44    5.57 v _1639_/X (sky130_fd_sc_hd__xor3_1)
   0.39    5.96 v _1643_/X (sky130_fd_sc_hd__xor3_1)
   0.10    6.06 ^ _1644_/Y (sky130_fd_sc_hd__nand2_1)
   0.41    6.47 v _1663_/X (sky130_fd_sc_hd__xnor3_1)
   0.37    6.84 v _1664_/X (sky130_fd_sc_hd__maj3_1)
   0.38    7.22 v _1750_/X (sky130_fd_sc_hd__xor3_1)
   0.11    7.33 ^ _1751_/Y (sky130_fd_sc_hd__o22ai_1)
   0.09    7.43 ^ _1752_/X (sky130_fd_sc_hd__a21o_1)
   0.05    7.48 v _1756_/Y (sky130_fd_sc_hd__a21oi_1)
   0.34    7.82 v _1757_/X (sky130_fd_sc_hd__maj3_1)
   0.20    8.02 ^ _1761_/Y (sky130_fd_sc_hd__o221ai_1)
   0.16    8.18 ^ _1764_/X (sky130_fd_sc_hd__a211o_1)
   0.06    8.25 v _1910_/Y (sky130_fd_sc_hd__a211oi_1)
   0.20    8.45 ^ _2046_/Y (sky130_fd_sc_hd__o211ai_1)
   0.11    8.56 v _2170_/Y (sky130_fd_sc_hd__a211oi_1)
   0.22    8.78 v _2226_/X (sky130_fd_sc_hd__o21a_1)
   0.36    9.14 ^ _2337_/Y (sky130_fd_sc_hd__o311ai_0)
   0.16    9.30 v _2388_/Y (sky130_fd_sc_hd__a21boi_0)
   0.22    9.52 ^ _2432_/Y (sky130_fd_sc_hd__o21ai_0)
   0.12    9.65 v _2482_/Y (sky130_fd_sc_hd__a21oi_1)
   0.18    9.83 ^ _2524_/Y (sky130_fd_sc_hd__o21ai_0)
   0.10    9.93 v _2527_/Y (sky130_fd_sc_hd__nand2_1)
   0.36   10.29 v _2556_/X (sky130_fd_sc_hd__maj3_1)
   0.13   10.42 v _2575_/Y (sky130_fd_sc_hd__xnor2_1)
   0.00   10.42 v _2607_/D (sky130_fd_sc_hd__dfrtp_1)
          10.42   data arrival time

  20.00   20.00   clock clk (rise edge)
   0.00   20.00   clock network delay (ideal)
  -0.50   19.50   clock uncertainty
   0.00   19.50   clock reconvergence pessimism
          19.50 ^ _2607_/CLK (sky130_fd_sc_hd__dfrtp_1)
  -0.12   19.38   library setup time
          19.38   data required time
---------------------------------------------------------
          19.38   data required time
         -10.42   data arrival time
---------------------------------------------------------
           8.96   slack (MET)


Group                  Internal  Switching    Leakage      Total
                          Power      Power      Power      Power (Watts)
----------------------------------------------------------------
Sequential             1.36e-04   2.58e-06   3.68e-10   1.38e-04   6.7%
Combinational          1.05e-03   8.63e-04   4.01e-09   1.92e-03  93.3%
Clock                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
----------------------------------------------------------------
Total                  1.19e-03   8.65e-04   4.38e-09   2.05e-03 100.0%
                          57.9%      42.1%       0.0%
openroad> 

Timing Report

In OpenROAD, a Timing Report is the result of the static timing analysis performed by OpenSTA to check whether the design meets its timing constraints. It evaluates the delay of signal paths in the synthesized or placed-and-routed circuit and compares the data arrival time with the data required time, based on the clock definition and the SDC constraints. This report is used to determine whether the design can operate correctly at the target frequency.*

A timing report in OpenROAD usually shows the startpoint, endpoint, path group, data arrival time, data required time, and slack. The most important result is the slack: if it is positive, the path meets timing; if it is negative, the path violates the timing constraint. In this way, the timing report helps identify the critical paths of the design and verify whether the implementation is fast enough for the selected clock period. OpenROAD uses OpenSTA as its timing engine.

I will run several simulations to evaluate whether the clock frequency is properly adjusted to the behavior of my circuit. By testing different clock speeds, I can verify the timing performance of the design and identify a frequency at which the circuit works reliably.

Run at 50Mhzs

[INFO DRT-0180] Post processing.
Design area 10793 um^2 43% utilization.
Startpoint: carrier_in[5] (input port clocked by clk)
Endpoint: _2607_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   5.00    5.00 ^ input external delay
   0.00    5.00 ^ carrier_in[5] (in)
   0.13    5.13 ^ _1564_/X (sky130_fd_sc_hd__and2_0)
   0.44    5.57 v _1639_/X (sky130_fd_sc_hd__xor3_1)
   0.39    5.96 v _1643_/X (sky130_fd_sc_hd__xor3_1)
   0.10    6.06 ^ _1644_/Y (sky130_fd_sc_hd__nand2_1)
   0.41    6.47 v _1663_/X (sky130_fd_sc_hd__xnor3_1)
   0.37    6.84 v _1664_/X (sky130_fd_sc_hd__maj3_1)
   0.38    7.22 v _1750_/X (sky130_fd_sc_hd__xor3_1)
   0.11    7.33 ^ _1751_/Y (sky130_fd_sc_hd__o22ai_1)
   0.09    7.43 ^ _1752_/X (sky130_fd_sc_hd__a21o_1)
   0.05    7.48 v _1756_/Y (sky130_fd_sc_hd__a21oi_1)
   0.34    7.82 v _1757_/X (sky130_fd_sc_hd__maj3_1)
   0.20    8.02 ^ _1761_/Y (sky130_fd_sc_hd__o221ai_1)
   0.16    8.18 ^ _1764_/X (sky130_fd_sc_hd__a211o_1)
   0.06    8.25 v _1910_/Y (sky130_fd_sc_hd__a211oi_1)
   0.20    8.45 ^ _2046_/Y (sky130_fd_sc_hd__o211ai_1)
   0.11    8.56 v _2170_/Y (sky130_fd_sc_hd__a211oi_1)
   0.22    8.78 v _2226_/X (sky130_fd_sc_hd__o21a_1)
   0.36    9.14 ^ _2337_/Y (sky130_fd_sc_hd__o311ai_0)
   0.16    9.30 v _2388_/Y (sky130_fd_sc_hd__a21boi_0)
   0.22    9.52 ^ _2432_/Y (sky130_fd_sc_hd__o21ai_0)
   0.12    9.65 v _2482_/Y (sky130_fd_sc_hd__a21oi_1)
   0.18    9.83 ^ _2524_/Y (sky130_fd_sc_hd__o21ai_0)
   0.10    9.93 v _2527_/Y (sky130_fd_sc_hd__nand2_1)
   0.36   10.29 v _2556_/X (sky130_fd_sc_hd__maj3_1)
   0.13   10.42 v _2575_/Y (sky130_fd_sc_hd__xnor2_1)
   0.00   10.42 v _2607_/D (sky130_fd_sc_hd__dfrtp_1)
          10.42   data arrival time

  20.00   20.00   clock clk (rise edge)
   0.00   20.00   clock network delay (ideal)
  -0.50   19.50   clock uncertainty
   0.00   19.50   clock reconvergence pessimism
          19.50 ^ _2607_/CLK (sky130_fd_sc_hd__dfrtp_1)
  -0.12   19.38   library setup time
          19.38   data required time
---------------------------------------------------------
          19.38   data required time
         -10.42   data arrival time
---------------------------------------------------------
           8.96   slack (MET)

The timing report shows that the design has a total area of 10,793 µm² and an effective utilization of about 16%, which means the core is relatively lightly occupied and still has plenty of free space for placement and routing. This is a positive result, since lower utilization usually reduces congestion and makes the physical implementation easier.

The reported path is a register-to-register maximum timing path in the clk domain. The startpoint is flip-flop _2592_, and the endpoint is flip-flop _2576_, both triggered by the rising edge of the same clock. This means the tool is checking whether data launched from one flip-flop can travel through the logic and reach the next flip-flop before the following clock edge.

In this case, the path is very short. The data is launched at 0.00 ns, and the source flip-flop contributes a clock-to-Q delay of 0.33 ns. The signal then reaches the destination input at 0.33 ns, with no additional combinational delay shown in the report. This indicates that the connection between these registers is very fast.

On the capture side, the next active clock edge is at 20.00 ns, corresponding to a 50 MHz clock. After subtracting the clock uncertainty of 0.20 ns and the setup time of 0.12 ns, the required arrival time becomes 19.68 ns. Since the actual arrival time is only 10.42 ns, the final setup slack is 8.96 ns, which is strongly positive.

This means the path meets timing comfortably. The margin is very large, so the design is operating well within the imposed clock constraint. In practice, this suggests that timing is not a limiting factor for this design at the current frequency, and the circuit could likely run at a significantly higher clock rate before setup violations appear.

Run at 20Mhzs

In this case, the constraints.sdc file is the same as in the class example, except for the clock period. Because I want to run the design at 20 MHz instead of 50 MHz, I need to change the clock period from 20 ns to 50 ns. The other constraints are kept unchanged, so the file still defines the input and output timing assumptions, marks the reset as asynchronous, and adds a small clock uncertainty margin.

# Define a 20 MHz clock (50 ns period) on the 'clk' input
create_clock -name clk -period 50 [get_ports clk]

# Input signals arrive 5 ns after clock edge
set_input_delay -clock clk 5 [all_inputs]

# Output signals must be valid 5 ns before next clock edge
set_output_delay -clock clk 5 [all_outputs]

# Reset is asynchronous - don't check timing on it
set_false_path -from [get_ports rst_n]

# Account for clock jitter/skew
set_clock_uncertainty 0.5 [get_clocks clk]

Terminal OpenRoad 20Mhzs

/foss/designs/ring_modulator > openroad run_openroad.tcl
OpenROAD 26Q1-990-g15af3a5c0 
Features included (+) or not (-): +GPU +GUI +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef, created 14 layers, 25 vias
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef at line 2.

[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells
[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.
[WARNING IFP-0028] Core area lower left (20.000, 20.000) snapped to (20.240, 21.760).
[INFO IFP-0001] Added 58 rows of 347 site unithd.
[INFO IFP-0100] Die BBox:  (  0.000  0.000 ) ( 200.000 200.000 ) um
[INFO IFP-0101] Core BBox: ( 20.240 21.760 ) ( 179.860 179.520 ) um
[INFO IFP-0102] Core area:                        25181.651 um^2
[INFO IFP-0103] Total instances area:             10792.851 um^2
[INFO IFP-0104] Effective utilization:                0.429
[INFO IFP-0105] Number of instances:                   1327
Found 0 macro blocks.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0001] Number of available slots 718
[INFO PPL-0002] Number of I/O             50
[INFO PPL-0003] Number of I/O w/sink      50
[INFO PPL-0004] Number of I/O w/o sink    0
[INFO PPL-0005] Slots per section         200
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 5850.00 um.
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: (  0.460  2.720 ) um
[INFO GPL-0004] CoreBBox: ( 20.240 21.760 ) ( 179.860 179.520 ) um
[INFO GPL-0036] Movable instances area:      10792.851 um^2
[INFO GPL-0037] Total instances area:        10792.851 um^2
[INFO GPL-0035] Pin density area adjust:       576.506 um^2
[INFO GPL-0032] ---- Initialize Region: Top-level
[INFO GPL-0006] Number of instances:              1327
[INFO GPL-0007] Movable instances:                1327
[INFO GPL-0008] Fixed instances:                     0
[INFO GPL-0009] Dummy instances:                     0
[INFO GPL-0010] Number of nets:                   1376
[INFO GPL-0011] Number of pins:                   4544
[INFO GPL-0012] Die BBox:  (  0.000  0.000 ) ( 200.000 200.000 ) um
[INFO GPL-0013] Core BBox: ( 20.240 21.760 ) ( 179.860 179.520 ) um
[INFO GPL-0016] Core area:                   25181.651 um^2
[INFO GPL-0014] Region name: top-level.
[INFO GPL-0015] Region area:                 25181.651 um^2
[INFO GPL-0017] Fixed instances area:            0.000 um^2
[INFO GPL-0018] Movable instances area:      11369.357 um^2
[INFO GPL-0019] Utilization:                    45.149 %
[INFO GPL-0020] Standard cells area:         11369.357 um^2
[INFO GPL-0021] Large instances area:            0.000 um^2
[INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
[INFO GPL-0051] Source of initial instance position counters:
    Odb location = 0    Core center = 1327  Region center = 0
[InitialPlace]  Iter: 1 conjugate gradient residual: 0.00000012 HPWL: 24479640
[InitialPlace]  Iter: 2 conjugate gradient residual: 0.00000010 HPWL: 11932617
[InitialPlace]  Iter: 3 conjugate gradient residual: 0.00000011 HPWL: 11928544
[InitialPlace]  Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 11941236
[InitialPlace]  Iter: 5 conjugate gradient residual: 0.00000010 HPWL: 11933140
[INFO GPL-0033] ---- Initialize Nesterov Region: Top-level
[INFO GPL-0023] Placement target density:       0.7000
[INFO GPL-0024] Movable insts average area:      8.568 um^2
[INFO GPL-0025] Ideal bin area:                 12.240 um^2
[INFO GPL-0026] Ideal bin count:                  2057
[INFO GPL-0027] Total bin area:              25181.651 um^2
[INFO GPL-0028] Bin count (X, Y):          32 ,     32
[INFO GPL-0029] Bin size (W * H):       4.988 *  4.930 um
[INFO GPL-0030] Number of bins:                   1024
[INFO GPL-0007] ---- Execute Nesterov Global Placement.
[INFO GPL-0031] HPWL: Half-Perimeter Wirelength
Iteration | Overflow |     HPWL (um) |  HPWL(%) |   Penalty | Group
---------------------------------------------------------------
        0 |   0.9871 |  5.067019e+03 |   +0.00% |  1.56e-15 |      
       10 |   0.9685 |  4.739293e+03 |   -6.47% |  2.54e-15 |      
       20 |   0.9686 |  4.736841e+03 |   -0.05% |  4.14e-15 |      
       30 |   0.9686 |  4.737713e+03 |   +0.02% |  6.75e-15 |      
       40 |   0.9686 |  4.737197e+03 |   -0.01% |  1.10e-14 |      
       50 |   0.9686 |  4.736066e+03 |   -0.02% |  1.79e-14 |      
       60 |   0.9686 |  4.735912e+03 |   -0.00% |  2.92e-14 |      
       70 |   0.9685 |  4.736710e+03 |   +0.02% |  4.75e-14 |      
       80 |   0.9685 |  4.738283e+03 |   +0.03% |  7.74e-14 |      
       90 |   0.9685 |  4.740634e+03 |   +0.05% |  1.26e-13 |      
      100 |   0.9684 |  4.745291e+03 |   +0.10% |  2.05e-13 |      
      110 |   0.9684 |  4.754373e+03 |   +0.19% |  3.35e-13 |      
      120 |   0.9682 |  4.770138e+03 |   +0.33% |  5.45e-13 |      
      130 |   0.9680 |  4.798578e+03 |   +0.60% |  8.88e-13 |      
      140 |   0.9676 |  4.852283e+03 |   +1.12% |  1.45e-12 |      
      150 |   0.9662 |  4.964603e+03 |   +2.31% |  2.35e-12 |      
      160 |   0.9616 |  5.221878e+03 |   +5.18% |  3.84e-12 |      
      170 |   0.9569 |  5.701178e+03 |   +9.18% |  6.25e-12 |      
      180 |   0.9449 |  6.384858e+03 |  +11.99% |  1.02e-11 |      
      190 |   0.9265 |  7.046349e+03 |  +10.36% |  1.66e-11 |      
      200 |   0.9055 |  7.691506e+03 |   +9.16% |  2.70e-11 |      
      210 |   0.8812 |  8.430799e+03 |   +9.61% |  4.40e-11 |      
      220 |   0.8518 |  9.355397e+03 |  +10.97% |  7.16e-11 |      
      230 |   0.8211 |  1.041856e+04 |  +11.36% |  1.17e-10 |      
      240 |   0.7841 |  1.140621e+04 |   +9.48% |  1.90e-10 |      
      250 |   0.7451 |  1.242977e+04 |   +8.97% |  3.09e-10 |      
      260 |   0.7052 |  1.337410e+04 |   +7.60% |  5.04e-10 |      
      270 |   0.6577 |  1.440097e+04 |   +7.68% |  8.21e-10 |      
      280 |   0.6124 |  1.533307e+04 |   +6.47% |  1.34e-09 |      
      290 |   0.5630 |  1.611453e+04 |   +5.10% |  2.18e-09 |      
      300 |   0.5065 |  1.669529e+04 |   +3.60% |  3.55e-09 |      
      310 |   0.4575 |  1.699003e+04 |   +1.77% |  5.78e-09 |      
      320 |   0.4164 |  1.737706e+04 |   +2.28% |  9.41e-09 |      
      330 |   0.3532 |  1.749215e+04 |   +0.66% |  1.53e-08 |      
      340 |   0.3126 |  1.749517e+04 |   +0.02% |  2.30e-08 |      
      350 |   0.2765 |  1.773039e+04 |   +1.34% |  3.39e-08 |      
      360 |   0.2553 |  1.798743e+04 |   +1.45% |  5.00e-08 |      
      370 |   0.2242 |  1.802507e+04 |   +0.21% |  7.36e-08 |      
      380 |   0.2025 |  1.806830e+04 |   +0.24% |  1.08e-07 |      
      390 |   0.1800 |  1.808768e+04 |   +0.11% |  1.60e-07 |      
      400 |   0.1561 |  1.809788e+04 |   +0.06% |  2.35e-07 |      
      410 |   0.1338 |  1.810114e+04 |   +0.02% |  3.47e-07 |      
      420 |   0.1165 |  1.814420e+04 |   +0.24% |  5.11e-07 |      
      429 |   0.0996 |  1.818017e+04 |          |  7.53e-07 |      
---------------------------------------------------------------
[INFO GPL-1001] Global placement finished at iteration 429
[INFO GPL-1002] Placed Cell Area            11369.3568
[INFO GPL-1003] Available Free Area         25181.6512
[INFO GPL-1004] Minimum Feasible Density        0.4600 (cell_area / free_area)
[INFO GPL-1006]   Suggested Target Densities:
[INFO GPL-1007]     - For 90% usage of free space: 0.5017
[INFO GPL-1008]     - For 80% usage of free space: 0.5644
[INFO GPL-1009]     - For 50% usage of free space: 0.9030
[INFO GPL-1014] Final placement area: 11369.36 (+0.00%)
Placement Analysis
---------------------------------
total displacement       3015.3 u
average displacement        2.3 u
max displacement           12.3 u
original HPWL           18236.6 u
legalized HPWL          21484.5 u
delta HPWL                   18 %

[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4

Units:                1000
Number of layers:     13
Number of macros:     437
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.

Design:                   ring_modulator
Die area:                 ( 0 0 ) ( 200000 200000 )
Number of track patterns: 12
Number of DEF vias:       0
Number of components:     1327
Number of terminals:      50
Number of snets:          0
Number of nets:           1376

[INFO DRT-0167] List of default vias:
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: M2M3_PR
  Layer via3
    default via: M3M4_PR
  Layer via4
    default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
[INFO DRT-0164] Number of unique instances = 78.
[INFO DRT-0168] Init region query.
[INFO DRT-0024]   Complete FR_MASTERSLICE.
[INFO DRT-0024]   Complete licon.
[INFO DRT-0024]   Complete li1.
[INFO DRT-0024]   Complete mcon.
[INFO DRT-0024]   Complete met1.
[INFO DRT-0024]   Complete via.
[INFO DRT-0024]   Complete met2.
[INFO DRT-0024]   Complete via2.
[INFO DRT-0024]   Complete met3.
[INFO DRT-0024]   Complete via3.
[INFO DRT-0024]   Complete met4.
[INFO DRT-0024]   Complete via4.
[INFO DRT-0024]   Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] licon shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 34554.
[INFO DRT-0033] mcon shape region query size = 0.
[INFO DRT-0033] met1 shape region query size = 3922.
[INFO DRT-0033] via shape region query size = 0.
[INFO DRT-0033] met2 shape region query size = 0.
[INFO DRT-0033] via2 shape region query size = 0.
[INFO DRT-0033] met3 shape region query size = 50.
[INFO DRT-0033] via3 shape region query size = 0.
[INFO DRT-0033] met4 shape region query size = 0.
[INFO DRT-0033] via4 shape region query size = 0.
[INFO DRT-0033] met5 shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0078]   Complete 636 pins.
[INFO DRT-0081]   Complete 78 unique inst patterns.
[INFO DRT-0084]   Complete 673 groups.
#scanned instances     = 1327
#unique  instances     = 78
#stdCellGenAp          = 2357
#stdCellValidPlanarAp  = 8
#stdCellValidViaAp     = 1936
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 4494
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:27, elapsed time = 00:00:27, memory = 217.70 (MB), peak = 217.52 (MB)

[INFO DRT-0157] Number of guides:     8400

[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 28 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 28 STEP 6900 ;
[INFO DRT-0028]   Complete FR_MASTERSLICE.
[INFO DRT-0028]   Complete licon.
[INFO DRT-0028]   Complete li1.
[INFO DRT-0028]   Complete mcon.
[INFO DRT-0028]   Complete met1.
[INFO DRT-0028]   Complete via.
[INFO DRT-0028]   Complete met2.
[INFO DRT-0028]   Complete via2.
[INFO DRT-0028]   Complete met3.
[INFO DRT-0028]   Complete via3.
[INFO DRT-0028]   Complete met4.
[INFO DRT-0028]   Complete via4.
[INFO DRT-0028]   Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035]   Complete FR_MASTERSLICE (guide).
[INFO DRT-0035]   Complete licon (guide).
[INFO DRT-0035]   Complete li1 (guide).
[INFO DRT-0035]   Complete mcon (guide).
[INFO DRT-0035]   Complete met1 (guide).
[INFO DRT-0035]   Complete via (guide).
[INFO DRT-0035]   Complete met2 (guide).
[INFO DRT-0035]   Complete via2 (guide).
[INFO DRT-0035]   Complete met3 (guide).
[INFO DRT-0035]   Complete via3 (guide).
[INFO DRT-0035]   Complete met4 (guide).
[INFO DRT-0035]   Complete via4 (guide).
[INFO DRT-0035]   Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] licon guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 3222.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 2550.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 1154.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 55.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 0.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 218.50 (MB), peak = 218.45 (MB)
[INFO DRT-0245] skipped writing guide updates to database.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 4376 vertical wires in 1 frboxes and 2605 horizontal wires in 1 frboxes.
[INFO DRT-0186] Done with 351 vertical wires in 1 frboxes and 775 horizontal wires in 1 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 227.73 (MB), peak = 227.70 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 227.86 (MB), peak = 227.70 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 227.86 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:04, memory = 255.15 (MB).
    Completing 30% with 90 violations.
    elapsed time = 00:00:04, memory = 255.15 (MB).
    Completing 40% with 90 violations.
    elapsed time = 00:00:10, memory = 267.15 (MB).
    Completing 50% with 90 violations.
    elapsed time = 00:00:13, memory = 272.41 (MB).
    Completing 60% with 200 violations.
    elapsed time = 00:00:14, memory = 272.41 (MB).
    Completing 70% with 200 violations.
    elapsed time = 00:00:16, memory = 290.53 (MB).
    Completing 80% with 291 violations.
    elapsed time = 00:00:18, memory = 290.53 (MB).
    Completing 90% with 291 violations.
    elapsed time = 00:00:21, memory = 293.06 (MB).
    Completing 100% with 416 violations.
    elapsed time = 00:00:22, memory = 293.06 (MB).
[INFO DRT-0199]   Number of violations = 440.
Viol/Layer        mcon   met1   met2
Cut Spacing          2      0      0
Metal Spacing        0    109     13
Recheck              0     18      6
Short                0    277     15
[INFO DRT-0267] cpu time = 00:00:22, elapsed time = 00:00:22, memory = 593.11 (MB), peak = 592.81 (MB)
Total wire length = 26355 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 13630 um.
Total wire length on LAYER met2 = 11672 um.
Total wire length on LAYER met3 = 1051 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8782.
Up-via summary (total 8782):

-----------------------
 FR_MASTERSLICE       0
            li1    4538
           met1    4160
           met2      84
           met3       0
           met4       0
-----------------------
               8782


[INFO DRT-0195] Start 1st optimization iteration.
    Completing 10% with 440 violations.
    elapsed time = 00:00:00, memory = 593.11 (MB).
    Completing 20% with 440 violations.
    elapsed time = 00:00:02, memory = 593.11 (MB).
    Completing 30% with 440 violations.
    elapsed time = 00:00:02, memory = 593.11 (MB).
    Completing 40% with 412 violations.
    elapsed time = 00:00:02, memory = 593.11 (MB).
    Completing 50% with 412 violations.
    elapsed time = 00:00:07, memory = 593.11 (MB).
    Completing 60% with 412 violations.
    elapsed time = 00:00:07, memory = 593.11 (MB).
    Completing 70% with 352 violations.
    elapsed time = 00:00:08, memory = 593.11 (MB).
    Completing 80% with 352 violations.
    elapsed time = 00:00:10, memory = 593.11 (MB).
    Completing 90% with 310 violations.
    elapsed time = 00:00:11, memory = 593.11 (MB).
    Completing 100% with 229 violations.
    elapsed time = 00:00:20, memory = 593.18 (MB).
[INFO DRT-0199]   Number of violations = 229.
Viol/Layer        mcon   met1   met2
Cut Spacing          2      0      0
Metal Spacing        0     57      0
Short                0    167      3
[INFO DRT-0267] cpu time = 00:00:20, elapsed time = 00:00:20, memory = 593.23 (MB), peak = 592.96 (MB)
Total wire length = 26108 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 13469 um.
Total wire length on LAYER met2 = 11560 um.
Total wire length on LAYER met3 = 1079 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8718.
Up-via summary (total 8718):

-----------------------
 FR_MASTERSLICE       0
            li1    4533
           met1    4098
           met2      87
           met3       0
           met4       0
-----------------------
               8718


[INFO DRT-0195] Start 2nd optimization iteration.
    Completing 10% with 229 violations.
    elapsed time = 00:00:00, memory = 593.23 (MB).
    Completing 20% with 229 violations.
    elapsed time = 00:00:02, memory = 593.23 (MB).
    Completing 30% with 229 violations.
    elapsed time = 00:00:04, memory = 593.23 (MB).
    Completing 40% with 245 violations.
    elapsed time = 00:00:04, memory = 593.23 (MB).
    Completing 50% with 245 violations.
    elapsed time = 00:00:06, memory = 593.23 (MB).
    Completing 60% with 245 violations.
    elapsed time = 00:00:08, memory = 593.23 (MB).
    Completing 70% with 264 violations.
    elapsed time = 00:00:08, memory = 593.23 (MB).
    Completing 80% with 264 violations.
    elapsed time = 00:00:12, memory = 593.23 (MB).
    Completing 90% with 254 violations.
    elapsed time = 00:00:12, memory = 593.23 (MB).
    Completing 100% with 248 violations.
    elapsed time = 00:00:20, memory = 593.23 (MB).
[INFO DRT-0199]   Number of violations = 248.
Viol/Layer        mcon   met1   met2   met3
Cut Spacing          6      0      0      0
Metal Spacing        0     41      4      1
Short                0    186     10      0
[INFO DRT-0267] cpu time = 00:00:20, elapsed time = 00:00:20, memory = 593.38 (MB), peak = 593.12 (MB)
Total wire length = 26037 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 13411 um.
Total wire length on LAYER met2 = 11536 um.
Total wire length on LAYER met3 = 1089 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8736.
Up-via summary (total 8736):

-----------------------
 FR_MASTERSLICE       0
            li1    4533
           met1    4117
           met2      86
           met3       0
           met4       0
-----------------------
               8736


[INFO DRT-0195] Start 3rd optimization iteration.
    Completing 10% with 248 violations.
    elapsed time = 00:00:00, memory = 593.38 (MB).
    Completing 20% with 248 violations.
    elapsed time = 00:00:01, memory = 593.38 (MB).
    Completing 30% with 211 violations.
    elapsed time = 00:00:01, memory = 593.38 (MB).
    Completing 40% with 211 violations.
    elapsed time = 00:00:03, memory = 593.38 (MB).
    Completing 50% with 211 violations.
    elapsed time = 00:00:04, memory = 593.38 (MB).
    Completing 60% with 108 violations.
    elapsed time = 00:00:05, memory = 593.38 (MB).
    Completing 70% with 108 violations.
    elapsed time = 00:00:08, memory = 593.38 (MB).
    Completing 80% with 81 violations.
    elapsed time = 00:00:08, memory = 593.38 (MB).
    Completing 90% with 81 violations.
    elapsed time = 00:00:09, memory = 593.38 (MB).
    Completing 100% with 12 violations.
    elapsed time = 00:00:10, memory = 593.38 (MB).
[INFO DRT-0199]   Number of violations = 12.
Viol/Layer        met1
Metal Spacing        2
Short               10
[INFO DRT-0267] cpu time = 00:00:10, elapsed time = 00:00:10, memory = 593.38 (MB), peak = 593.12 (MB)
Total wire length = 25936 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 12540 um.
Total wire length on LAYER met2 = 11494 um.
Total wire length on LAYER met3 = 1901 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8863.
Up-via summary (total 8863):

-----------------------
 FR_MASTERSLICE       0
            li1    4535
           met1    4132
           met2     196
           met3       0
           met4       0
-----------------------
               8863


[INFO DRT-0195] Start 4th guides tiles iteration.
    Completing 30% with 12 violations.
    elapsed time = 00:00:00, memory = 593.38 (MB).
    Completing 60% with 12 violations.
    elapsed time = 00:00:00, memory = 593.38 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 593.38 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 593.38 (MB), peak = 593.12 (MB)
Total wire length = 25929 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 12537 um.
Total wire length on LAYER met2 = 11492 um.
Total wire length on LAYER met3 = 1899 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8860.
Up-via summary (total 8860):

-----------------------
 FR_MASTERSLICE       0
            li1    4535
           met1    4129
           met2     196
           met3       0
           met4       0
-----------------------
               8860


[WARNING DRT-0290] Warning: no DRC report specified, skipped writing DRC report
[INFO DRT-0198] Complete detail routing.
Total wire length = 25929 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 12537 um.
Total wire length on LAYER met2 = 11492 um.
Total wire length on LAYER met3 = 1899 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 8860.
Up-via summary (total 8860):

-----------------------
 FR_MASTERSLICE       0
            li1    4535
           met1    4129
           met2     196
           met3       0
           met4       0
-----------------------
               8860


[INFO DRT-0267] cpu time = 00:01:14, elapsed time = 00:01:14, memory = 593.43 (MB), peak = 593.30 (MB)

[INFO DRT-0180] Post processing.
Design area 10793 um^2 43% utilization.
Startpoint: carrier_in[5] (input port clocked by clk)
Endpoint: _2607_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   5.00    5.00 ^ input external delay
   0.00    5.00 ^ carrier_in[5] (in)
   0.13    5.13 ^ _1564_/X (sky130_fd_sc_hd__and2_0)
   0.44    5.57 v _1639_/X (sky130_fd_sc_hd__xor3_1)
   0.39    5.96 v _1643_/X (sky130_fd_sc_hd__xor3_1)
   0.10    6.06 ^ _1644_/Y (sky130_fd_sc_hd__nand2_1)
   0.41    6.47 v _1663_/X (sky130_fd_sc_hd__xnor3_1)
   0.37    6.84 v _1664_/X (sky130_fd_sc_hd__maj3_1)
   0.38    7.22 v _1750_/X (sky130_fd_sc_hd__xor3_1)
   0.11    7.33 ^ _1751_/Y (sky130_fd_sc_hd__o22ai_1)
   0.09    7.43 ^ _1752_/X (sky130_fd_sc_hd__a21o_1)
   0.05    7.48 v _1756_/Y (sky130_fd_sc_hd__a21oi_1)
   0.34    7.82 v _1757_/X (sky130_fd_sc_hd__maj3_1)
   0.20    8.02 ^ _1761_/Y (sky130_fd_sc_hd__o221ai_1)
   0.16    8.18 ^ _1764_/X (sky130_fd_sc_hd__a211o_1)
   0.06    8.25 v _1910_/Y (sky130_fd_sc_hd__a211oi_1)
   0.20    8.45 ^ _2046_/Y (sky130_fd_sc_hd__o211ai_1)
   0.11    8.56 v _2170_/Y (sky130_fd_sc_hd__a211oi_1)
   0.22    8.78 v _2226_/X (sky130_fd_sc_hd__o21a_1)
   0.36    9.14 ^ _2337_/Y (sky130_fd_sc_hd__o311ai_0)
   0.16    9.30 v _2388_/Y (sky130_fd_sc_hd__a21boi_0)
   0.22    9.52 ^ _2432_/Y (sky130_fd_sc_hd__o21ai_0)
   0.12    9.65 v _2482_/Y (sky130_fd_sc_hd__a21oi_1)
   0.18    9.83 ^ _2524_/Y (sky130_fd_sc_hd__o21ai_0)
   0.10    9.93 v _2527_/Y (sky130_fd_sc_hd__nand2_1)
   0.36   10.29 v _2556_/X (sky130_fd_sc_hd__maj3_1)
   0.13   10.42 v _2575_/Y (sky130_fd_sc_hd__xnor2_1)
   0.00   10.42 v _2607_/D (sky130_fd_sc_hd__dfrtp_1)
          10.42   data arrival time

  50.00   50.00   clock clk (rise edge)
   0.00   50.00   clock network delay (ideal)
  -0.50   49.50   clock uncertainty
   0.00   49.50   clock reconvergence pessimism
          49.50 ^ _2607_/CLK (sky130_fd_sc_hd__dfrtp_1)
  -0.12   49.38   library setup time
          49.38   data required time
---------------------------------------------------------
          49.38   data required time
         -10.42   data arrival time
---------------------------------------------------------
          38.96   slack (MET)


Group                  Internal  Switching    Leakage      Total
                          Power      Power      Power      Power (Watts)
----------------------------------------------------------------
Sequential             5.43e-05   1.03e-06   3.68e-10   5.53e-05   6.7%
Combinational          4.21e-04   3.45e-04   4.01e-09   7.66e-04  93.3%
Clock                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
----------------------------------------------------------------
Total                  4.76e-04   3.46e-04   4.38e-09   8.22e-04 100.0%
                          57.9%      42.1%       0.0%
openroad> 

Design area 10793 um^2 43% utilization.
Startpoint: carrier_in[5] (input port clocked by clk)
Endpoint: _2607_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   5.00    5.00 ^ input external delay
   0.00    5.00 ^ carrier_in[5] (in)
   0.13    5.13 ^ _1564_/X (sky130_fd_sc_hd__and2_0)
   0.44    5.57 v _1639_/X (sky130_fd_sc_hd__xor3_1)
   0.39    5.96 v _1643_/X (sky130_fd_sc_hd__xor3_1)
   0.10    6.06 ^ _1644_/Y (sky130_fd_sc_hd__nand2_1)
   0.41    6.47 v _1663_/X (sky130_fd_sc_hd__xnor3_1)
   0.37    6.84 v _1664_/X (sky130_fd_sc_hd__maj3_1)
   0.38    7.22 v _1750_/X (sky130_fd_sc_hd__xor3_1)
   0.11    7.33 ^ _1751_/Y (sky130_fd_sc_hd__o22ai_1)
   0.09    7.43 ^ _1752_/X (sky130_fd_sc_hd__a21o_1)
   0.05    7.48 v _1756_/Y (sky130_fd_sc_hd__a21oi_1)
   0.34    7.82 v _1757_/X (sky130_fd_sc_hd__maj3_1)
   0.20    8.02 ^ _1761_/Y (sky130_fd_sc_hd__o221ai_1)
   0.16    8.18 ^ _1764_/X (sky130_fd_sc_hd__a211o_1)
   0.06    8.25 v _1910_/Y (sky130_fd_sc_hd__a211oi_1)
   0.20    8.45 ^ _2046_/Y (sky130_fd_sc_hd__o211ai_1)
   0.11    8.56 v _2170_/Y (sky130_fd_sc_hd__a211oi_1)
   0.22    8.78 v _2226_/X (sky130_fd_sc_hd__o21a_1)
   0.36    9.14 ^ _2337_/Y (sky130_fd_sc_hd__o311ai_0)
   0.16    9.30 v _2388_/Y (sky130_fd_sc_hd__a21boi_0)
   0.22    9.52 ^ _2432_/Y (sky130_fd_sc_hd__o21ai_0)
   0.12    9.65 v _2482_/Y (sky130_fd_sc_hd__a21oi_1)
   0.18    9.83 ^ _2524_/Y (sky130_fd_sc_hd__o21ai_0)
   0.10    9.93 v _2527_/Y (sky130_fd_sc_hd__nand2_1)
   0.36   10.29 v _2556_/X (sky130_fd_sc_hd__maj3_1)
   0.13   10.42 v _2575_/Y (sky130_fd_sc_hd__xnor2_1)
   0.00   10.42 v _2607_/D (sky130_fd_sc_hd__dfrtp_1)
          10.42   data arrival time

  50.00   50.00   clock clk (rise edge)
   0.00   50.00   clock network delay (ideal)
  -0.50   49.50   clock uncertainty
   0.00   49.50   clock reconvergence pessimism
          49.50 ^ _2607_/CLK (sky130_fd_sc_hd__dfrtp_1)
  -0.12   49.38   library setup time
          49.38   data required time
---------------------------------------------------------
          49.38   data required time
         -10.42   data arrival time
---------------------------------------------------------
          38.96   slack (MET)

At 20 MHz, the clock period is 50 ns, so the design has much more time to propagate signals than it would at higher frequencies. In this timing report, the data path starts from the input carrier_in[5] and ends at the flip-flop _2607_, both referenced to the clk domain. The total data arrival time is 10.42 ns, which means the signal only needs about 10.42 ns to travel through the combinational logic and reach the destination register.

The data required time is 49.38 ns. This value comes from the 50 ns clock period, minus 0.5 ns of clock uncertainty, and minus 0.12 ns of setup time required by the destination flip-flop. Since the signal arrives at 10.42 ns and it is only required before 49.38 ns, the design still has a large positive margin.

The reported slack is 38.96 ns (MET), which means the timing constraint is satisfied with a lot of margin. In other words, at 20 MHz the design is comfortably meeting timing, because the critical path delay is much smaller than the available clock period. This indicates that the circuit is running slowly enough for the current implementation, and timing is not a problem at this frequency.

The area report also shows a design area of 10793 µm² with 43% utilization, which means the layout is not heavily congested and still has free space for routing and placement. Overall, these results show that the design is relatively relaxed at 20 MHz, with plenty of timing headroom.

Power Analysis

Group	Internal Power	Switching Power	Leakage Power	Total Power (W)	Share
Sequential	5.43e-05	1.03e-06	3.68e-10	5.53e-05	6.7%
Combinational	4.21e-04	3.45e-04	4.01e-09	7.66e-04	93.3%
Clock	0.00e+00	0.00e+00	0.00e+00	0.00e+00	0.0%
Macro	0.00e+00	0.00e+00	0.00e+00	0.00e+00	0.0%
Pad	0.00e+00	0.00e+00	0.00e+00	0.00e+00	0.0%
Total	4.76e-04	3.46e-04	4.38e-09	8.22e-04	100.0%
Breakdown	57.9%	42.1%	0.0%

In OpenROAD, the power report shows that my design has a total power consumption of 8.22e-04 W, which is about 0.822 mW. Most of this power is consumed by the combinational part of the circuit, which accounts for 7.66e-04 W, or 93.3% of the total power. In comparison, the sequential logic only contributes 5.53e-05 W, which is 6.7%. There is no reported power contribution from the clock network, macros, or pads in this result.

When I look at the power components, I can see that internal power is the largest contribution, with 4.76e-04 W, corresponding to 57.9% of the total. Switching power is also significant, with 3.46e-04 W, or 42.1%, while leakage power is almost negligible at 4.38e-09 W. This means that the power consumption of my design is mainly dominated by active logic operation, especially in the combinational cells, rather than by static leakage.

From this OpenROAD power analysis, I can conclude that my design has a relatively low overall power consumption, below 1 mW, and that the main source of power usage comes from the combinational logic. If I wanted to optimize the design further, I would mainly focus on reducing switching activity or simplifying the combinational paths.

Generate GDS

GDS, or GDSII, is the standard file format used to describe the final physical layout of an integrated circuit. It contains the geometric shapes, layers, and hierarchical structures that represent the chip layout, including metal layers, vias, diffusion regions, and other mask information needed for fabrication. In the digital design flow, the GDS file is one of the final outputs, because it represents the layout that can be reviewed in tools such as KLayout and later used for manufacturing.

To generate the GDS file, I will base my work on the Makefiles provided in the example designs and then adapt them to my own project. This is a practical way to understand how the OpenROAD flow is organized and to build a working flow for my circuit. The GDS file is the final layout description of the chip, containing the physical geometry of the design and the information needed to visualize and fabricate it.

# =============================================================================
# Ring Modulator - Build Automation
# =============================================================================

SHELL := /bin/bash

# Tools
IVERILOG := iverilog
VVP := vvp
VERILATOR := verilator
YOSYS := yosys
OPENROAD := openroad
KLAYOUT := klayout
MAGIC := magic

# Common options
IVERILOG_FLAGS := -Wall -g2012
VERILATOR_FLAGS := --lint-only -Wall

# Paths
LIB := lib
FLOW := flow

# =============================================================================
# PDK Detection
# =============================================================================

ifndef PDK_ROOT
  ifneq (,$(wildcard /foss/pdks/sky130A))
    PDK_ROOT := /foss/pdks
  else ifneq (,$(wildcard $(HOME)/pdks/sky130A))
    PDK_ROOT := $(HOME)/pdks
  else ifneq (,$(wildcard /opt/pdks/sky130A))
    PDK_ROOT := /opt/pdks
  endif
endif

define check_pdk
    @if [ -z "$(PDK_ROOT)" ]; then \
        echo "ERROR: PDK_ROOT is not set and Sky130 PDK not found."; \
        echo ""; \
        echo "To run the ASIC flow, you need the Sky130 PDK."; \
        echo "Use IIC-OSIC-TOOLS Docker or export PDK_ROOT manually."; \
        exit 1; \
    fi
endef

# =============================================================================
# Project definition
# =============================================================================

RING_TOP := ring_modulator
RING_DIR := ring_modulator
RING_SRC := $(RING_DIR)/ring_modulator.v
RING_BUILD := $(RING_DIR)/build

# Optional testbench
RING_TB := $(RING_DIR)/ring_modulator_tb.v

# Standard cell library GDS path
LIB_DIR := $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd

# =============================================================================
# Simulation
# =============================================================================

.PHONY: sim-ring

sim-ring: $(RING_DIR)/ring_modulator.vvp
    $(VVP) $<

$(RING_DIR)/ring_modulator.vvp: $(RING_SRC) $(RING_TB)
    $(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^

# =============================================================================
# Lint
# =============================================================================

.PHONY: lint-ring

lint-ring:
    $(VERILATOR) $(VERILATOR_FLAGS) -I$(LIB) $(RING_SRC)

# =============================================================================
# Quick synthesis (no PDK required)
# =============================================================================

.PHONY: synth-ring

synth-ring:
    $(YOSYS) -p "read_verilog -I$(LIB) $(RING_SRC); synth -top $(RING_TOP); stat"

# =============================================================================
# Sky130 synthesis
# =============================================================================

.PHONY: sky130-ring

sky130-ring: $(RING_BUILD)/$(RING_TOP)_synth.v

$(RING_BUILD)/$(RING_TOP)_synth.v: $(RING_SRC)
    $(call check_pdk)
    @mkdir -p $(RING_BUILD)
    cd $(RING_DIR) && \
        TOP=$(RING_TOP) \
        VERILOG="ring_modulator.v" \
        OUT_DIR=build \
        $(YOSYS) -c ../$(FLOW)/synth.tcl

# =============================================================================
# Place & Route
# =============================================================================

.PHONY: pnr-ring

pnr-ring: $(RING_BUILD)/$(RING_TOP).def

$(RING_BUILD)/$(RING_TOP).def: $(RING_BUILD)/$(RING_TOP)_synth.v
    cd $(RING_DIR) && \
        TOP=$(RING_TOP) \
        OUT_DIR=build \
        $(OPENROAD) -exit ../$(FLOW)/pnr.tcl

# =============================================================================
# GDS generation
# =============================================================================

.PHONY: gds-ring

gds-ring: $(RING_BUILD)/$(RING_TOP).gds

$(RING_BUILD)/$(RING_TOP).gds: $(RING_BUILD)/$(RING_TOP).def
    cd $(RING_DIR) && \
        $(KLAYOUT) -zz -r ../$(FLOW)/def2gds.rb \
        -rd def_file=build/$(RING_TOP).def \
        -rd gds_file=build/$(RING_TOP).gds

# =============================================================================
# Full build
# =============================================================================

.PHONY: build-ring

build-ring: gds-ring
    @echo "Ring Modulator build complete: $(RING_BUILD)/$(RING_TOP).gds"

# =============================================================================
# View layout
# =============================================================================

.PHONY: view-ring view-ring-gds

# View DEF with tech + std cell GDS
view-ring: $(RING_BUILD)/$(RING_TOP).def
    $(call check_pdk)
    $(KLAYOUT) -n $(PDK_ROOT)/sky130A/libs.tech/klayout/tech/sky130A.lyt \
        $(LIB_DIR)/gds/sky130_fd_sc_hd.gds $<

# View final GDS directly
view-ring-gds: $(RING_BUILD)/$(RING_TOP).gds
    $(call check_pdk)
    $(KLAYOUT) -n $(PDK_ROOT)/sky130A/libs.tech/klayout/tech/sky130A.lyt \
        $<

# =============================================================================
# Reports
# =============================================================================

.PHONY: report-ring

report-ring:
    @echo "=== Ring Modulator Reports ==="
    @cat $(RING_BUILD)/$(RING_TOP)_timing.rpt 2>/dev/null || echo "Run 'make pnr-ring' first"
    @cat $(RING_BUILD)/$(RING_TOP)_area.rpt 2>/dev/null || true

# =============================================================================
# Environment check
# =============================================================================

.PHONY: check-env

check-env:
    @echo "=== Environment Check ==="
    @echo ""
    @echo "PDK_ROOT: $(PDK_ROOT)"
    @if [ -n "$(PDK_ROOT)" ] && [ -d "$(PDK_ROOT)/sky130A" ]; then \
        echo "  Status: OK (Sky130 PDK found)"; \
    else \
        echo "  Status: NOT FOUND"; \
    fi
    @echo ""
    @echo "Tools:"
    @which $(YOSYS) > /dev/null 2>&1 && echo "  yosys:    OK ($(shell which $(YOSYS)))" || echo "  yosys:    NOT FOUND"
    @which $(OPENROAD) > /dev/null 2>&1 && echo "  openroad: OK ($(shell which $(OPENROAD)))" || echo "  openroad: NOT FOUND"
    @which $(KLAYOUT) > /dev/null 2>&1 && echo "  klayout:  OK ($(shell which $(KLAYOUT)))" || echo "  klayout:  NOT FOUND"
    @which $(IVERILOG) > /dev/null 2>&1 && echo "  iverilog: OK ($(shell which $(IVERILOG)))" || echo "  iverilog: NOT FOUND"
    @which $(VERILATOR) > /dev/null 2>&1 && echo "  verilator: OK ($(shell which $(VERILATOR)))" || echo "  verilator: NOT FOUND"

# =============================================================================
# Clean
# =============================================================================

.PHONY: clean clean-sim clean-build

clean-sim:
    rm -f $(RING_DIR)/*.vvp $(RING_DIR)/*.vcd
    @echo "Cleaned simulation files."

clean-build:
    rm -rf $(RING_BUILD)
    @echo "Cleaned build directory."

clean: clean-sim clean-build
    @echo "All cleaned."

# =============================================================================
# Help
# =============================================================================

.PHONY: help

help:
    @echo "Ring Modulator Makefile"
    @echo ""
    @echo "Setup:"
    @echo "  make check-env     - Check tools and PDK"
    @echo ""
    @echo "Simulation:"
    @echo "  make sim-ring      - Run simulation"
    @echo ""
    @echo "Lint:"
    @echo "  make lint-ring     - Lint with Verilator"
    @echo ""
    @echo "Quick synthesis:"
    @echo "  make synth-ring    - Synthesize and show stats"
    @echo ""
    @echo "ASIC flow:"
    @echo "  make sky130-ring   - Synthesize to Sky130 cells"
    @echo "  make pnr-ring      - Place and route"
    @echo "  make gds-ring      - Generate GDS"
    @echo "  make build-ring    - Full flow"
    @echo ""
    @echo "View:"
    @echo "  make view-ring     - View DEF in KLayout"
    @echo "  make view-ring-gds - View final GDS in KLayout"
    @echo ""
    @echo "Reports:"
    @echo "  make report-ring   - Show timing/area reports"
    @echo ""
    @echo "Cleanup:"
    @echo "  make clean         - Remove generated files"

To run the Makefile, I first need to copy the lib and flow folders from the examples into my project directory. These folders contain the support files and scripts required for synthesis, place and route, and GDS generation. Once they are in place, I can run the flow from the terminal with make build-ring.

Terminal Full flow

```bash /foss/designs/ring_modulator > make build-ring cd ring_modulator && \ TOP=ring_modulator \ OUT_DIR=build \ openroad -exit ../flow/pnr.tcl OpenROAD 26Q1-990-g15af3a5c0 Features included (+) or not (-): +GPU +GUI +Python This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. ============================================ Place & Route: ring_modulator Build dir: build PDK: /foss/pdks ============================================ [INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef, created 14 layers, 25 vias [WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later. The NOWIREEXTENSIONATPIN statement will be ignored. See file /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef at line 2. [INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells [WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later. The NOWIREEXTENSIONATPIN statement will be ignored. See file /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef at line 2. [INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef, created 8 library cells [WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed. Initializing floorplan... [INFO IFP-0107] Defining die area using utilization: 40.00% and aspect ratio: 1. [WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.060, 5.440). [INFO IFP-0001] Added 60 rows of 356 site unithd. [INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 174.260 174.260 ) um [INFO IFP-0101] Core BBox: ( 5.060 5.440 ) ( 168.820 168.640 ) um [INFO IFP-0102] Core area: 26725.632 um^2 [INFO IFP-0103] Total instances area: 10792.851 um^2 [INFO IFP-0104] Effective utilization: 0.404 [INFO IFP-0105] Number of instances: 1327 Placing I/O pins... Found 0 macro blocks. Using 2 tracks default min distance between IO pins. [INFO PPL-0001] Number of available slots 624 [INFO PPL-0002] Number of I/O 50 [INFO PPL-0003] Number of I/O w/sink 50 [INFO PPL-0004] Number of I/O w/o sink 0 [INFO PPL-0005] Slots per section 200 [INFO PPL-0008] Successfully assigned pins to sections. [INFO PPL-0012] I/O nets HPWL: 5206.50 um. Building power grid... [INFO PDN-0001] Inserting grid: core_grid Running placement... [INFO GPL-0001] ---- Initialize GPL Main Data Structures [INFO GPL-0002] DBU: 1000 [INFO GPL-0003] SiteSize: ( 0.460 2.720 ) um [INFO GPL-0004] CoreBBox: ( 5.060 5.440 ) ( 168.820 168.640 ) um [INFO GPL-0036] Movable instances area: 17434.221 um^2 [INFO GPL-0037] Total instances area: 17434.221 um^2 [INFO GPL-0035] Pin density area adjust: 1265.499 um^2 [INFO GPL-0032] ---- Initialize Region: Top-level [INFO GPL-0006] Number of instances: 1327 [INFO GPL-0007] Movable instances: 1327 [INFO GPL-0008] Fixed instances: 0 [INFO GPL-0009] Dummy instances: 0 [INFO GPL-0010] Number of nets: 1376 [INFO GPL-0011] Number of pins: 4544 [INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 174.260 174.260 ) um [INFO GPL-0013] Core BBox: ( 5.060 5.440 ) ( 168.820 168.640 ) um [INFO GPL-0016] Core area: 26725.632 um^2 [INFO GPL-0014] Region name: top-level. [INFO GPL-0015] Region area: 26725.632 um^2 [INFO GPL-0017] Fixed instances area: 0.000 um^2 [INFO GPL-0018] Movable instances area: 18699.720 um^2 [INFO GPL-0019] Utilization: 69.969 % [INFO GPL-0020] Standard cells area: 18699.720 um^2 [INFO GPL-0021] Large instances area: 0.000 um^2 [INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement. [INFO GPL-0051] Source of initial instance position counters: Odb location = 0 Core center = 1327 Region center = 0 [InitialPlace] Iter: 1 conjugate gradient residual: 0.00000010 HPWL: 14059080 [InitialPlace] Iter: 2 conjugate gradient residual: 0.00000012 HPWL: 11229104 [InitialPlace] Iter: 3 conjugate gradient residual: 0.00000009 HPWL: 11137333 [InitialPlace] Iter: 4 conjugate gradient residual: 0.00000010 HPWL: 11133147 [InitialPlace] Iter: 5 conjugate gradient residual: 0.00000010 HPWL: 11127106 [INFO GPL-0033] ---- Initialize Nesterov Region: Top-level [INFO GPL-0023] Placement target density: 0.7000 [INFO GPL-0024] Movable insts average area: 14.092 um^2 [INFO GPL-0025] Ideal bin area: 20.131 um^2 [INFO GPL-0026] Ideal bin count: 1327 [INFO GPL-0027] Total bin area: 26725.632 um^2 [INFO GPL-0028] Bin count (X, Y): 32 , 32 [INFO GPL-0029] Bin size (W * H): 5.117 * 5.100 um [INFO GPL-0030] Number of bins: 1024 [INFO GPL-0007] ---- Execute Nesterov Global Placement. [INFO GPL-0031] HPWL: Half-Perimeter Wirelength Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group --------------------------------------------------------------- 0 | 0.9909 | 4.437136e+03 | +0.00% | 6.47e-16 | 10 | 0.9818 | 4.040570e+03 | -8.94% | 1.05e-15 | 20 | 0.9818 | 4.018020e+03 | -0.56% | 1.72e-15 | 30 | 0.9818 | 4.016836e+03 | -0.03% | 2.80e-15 | 40 | 0.9818 | 4.018306e+03 | +0.04% | 4.56e-15 | 50 | 0.9818 | 4.018810e+03 | +0.01% | 7.42e-15 | 60 | 0.9818 | 4.018804e+03 | -0.00% | 1.21e-14 | 70 | 0.9818 | 4.018718e+03 | -0.00% | 1.97e-14 | 80 | 0.9818 | 4.018838e+03 | +0.00% | 3.21e-14 | 90 | 0.9818 | 4.019465e+03 | +0.02% | 5.22e-14 | 100 | 0.9818 | 4.021197e+03 | +0.04% | 8.51e-14 | 110 | 0.9817 | 4.024455e+03 | +0.08% | 1.39e-13 | 120 | 0.9816 | 4.032626e+03 | +0.20% | 2.26e-13 | 130 | 0.9814 | 4.055615e+03 | +0.57% | 3.68e-13 | 140 | 0.9806 | 4.118963e+03 | +1.56% | 5.99e-13 | 150 | 0.9795 | 4.286037e+03 | +4.06% | 9.76e-13 | 160 | 0.9763 | 4.693326e+03 | +9.50% | 1.59e-12 | 170 | 0.9688 | 5.410810e+03 | +15.29% | 2.59e-12 | 180 | 0.9578 | 6.239297e+03 | +15.31% | 4.22e-12 | 190 | 0.9436 | 7.050881e+03 | +13.01% | 6.87e-12 | 200 | 0.9283 | 7.929782e+03 | +12.47% | 1.12e-11 | 210 | 0.9030 | 9.096304e+03 | +14.71% | 1.82e-11 | 220 | 0.8758 | 1.043128e+04 | +14.68% | 2.97e-11 | 230 | 0.8420 | 1.175506e+04 | +12.69% | 4.83e-11 | 240 | 0.8064 | 1.312458e+04 | +11.65% | 7.87e-11 | 250 | 0.7661 | 1.446914e+04 | +10.24% | 1.28e-10 | 260 | 0.7270 | 1.558611e+04 | +7.72% | 2.09e-10 | 270 | 0.6839 | 1.663254e+04 | +6.71% | 3.40e-10 | 280 | 0.6395 | 1.767313e+04 | +6.26% | 5.54e-10 | 290 | 0.5971 | 1.872833e+04 | +5.97% | 9.02e-10 | 300 | 0.5428 | 1.965606e+04 | +4.95% | 1.47e-09 | 310 | 0.4912 | 2.019567e+04 | +2.75% | 2.39e-09 | 320 | 0.4387 | 2.067043e+04 | +2.35% | 3.90e-09 | 330 | 0.3911 | 2.123655e+04 | +2.74% | 6.35e-09 | 340 | 0.3496 | 2.171435e+04 | +2.25% | 1.03e-08 | 350 | 0.3193 | 2.205448e+04 | +1.57% | 1.54e-08 | 360 | 0.2933 | 2.229548e+04 | +1.09% | 2.27e-08 | 370 | 0.2717 | 2.258966e+04 | +1.32% | 3.34e-08 | 380 | 0.2502 | 2.276465e+04 | +0.77% | 4.92e-08 | 390 | 0.2277 | 2.283762e+04 | +0.32% | 7.25e-08 | 400 | 0.2056 | 2.293725e+04 | +0.44% | 1.07e-07 | 410 | 0.1851 | 2.304580e+04 | +0.47% | 1.57e-07 | 420 | 0.1656 | 2.317916e+04 | +0.58% | 2.32e-07 | 430 | 0.1494 | 2.328249e+04 | +0.45% | 3.41e-07 | 440 | 0.1306 | 2.338132e+04 | +0.42% | 5.03e-07 | 450 | 0.1100 | 2.347467e+04 | +0.40% | 7.40e-07 | 456 | 0.0990 | 2.351382e+04 | | 9.71e-07 | --------------------------------------------------------------- [INFO GPL-1001] Global placement finished at iteration 456 [INFO GPL-1002] Placed Cell Area 18699.7202 [INFO GPL-1003] Available Free Area 26725.6320 [INFO GPL-1004] Minimum Feasible Density 0.7000 (cell_area / free_area) [INFO GPL-1006] Suggested Target Densities: [INFO GPL-1007] - For 90% usage of free space: 0.7774 [INFO GPL-1008] - For 80% usage of free space: 0.8746 [INFO GPL-1014] Final placement area: 18699.72 (+0.00%) Placement Analysis --------------------------------- total displacement 2261.7 u average displacement 1.7 u max displacement 5.3 u original HPWL 23563.4 u legalized HPWL 25704.3 u delta HPWL 9 % Running clock tree synthesis... [WARNING EST-0027] no estimated parasitics. Using wire load models. Iteration | Area | Resized | Buffers | Nets repaired | Remaining --------------------------------------------------------------------- 0 | +0.0% | 0 | 0 | 0 | 1361 final | +0.0% | 0 | 0 | 0 | 0 --------------------------------------------------------------------- [INFO CTS-0050] Root buffer is sky130_fd_sc_hd__clkbuf_16. [INFO CTS-0051] Sink buffer is sky130_fd_sc_hd__clkbuf_4. [INFO CTS-0052] The following clock buffers will be used for CTS: sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_16 [INFO CTS-0049] Characterization buffer is sky130_fd_sc_hd__clkbuf_16. [INFO CTS-0007] Net "clk" found for clock "clk". [INFO CTS-0010] Clock net "clk" has 32 sinks. [INFO CTS-0008] TritonCTS found 1 clock nets. [INFO CTS-0097] Characterization used 3 buffer(s) types. [INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used. [INFO CTS-0027] Generating H-Tree topology for net clk. [INFO CTS-0028] Total number of sinks: 32. [INFO CTS-0090] Sinks will be clustered based on buffer max cap. [INFO CTS-0030] Number of static layers: 0. [INFO CTS-0020] Wire segment unit: 13600 dbu (13 um). [INFO CTS-0023] Original sink region: [(5785, 36780), (36145, 167340)]. [INFO CTS-0024] Normalized sink region: [(0.425368, 2.70441), (2.65772, 12.3044)]. [INFO CTS-0025] Width: 2.2324. [INFO CTS-0026] Height: 9.6000. Level 1 Direction: Vertical Sinks per sub-region: 16 Sub-region size: 2.2324 X 4.8000 [INFO CTS-0034] Segment length (rounded): 2. Level 2 Direction: Horizontal Sinks per sub-region: 8 Sub-region size: 1.1162 X 4.8000 [INFO CTS-0034] Segment length (rounded): 1. [INFO CTS-0032] Stop criterion found. Max number of sinks is 15. [INFO CTS-0035] Number of sinks covered: 32. [INFO CTS-0018] Created 5 clock buffers. [INFO CTS-0012] Minimum number of buffers in the clock path: 2. [INFO CTS-0013] Maximum number of buffers in the clock path: 2. [INFO CTS-0015] Created 5 clock nets. [INFO CTS-0016] Fanout distribution for the current clock = 6:1, 7:2, 12:1.. [INFO CTS-0017] Max level of the clock tree: 2. [INFO CTS-0098] Clock net "clk" [INFO CTS-0099] Sinks 35 [INFO CTS-0100] Leaf buffers 0 [INFO CTS-0101] Average sink wire length 93.14 um [INFO CTS-0102] Path depth 2 - 2 [INFO CTS-0207] Dummy loads inserted 3 Placement Analysis --------------------------------- total displacement 38.0 u average displacement 0.0 u max displacement 4.0 u original HPWL 25849.2 u legalized HPWL 25873.9 u delta HPWL 0 % Running routing... [INFO DRT-0149] Reading tech and libs. [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2 [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3 [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 [WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4 Units: 1000 Number of layers: 13 Number of macros: 445 Number of vias: 29 Number of viarulegen: 25 [INFO DRT-0150] Reading design. Design: ring_modulator Die area: ( 0 0 ) ( 174260 174260 ) Number of track patterns: 12 Number of DEF vias: 0 Number of components: 1335 Number of terminals: 52 Number of snets: 2 Number of nets: 1381 [INFO DRT-0167] List of default vias: Layer via default via: M1M2_PR Layer via2 default via: M2M3_PR Layer via3 default via: M3M4_PR Layer via4 default via: M4M5_PR [INFO DRT-0162] Library cell analysis. [INFO DRT-0163] Instance analysis. [INFO DRT-0164] Number of unique instances = 82. [INFO DRT-0168] Init region query. [INFO DRT-0024] Complete FR_MASTERSLICE. [INFO DRT-0024] Complete licon. [INFO DRT-0024] Complete li1. [INFO DRT-0024] Complete mcon. [INFO DRT-0024] Complete met1. [INFO DRT-0024] Complete via. [INFO DRT-0024] Complete met2. [INFO DRT-0024] Complete via2. [INFO DRT-0024] Complete met3. [INFO DRT-0024] Complete via3. [INFO DRT-0024] Complete met4. [INFO DRT-0024] Complete via4. [INFO DRT-0024] Complete met5. [INFO DRT-0033] FR_MASTERSLICE shape region query size = 0. [INFO DRT-0033] licon shape region query size = 0. [INFO DRT-0033] li1 shape region query size = 34849. [INFO DRT-0033] mcon shape region query size = 0. [INFO DRT-0033] met1 shape region query size = 4213. [INFO DRT-0033] via shape region query size = 1070. [INFO DRT-0033] met2 shape region query size = 642. [INFO DRT-0033] via2 shape region query size = 856. [INFO DRT-0033] met3 shape region query size = 692. [INFO DRT-0033] via3 shape region query size = 856. [INFO DRT-0033] met4 shape region query size = 253. [INFO DRT-0033] via4 shape region query size = 25. [INFO DRT-0033] met5 shape region query size = 39. [INFO DRT-0165] Start pin access. [INFO DRT-0078] Complete 659 pins. [INFO DRT-0081] Complete 82 unique inst patterns. [INFO DRT-0084] Complete 886 groups. #scanned instances = 1335 #unique instances = 82 #stdCellGenAp = 2456 #stdCellValidPlanarAp = 8 #stdCellValidViaAp = 1970 #stdCellPinNoAp = 0 #stdCellPinCnt = 4507 #instTermValidViaApCnt = 0 #macroGenAp = 0 #macroValidPlanarAp = 0 #macroValidViaAp = 0 #macroNoAp = 0 [INFO DRT-0166] Complete pin access. [INFO DRT-0267] cpu time = 00:00:23, elapsed time = 00:00:23, memory = 230.41 (MB), peak = 230.25 (MB) [INFO DRT-0157] Number of guides: 8658 [INFO DRT-0169] Post process guides. [INFO DRT-0176] GCELLGRID X 0 DO 25 STEP 6900 ; [INFO DRT-0177] GCELLGRID Y 0 DO 25 STEP 6900 ; [INFO DRT-0028] Complete FR_MASTERSLICE. [INFO DRT-0028] Complete licon. [INFO DRT-0028] Complete li1. [INFO DRT-0028] Complete mcon. [INFO DRT-0028] Complete met1. [INFO DRT-0028] Complete via. [INFO DRT-0028] Complete met2. [INFO DRT-0028] Complete via2. [INFO DRT-0028] Complete met3. [INFO DRT-0028] Complete via3. [INFO DRT-0028] Complete met4. [INFO DRT-0028] Complete via4. [INFO DRT-0028] Complete met5. [INFO DRT-0178] Init guide query. [INFO DRT-0035] Complete FR_MASTERSLICE (guide). [INFO DRT-0035] Complete licon (guide). [INFO DRT-0035] Complete li1 (guide). [INFO DRT-0035] Complete mcon (guide). [INFO DRT-0035] Complete met1 (guide). [INFO DRT-0035] Complete via (guide). [INFO DRT-0035] Complete met2 (guide). [INFO DRT-0035] Complete via2 (guide). [INFO DRT-0035] Complete met3 (guide). [INFO DRT-0035] Complete via3 (guide). [INFO DRT-0035] Complete met4 (guide). [INFO DRT-0035] Complete via4 (guide). [INFO DRT-0035] Complete met5 (guide). [INFO DRT-0036] FR_MASTERSLICE guide region query size = 0. [INFO DRT-0036] licon guide region query size = 0. [INFO DRT-0036] li1 guide region query size = 3345. [INFO DRT-0036] mcon guide region query size = 0. [INFO DRT-0036] met1 guide region query size = 2757. [INFO DRT-0036] via guide region query size = 0. [INFO DRT-0036] met2 guide region query size = 1167. [INFO DRT-0036] via2 guide region query size = 0. [INFO DRT-0036] met3 guide region query size = 57. [INFO DRT-0036] via3 guide region query size = 0. [INFO DRT-0036] met4 guide region query size = 2. [INFO DRT-0036] via4 guide region query size = 0. [INFO DRT-0036] met5 guide region query size = 0. [INFO DRT-0179] Init gr pin query. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 230.41 (MB), peak = 230.25 (MB) [INFO DRT-0245] skipped writing guide updates to database. [INFO DRT-0185] Post process initialize RPin region query. [INFO DRT-0181] Start track assignment. [INFO DRT-0184] Done with 4514 vertical wires in 1 frboxes and 2814 horizontal wires in 1 frboxes. [INFO DRT-0186] Done with 359 vertical wires in 1 frboxes and 747 horizontal wires in 1 frboxes. [INFO DRT-0182] Complete track assignment. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 234.59 (MB), peak = 234.43 (MB) [INFO DRT-0187] Start routing data preparation. [INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 234.71 (MB), peak = 234.62 (MB) [INFO DRT-0194] Start detail routing. [INFO DRT-0195] Start 0th optimization iteration. Completing 10% with 0 violations. elapsed time = 00:00:01, memory = 242.66 (MB). Completing 20% with 0 violations. elapsed time = 00:00:04, memory = 266.46 (MB). Completing 30% with 91 violations. elapsed time = 00:00:06, memory = 268.66 (MB). Completing 40% with 91 violations. elapsed time = 00:00:08, memory = 268.66 (MB). Completing 50% with 91 violations. elapsed time = 00:00:08, memory = 273.14 (MB). Completing 60% with 193 violations. elapsed time = 00:00:11, memory = 285.24 (MB). Completing 70% with 193 violations. elapsed time = 00:00:12, memory = 285.24 (MB). Completing 80% with 264 violations. elapsed time = 00:00:14, memory = 285.24 (MB). Completing 90% with 264 violations. elapsed time = 00:00:15, memory = 285.24 (MB). Completing 100% with 323 violations. elapsed time = 00:00:15, memory = 285.24 (MB). [INFO DRT-0199] Number of violations = 372. Viol/Layer met1 met2 Metal Spacing 73 6 Recheck 37 12 Short 226 18 [INFO DRT-0267] cpu time = 00:00:15, elapsed time = 00:00:15, memory = 594.30 (MB), peak = 594.06 (MB) Total wire length = 31176 um. Total wire length on LAYER li1 = 0 um. Total wire length on LAYER met1 = 15866 um. Total wire length on LAYER met2 = 14245 um. Total wire length on LAYER met3 = 1039 um. Total wire length on LAYER met4 = 25 um. Total wire length on LAYER met5 = 0 um. Total number of vias = 8871. Up-via summary (total 8871): ----------------------- FR_MASTERSLICE 0 li1 4530 met1 4266 met2 71 met3 4 met4 0 ----------------------- 8871 [INFO DRT-0195] Start 1st optimization iteration. Completing 10% with 372 violations. elapsed time = 00:00:01, memory = 594.30 (MB). Completing 20% with 372 violations. elapsed time = 00:00:03, memory = 595.63 (MB). Completing 30% with 342 violations. elapsed time = 00:00:04, memory = 595.63 (MB). Completing 40% with 342 violations. elapsed time = 00:00:07, memory = 595.63 (MB). Completing 50% with 342 violations. elapsed time = 00:00:08, memory = 595.63 (MB). Completing 60% with 351 violations. elapsed time = 00:00:11, memory = 595.63 (MB). Completing 70% with 351 violations. elapsed time = 00:00:12, memory = 595.63 (MB). Completing 80% with 315 violations. elapsed time = 00:00:15, memory = 595.63 (MB). Completing 90% with 315 violations. elapsed time = 00:00:16, memory = 595.63 (MB). Completing 100% with 299 violations. elapsed time = 00:00:17, memory = 595.63 (MB). [INFO DRT-0199] Number of violations = 299. Viol/Layer mcon met1 met2 Cut Spacing 3 0 0 Metal Spacing 0 54 3 Min Hole 0 1 0 Short 0 233 5 [INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:17, memory = 595.90 (MB), peak = 595.62 (MB) Total wire length = 30991 um. Total wire length on LAYER li1 = 0 um. Total wire length on LAYER met1 = 15777 um. Total wire length on LAYER met2 = 14180 um. Total wire length on LAYER met3 = 1020 um. Total wire length on LAYER met4 = 12 um. Total wire length on LAYER met5 = 0 um. Total number of vias = 8860. Up-via summary (total 8860): ----------------------- FR_MASTERSLICE 0 li1 4529 met1 4256 met2 73 met3 2 met4 0 ----------------------- 8860 [INFO DRT-0195] Start 2nd optimization iteration. Completing 10% with 299 violations. elapsed time = 00:00:00, memory = 595.90 (MB). Completing 20% with 299 violations. elapsed time = 00:00:02, memory = 595.90 (MB). Completing 30% with 299 violations. elapsed time = 00:00:03, memory = 595.90 (MB). Completing 40% with 283 violations. elapsed time = 00:00:03, memory = 595.90 (MB). Completing 50% with 283 violations. elapsed time = 00:00:06, memory = 595.96 (MB). Completing 60% with 283 violations. elapsed time = 00:00:07, memory = 595.96 (MB). Completing 70% with 257 violations. elapsed time = 00:00:08, memory = 595.96 (MB). Completing 80% with 257 violations. elapsed time = 00:00:11, memory = 595.96 (MB). Completing 90% with 211 violations. elapsed time = 00:00:12, memory = 595.96 (MB). Completing 100% with 198 violations. elapsed time = 00:00:14, memory = 595.96 (MB). [INFO DRT-0199] Number of violations = 198. Viol/Layer mcon met1 met2 Cut Spacing 2 0 0 Metal Spacing 0 43 2 Min Hole 0 1 0 Short 0 146 4 [INFO DRT-0267] cpu time = 00:00:14, elapsed time = 00:00:14, memory = 595.96 (MB), peak = 595.62 (MB) Total wire length = 30946 um. Total wire length on LAYER li1 = 0 um. Total wire length on LAYER met1 = 15749 um. Total wire length on LAYER met2 = 14139 um. Total wire length on LAYER met3 = 1031 um. Total wire length on LAYER met4 = 25 um. Total wire length on LAYER met5 = 0 um. Total number of vias = 8822. Up-via summary (total 8822): ----------------------- FR_MASTERSLICE 0 li1 4530 met1 4211 met2 77 met3 4 met4 0 ----------------------- 8822 [INFO DRT-0195] Start 3rd optimization iteration. Completing 10% with 198 violations. elapsed time = 00:00:00, memory = 595.96 (MB). Completing 20% with 198 violations. elapsed time = 00:00:01, memory = 595.96 (MB). Completing 30% with 135 violations. elapsed time = 00:00:02, memory = 595.96 (MB). Completing 40% with 135 violations. elapsed time = 00:00:03, memory = 595.96 (MB). Completing 50% with 135 violations. elapsed time = 00:00:03, memory = 595.96 (MB). Completing 60% with 95 violations. elapsed time = 00:00:04, memory = 595.96 (MB). Completing 70% with 95 violations. elapsed time = 00:00:04, memory = 595.96 (MB). Completing 80% with 69 violations. elapsed time = 00:00:05, memory = 595.96 (MB). Completing 90% with 69 violations. elapsed time = 00:00:06, memory = 595.96 (MB). Completing 100% with 0 violations. elapsed time = 00:00:06, memory = 595.96 (MB). [INFO DRT-0199] Number of violations = 0. [INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:06, memory = 595.96 (MB), peak = 595.62 (MB) Total wire length = 30907 um. Total wire length on LAYER li1 = 0 um. Total wire length on LAYER met1 = 15140 um. Total wire length on LAYER met2 = 14154 um. Total wire length on LAYER met3 = 1533 um. Total wire length on LAYER met4 = 78 um. Total wire length on LAYER met5 = 0 um. Total number of vias = 8930. Up-via summary (total 8930): ----------------------- FR_MASTERSLICE 0 li1 4528 met1 4253 met2 138 met3 11 met4 0 ----------------------- 8930 [INFO DRT-0198] Complete detail routing. Total wire length = 30907 um. Total wire length on LAYER li1 = 0 um. Total wire length on LAYER met1 = 15140 um. Total wire length on LAYER met2 = 14154 um. Total wire length on LAYER met3 = 1533 um. Total wire length on LAYER met4 = 78 um. Total wire length on LAYER met5 = 0 um. Total number of vias = 8930. Up-via summary (total 8930): ----------------------- FR_MASTERSLICE 0 li1 4528 met1 4253 met2 138 met3 11 met4 0 ----------------------- 8930 [INFO DRT-0267] cpu time = 00:00:54, elapsed time = 00:00:54, memory = 596.02 (MB), peak = 595.80 (MB) [INFO DRT-0180] Post processing. Adding filler cells... [INFO DPL-0001] Placed 3270 filler instances. Running final analysis... [WARNING EST-0018] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance. Design area 10942 um^2 41% utilization. Writing outputs... ============================================ Place & Route complete! DEF: build/ring_modulator.def Netlist: build/ring_modulator_pnr.v Reports: build/ring_modulator_*.rpt ============================================ cd ring_modulator && \ klayout -zz -r ../flow/def2gds.rb \ -rd def_file=build/ring_modulator.def \ -rd gds_file=build/ring_modulator.gds ============================================ DEF to GDS Conversion ============================================ Loading standard cell GDS... Reading DEF: build/ring_modulator.def Writing GDS: build/ring_modulator.gds ============================================ GDS written successfully! File size: 5526084 bytes ============================================ Ring Modulator build complete: ring_modulator/build/ring_modulator.gds /foss/designs/ring_modulator > ```

To view the final GDS layout in KLayout, I run the command make view-ring-gds. This target opens the generated GDS file of my ring_modulator design using the Sky130 technology file in KLayout. The GDS file is the final physical representation of the chip, so opening it in KLayout allows me to inspect the real layout produced by the flow.

By using this command, I can check the final geometry of the design, including the overall chip area, the placement of the standard cells, the routing between them, and the general structure of the layout. This is an important final verification step, because it lets me visually confirm that the design was successfully converted into a physical layout and exported correctly as a GDS file.

In other words, make view-ring-gds is the step I use to review the final result of the ASIC flow in KLayout.

When I open the final GDS file in KLayout, I can see the physical implementation of my ring modulator as a real chip layout. The design is organized as a collection of standard cells placed inside the core area and connected through the metal routing layers. Instead of looking at the circuit as Verilog code or a logical netlist, KLayout shows the actual geometric shapes that would be used for fabrication.

At this stage, I can identify the overall structure of the design, including the placement of the cells, the routing between them, and the different layout layers such as diffusion, polysilicon, contacts, vias, and metal interconnects. This helps me understand how the logical design has been translated into a physical form.

By inspecting the layout in KLayout, I can also verify that the design looks consistent: the cells are placed in rows, the routing is distributed across the available metal layers, and the final result matches the expected area and structure of the circuit. In this way, KLayout provides a visual confirmation that the design flow has successfully produced a manufacturable layout.

From Confusion to Excitement

I managed to design the chip layout, and I am really happy about it. I still do not understand every step yet, but I am learning little by little, and each new result makes me even more excited. This is becoming a very special experience for me, and I feel that the next two sessions will be the real breakthrough of everything. I also want to thank the teachers and my classmates, because their support, knowledge, and shared energy are making all of this possible and turning it into reality.