Session 7: Packaging & Board Design¶
The class on Monday, March 9, taught by Alex, helped me understand much more clearly that my project is no longer only about designing the internal chip circuit, but about thinking of it as a complete system that must eventually be connected, powered, tested, and measured in the real world. Until now, I was mainly focused on the internal design itself: how the modulator block works, how the circuit behaves, and how to move forward step by step in the chip design flow. After this session, however, I can see much more clearly that I also need to define other equally important aspects, such as the package, the pin assignment, the evaluation board, and the overall testing strategy.
In my case, this is especially important because the final system is intended to work in a Eurorack environment, where I have +12 V and -12 V power rails for the analog side, and also +5 V available to supply the digital section and power the IC. The external input and output signals may reach up to ±5 V, so I can no longer think of the chip as an isolated block. I also need to think carefully about how those external voltages will be adapted to the safe operating range of the internal circuitry, and how the analog and digital domains will coexist on the same system.
Until now, my chip did not include power supply inputs in the Verilog file, so logically, when I checked the Yosys and OpenRoad results, there was nothing related to the power network. Because of that, I now need to review and redefine the top-level Verilog module to correctly add the power inputs and prepare the design for a more realistic physical integration. In that sense, this class helped me realize that the project does not end with simulation or layout. It starts becoming a real hardware system that must interact with a board, connectors, power rails, support circuitry, and measurement instruments.
Because of that, I think my next step should be to define a minimum but functional version of the project, carefully decide which pins I need for power, inputs, outputs, and testing, and begin designing the evaluation board in KiCad. That board will not only hold the chip, but will also help me organize power distribution, add proper decoupling, adapt signal levels where necessary, and make debugging much easier. I also think it is important to start planning now how I will verify that everything works: first checking that all power rails are correct, then confirming current consumption, then injecting simple test signals, and finally comparing the measured behavior with my simulation results.
I think this class really helped me shift my perspective. Before, I mostly saw the chip as a design block, but now I am starting to see it more as a real device: something that I will eventually need to assemble, power, probe, measure, and debug as part of a complete Eurorack-compatible system. For me, that change in mindset is very important, because it helps me connect the theoretical side of chip design with the practical side of turning it into a working physical prototype.
Optimize verilog¶
In this part of the project, I decided to reorganize my Verilog design into two levels: a clean functional core and a top-level module prepared for physical integration. The main block, ring_modulator, only contains the RTL logic of the ring modulator, with its clock, reset, signal input, carrier input, and output. At this level, I did not add power pins because I am still describing the logical behavior of the circuit, not its physical implementation.
ring_modulator.v¶
module ring_modulator (
input wire clk,
input wire rst_n,
input wire signed [15:0] signal_in,
input wire signed [15:0] carrier_in,
output reg signed [15:0] mod_out
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
mod_out <= 16'sd0;
else
mod_out <= (signal_in * carrier_in) >>> 15;
end
endmodule
ring_modulator_top.v¶
Then I added a top wrapper called ring_modulator_top. In this module, I included the power pins using the USE_POWER_PINS convention, with vccd1 and vssd1. This makes the design more suitable for an ASIC flow with Sky130 and OpenLane, while keeping the RTL core clean, reusable, and easy to simulate.
module ring_modulator_top (
ifdef USE_POWER_PINS
inout wire vccd1,
inout wire vssd1,
endif
input wire clk,
input wire rst_n,
input wire signed [15:0] signal_in,
input wire signed [15:0] carrier_in,
output wire signed [15:0] mod_out
);
ring_modulator u_ring_modulator (
.clk (clk),
.rst_n (rst_n),
.signal_in (signal_in),
.carrier_in (carrier_in),
.mod_out (mod_out)
);
endmodule
I also simplified the main multiplication operation. Instead of storing the product in an intermediate register and using it in the next clock cycle, I directly implemented the output as a signed multiplication followed by a 15-bit arithmetic shift: (signal_in * carrier_in) >>> 15. This better represents the fixed-point rescaling step and avoids an unnecessary extra cycle of latency.
Testbench¶
In addition, I prepared a simple testbench to verify the module with different input combinations, including both positive and negative values. This allows me to quickly check the behavior of the modulator in simulation and inspect the waveforms in GTKWave before moving on to synthesis.
`timescale 1ns/1ps
module ring_modulator_tb;
reg clk;
reg rst_n;
reg signed [15:0] signal_in;
reg signed [15:0] carrier_in;
wire signed [15:0] mod_out;
ring_modulator_top dut (
.clk(clk),
.rst_n(rst_n),
.signal_in(signal_in),
.carrier_in(carrier_in),
.mod_out(mod_out)
);
// 100 MHz clock
initial clk = 1'b0;
always #5 clk = ~clk;
// VCD dump
initial begin
$dumpfile("tb_ring_modulator.vcd");
$dumpvars(0, ring_modulator_tb);
end
// real -> Q1.15
function signed [15:0] real_to_q15;
input real x;
integer tmp;
begin
if (x > 0.999969) x = 0.999969;
if (x < -1.0) x = -1.0;
tmp = $rtoi(x * 32768.0);
real_to_q15 = tmp[15:0];
end
endfunction
// Parameters for sine generation
real fs, f_sig, f_car, A_sig, A_car;
integer n;
integer fcsv;
// Expected alignment for current RTL: 1 cycle
reg signed [15:0] sig_d0;
reg signed [15:0] car_d0;
reg signed [31:0] exp_prod;
reg signed [15:0] exp_out;
initial begin
// Config
fs = 48000.0;
f_sig = 200.0;
f_car = 1000.0;
A_sig = 0.9;
A_car = 0.9;
// Init
rst_n = 1'b0;
signal_in = 16'sd0;
carrier_in = 16'sd0;
sig_d0 = 16'sd0;
car_d0 = 16'sd0;
exp_prod = 32'sd0;
exp_out = 16'sd0;
// CSV
fcsv = $fopen("ringmod_sine.csv", "w");
if (fcsv == 0) begin
$display("ERROR: cannot open ringmod_sine.csv for writing. Check permissions / working directory.");
end else begin
$fwrite(fcsv, "n,signal_in,carrier_in,mod_out,exp_out\n");
$display("CSV opened OK: ringmod_sine.csv");
end
// Reset
repeat (5) @(posedge clk);
rst_n = 1'b1;
// Run
for (n = 0; n < 2000; n = n + 1) begin
real t, s1, s2;
@(posedge clk);
t = n / fs;
s1 = A_sig * $sin(2.0*3.141592653589793*f_sig*t);
s2 = A_car * $sin(2.0*3.141592653589793*f_car*t);
// Apply new samples
signal_in = real_to_q15(s1);
carrier_in = real_to_q15(s2);
// Expected value aligned to 1-cycle registered output
exp_prod = sig_d0 * car_d0;
exp_out = exp_prod >>> 15;
// Update delay line after computing expectation
sig_d0 = signal_in;
car_d0 = carrier_in;
if (fcsv != 0) begin
$fwrite(fcsv, "%0d,%0d,%0d,%0d,%0d\n", n, signal_in, carrier_in, mod_out, exp_out);
end
end
if (fcsv != 0) begin
$fclose(fcsv);
$display("CSV closed OK.");
end
$display("Done. Generated tb_ring_modulator.vcd and ringmod_sine.csv");
#20;
$finish;
end
endmodule
Finally, I prepared a basic OpenLane configuration file, defining ring_modulator_top as the main design, listing the Verilog sources, the clock port, and some initial floorplanning parameters. With this structure, my design is better organized, easier to document, and more ready to continue with synthesis, place and route, and GDS generation.
congif.tcl por RCL¶
set ::env(DESIGN_NAME) ring_modulator_top
set ::env(VERILOG_FILES) "\
$::env(DESIGN_DIR)/src/ring_modulator.v \
$::env(DESIGN_DIR)/src/ring_modulator_top.v"
set ::env(CLOCK_PORT) clk
set ::env(CLOCK_PERIOD) 10
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 100 100"
set ::env(PL_TARGET_DENSITY) 0.55
set ::env(SYNTH_USE_PG_PINS_DEFINES) 1
Running Yosys¶
yosys -p "
read_verilog ring_modulator.v;
hierarchy -check -top ring_modulator;
synth -top ring_modulator;
dfflibmap -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib;
abc -liberty /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib;
clean;
stat;
write_verilog -noattr ring_modulator_synth.v;
"
run_openroad.tcl¶
At this stage, I prepared a basic run_openroad.tcl script to move from synthesis to physical implementation. In this script, I load the Sky130 technology files, the standard-cell library, and the synthesized netlist of my top-level module. Then I read the timing constraints, define an initial floorplan, connect the power nets, and run the main physical design steps: placement, clock tree synthesis, and routing. Finally, I generate several reports, such as timing, area, and power, and save the resulting DEF, routed netlist, and database files. This script is still a simple starting point, but it helps me understand the structure of the physical design flow and how my Verilog design begins to turn into a real chip layout.
# run_openroad.tcl
# OpenROAD flow for ring_modulator_top
set design_name "ring_modulator_top"
set top_module "ring_modulator_top"
set netlist_file "./ring_modulator_top_synth.v"
set sdc_file "./src/${design_name}.sdc"
set tech_lef "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef"
set stdcell_lef "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef"
set liberty_file "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
set out_dir "./results/openroad"
file mkdir $out_dir
# --------------------------------------------------
# Read technology and design
# --------------------------------------------------
read_lef $tech_lef
read_lef $stdcell_lef
read_liberty $liberty_file
read_verilog $netlist_file
link_design $top_module
# --------------------------------------------------
# Constraints
# --------------------------------------------------
if {[file exists $sdc_file]} {
puts "Reading SDC: $sdc_file"
read_sdc $sdc_file
} else {
puts "WARNING: SDC file not found at $sdc_file"
puts "Applying basic default clock constraint on clk"
create_clock -name clk -period 20 [get_ports clk]
set all_in [all_inputs]
set clk_port [get_ports clk]
set clk_idx [lsearch $all_in $clk_port]
if {$clk_idx >= 0} {
set all_in_wo_clk [lreplace $all_in $clk_idx $clk_idx]
} else {
set all_in_wo_clk $all_in
}
if {[llength $all_in_wo_clk] > 0} {
set_input_delay 2 -clock clk $all_in_wo_clk
}
set all_out [all_outputs]
if {[llength $all_out] > 0} {
set_output_delay 2 -clock clk $all_out
}
}
# --------------------------------------------------
# Floorplan
# --------------------------------------------------
initialize_floorplan \
-site unithd \
-die_area "0 0 200 200" \
-core_area "20 20 180 180"
# --------------------------------------------------
# Routing tracks
# --------------------------------------------------
make_tracks li1 -x_offset 0.17 -x_pitch 0.34 -y_offset 0.23 -y_pitch 0.46
make_tracks met1 -x_offset 0.17 -x_pitch 0.34 -y_offset 0.23 -y_pitch 0.46
make_tracks met2 -x_offset 0.23 -x_pitch 0.46 -y_offset 0.17 -y_pitch 0.34
make_tracks met3 -x_offset 0.34 -x_pitch 0.68 -y_offset 0.34 -y_pitch 0.68
make_tracks met4 -x_offset 0.46 -x_pitch 0.92 -y_offset 0.46 -y_pitch 0.92
make_tracks met5 -x_offset 1.70 -x_pitch 3.40 -y_offset 1.70 -y_pitch 3.40
# --------------------------------------------------
# Power / Ground connections
# --------------------------------------------------
add_global_connection -net vccd1 -inst_pattern .* -pin_pattern ^VPWR$ -power
add_global_connection -net vssd1 -inst_pattern .* -pin_pattern ^VGND$ -ground
add_global_connection -net vccd1 -inst_pattern .* -pin_pattern ^VDD$ -power
add_global_connection -net vssd1 -inst_pattern .* -pin_pattern ^VSS$ -ground
global_connect
# --------------------------------------------------
# PDN
# --------------------------------------------------
define_pdn_grid -name core_grid
add_pdn_stripe -grid core_grid -layer met4 -width 1.6 -pitch 40.0 -offset 5.0
add_pdn_stripe -grid core_grid -layer met5 -width 1.6 -pitch 40.0 -offset 5.0
add_pdn_connect -grid core_grid -layers {met4 met5}
# --------------------------------------------------
# Pin placement
# --------------------------------------------------
place_pins -hor_layers met3 -ver_layers met2
# --------------------------------------------------
# Placement / CTS / Routing
# --------------------------------------------------
global_placement
detailed_placement
set_wire_rc -clock -layer met3
clock_tree_synthesis
repair_clock_nets
set_routing_layers -signal met1-met5 -clock met3-met5
global_route
detailed_route
# --------------------------------------------------
# Reports
# --------------------------------------------------
report_checks > $out_dir/checks.rpt
report_tns > $out_dir/tns.rpt
report_wns > $out_dir/wns.rpt
report_design_area > $out_dir/area.rpt
catch {report_power > $out_dir/power.rpt}
# --------------------------------------------------
# Outputs
# --------------------------------------------------
write_def $out_dir/${design_name}.def
write_verilog $out_dir/${design_name}_routed.v
write_db $out_dir/${design_name}.odb
puts "OpenROAD flow finished for $design_name"
openroad -exit run_openroad.tcl | tee openroad.log
Makefile command¶
To simulate my design, I used Icarus Verilog as a simple way to compile and run the Verilog files before moving on to synthesis. First, I compiled the main RTL module, the top-level wrapper, and the testbench together into a simulation executable. Then I ran that executable to launch the testbench and apply the input stimuli that I had prepared for the ring modulator. During the simulation, the waveform file was generated automatically, which allowed me to inspect the behavior of the design over time. Finally, I opened that waveform file in GTKWave to visually check signals such as the clock, reset, inputs, and output, and confirm that the modulator was behaving as expected before continuing with the next steps of the flow.
# =============================================================================
# Ring Modulator Top - Build Automation
# =============================================================================
SHELL := /bin/bash
# Tools
IVERILOG := iverilog
VVP := vvp
VERILATOR := verilator
YOSYS := yosys
OPENROAD := openroad
KLAYOUT := klayout
MAGIC := magic
# Common options
IVERILOG_FLAGS := -Wall -g2012
VERILATOR_FLAGS := --lint-only -Wall
# Paths
LIB := lib
FLOW := flow
# =============================================================================
# PDK Detection
# =============================================================================
ifndef PDK_ROOT
ifneq (,$(wildcard /foss/pdks/sky130A))
PDK_ROOT := /foss/pdks
else ifneq (,$(wildcard $(HOME)/pdks/sky130A))
PDK_ROOT := $(HOME)/pdks
else ifneq (,$(wildcard /opt/pdks/sky130A))
PDK_ROOT := /opt/pdks
endif
endif
define check_pdk
@if [ -z "$(PDK_ROOT)" ]; then \
echo "ERROR: PDK_ROOT is not set and Sky130 PDK not found."; \
echo ""; \
echo "To run the ASIC flow, you need the Sky130 PDK."; \
echo "Use IIC-OSIC-TOOLS Docker or export PDK_ROOT manually."; \
exit 1; \
fi
endef
# =============================================================================
# Project definition
# =============================================================================
RING_TOP := ring_modulator_top
RING_DIR := ring_modulator
RING_SRC_CORE := $(RING_DIR)/ring_modulator.v
RING_SRC_TOP := $(RING_DIR)/ring_modulator_top.v
RING_SRCS := $(RING_SRC_CORE) $(RING_SRC_TOP)
RING_BUILD := $(RING_DIR)/build
# Testbench
RING_TB := $(RING_DIR)/ring_modulator_tb.v
# Constraints
RING_SDC := $(RING_DIR)/ring_modulator_top.sdc
# Standard cell library GDS path
LIB_DIR := $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd
# =============================================================================
# Simulation
# =============================================================================
.PHONY: sim-ring
sim-ring: $(RING_DIR)/ring_modulator_tb.vvp
$(VVP) $<
$(RING_DIR)/ring_modulator_tb.vvp: $(RING_SRCS) $(RING_TB)
$(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^
# =============================================================================
# Lint
# =============================================================================
.PHONY: lint-ring
lint-ring:
$(VERILATOR) $(VERILATOR_FLAGS) -I$(LIB) $(RING_SRCS)
# =============================================================================
# Quick synthesis (no PDK required)
# =============================================================================
.PHONY: synth-ring
synth-ring:
$(YOSYS) -p "read_verilog -I$(LIB) $(RING_SRCS); synth -top $(RING_TOP); stat"
# =============================================================================
# Sky130 synthesis
# =============================================================================
.PHONY: sky130-ring
sky130-ring: $(RING_BUILD)/$(RING_TOP)_synth.v
$(RING_BUILD)/$(RING_TOP)_synth.v: $(RING_SRCS)
$(call check_pdk)
@mkdir -p $(RING_BUILD)
cd $(RING_DIR) && \
TOP=$(RING_TOP) \
VERILOG="ring_modulator.v ring_modulator_top.v" \
OUT_DIR=build \
$(YOSYS) -c ../$(FLOW)/synth.tcl
# =============================================================================
# Place & Route
# =============================================================================
.PHONY: pnr-ring
pnr-ring: $(RING_BUILD)/$(RING_TOP).def
$(RING_BUILD)/$(RING_TOP).def: $(RING_BUILD)/$(RING_TOP)_synth.v $(RING_SDC)
$(call check_pdk)
cd $(RING_DIR) && \
TOP=$(RING_TOP) \
SDC=ring_modulator_top.sdc \
OUT_DIR=build \
$(OPENROAD) -exit ../$(FLOW)/pnr.tcl
# =============================================================================
# GDS generation
# =============================================================================
.PHONY: gds-ring
gds-ring: $(RING_BUILD)/$(RING_TOP).gds
$(RING_BUILD)/$(RING_TOP).gds: $(RING_BUILD)/$(RING_TOP).def
$(call check_pdk)
cd $(RING_DIR) && \
$(KLAYOUT) -zz -r ../$(FLOW)/def2gds.rb \
-rd def_file=build/$(RING_TOP).def \
-rd gds_file=build/$(RING_TOP).gds
# =============================================================================
# Full build
# =============================================================================
.PHONY: build-ring
build-ring: gds-ring
@echo "Ring Modulator Top build complete: $(RING_BUILD)/$(RING_TOP).gds"
# =============================================================================
# View layout
# =============================================================================
.PHONY: view-ring view-ring-gds
view-ring: $(RING_BUILD)/$(RING_TOP).def
$(call check_pdk)
$(KLAYOUT) -n $(PDK_ROOT)/sky130A/libs.tech/klayout/tech/sky130A.lyt \
$(LIB_DIR)/gds/sky130_fd_sc_hd.gds $<
view-ring-gds: $(RING_BUILD)/$(RING_TOP).gds
$(call check_pdk)
$(KLAYOUT) -n $(PDK_ROOT)/sky130A/libs.tech/klayout/tech/sky130A.lyt \
$<
# =============================================================================
# Reports
# =============================================================================
.PHONY: report-ring
report-ring:
@echo "=== Ring Modulator Top Reports ==="
@cat $(RING_BUILD)/$(RING_TOP)_timing.rpt 2>/dev/null || echo "Run 'make pnr-ring' first"
@cat $(RING_BUILD)/$(RING_TOP)_area.rpt 2>/dev/null || true
@cat $(RING_BUILD)/$(RING_TOP)_power.rpt 2>/dev/null || true
# =============================================================================
# Environment check
# =============================================================================
.PHONY: check-env
check-env:
@echo "=== Environment Check ==="
@echo ""
@echo "PDK_ROOT: $(PDK_ROOT)"
@if [ -n "$(PDK_ROOT)" ] && [ -d "$(PDK_ROOT)/sky130A" ]; then \
echo " Status: OK (Sky130 PDK found)"; \
else \
echo " Status: NOT FOUND"; \
fi
@echo ""
@echo "Tools:"
@which $(YOSYS) > /dev/null 2>&1 && echo " yosys: OK ($(shell which $(YOSYS)))" || echo " yosys: NOT FOUND"
@which $(OPENROAD) > /dev/null 2>&1 && echo " openroad: OK ($(shell which $(OPENROAD)))" || echo " openroad: NOT FOUND"
@which $(KLAYOUT) > /dev/null 2>&1 && echo " klayout: OK ($(shell which $(KLAYOUT)))" || echo " klayout: NOT FOUND"
@which $(IVERILOG) > /dev/null 2>&1 && echo " iverilog: OK ($(shell which $(IVERILOG)))" || echo " iverilog: NOT FOUND"
@which $(VERILATOR) > /dev/null 2>&1 && echo " verilator: OK ($(shell which $(VERILATOR)))" || echo " verilator: NOT FOUND"
@which $(MAGIC) > /dev/null 2>&1 && echo " magic: OK ($(shell which $(MAGIC)))" || echo " magic: NOT FOUND"
# =============================================================================
# Clean
# =============================================================================
.PHONY: clean clean-sim clean-build
clean-sim:
rm -f $(RING_DIR)/*.vvp $(RING_DIR)/*.vcd
@echo "Cleaned simulation files."
clean-build:
rm -rf $(RING_BUILD)
@echo "Cleaned build directory."
clean: clean-sim clean-build
@echo "All cleaned."
# =============================================================================
# Help
# =============================================================================
.PHONY: help
help:
@echo "Ring Modulator Top Makefile"
@echo ""
@echo "Setup:"
@echo " make check-env - Check tools and PDK"
@echo ""
@echo "Simulation:"
@echo " make sim-ring - Run simulation"
@echo ""
@echo "Lint:"
@echo " make lint-ring - Lint with Verilator"
@echo ""
@echo "Quick synthesis:"
@echo " make synth-ring - Synthesize and show stats"
@echo ""
@echo "ASIC flow:"
@echo " make sky130-ring - Synthesize to Sky130 cells"
@echo " make pnr-ring - Place and route"
@echo " make gds-ring - Generate GDS"
@echo " make build-ring - Full flow"
@echo ""
@echo "View:"
@echo " make view-ring - View DEF in KLayout"
@echo " make view-ring-gds - View final GDS in KLayout"
@echo ""
@echo "Reports:"
@echo " make report-ring - Show timing/area/power reports"
@echo ""
@echo "Cleanup:"
@echo " make clean - Remove generated files"
Terminal contents
/foss/designs/ring_modulator_final_proyect > make build-ring
cd ring_modulator && \
TOP=ring_modulator_top \
VERILOG="ring_modulator.v ring_modulator_top.v" \
OUT_DIR=build \
yosys -c ../flow/synth.tcl
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.62 (git sha1 7326bb7d6, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
[TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip.
[TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip.
============================================
Synthesizing: ring_modulator_top
Sources: ring_modulator.v ring_modulator_top.v
Output: build
============================================
1. Executing Verilog-2005 frontend: ring_modulator.v
Parsing Verilog input from `ring_modulator.v' to AST representation.
Generating RTLIL representation for module `\ring_modulator'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: ring_modulator_top.v
Parsing Verilog input from `ring_modulator_top.v' to AST representation.
Generating RTLIL representation for module `\ring_modulator_top'.
Successfully finished Verilog frontend.
3. Executing HIERARCHY pass (managing design hierarchy).
3.1. Analyzing design hierarchy..
Top module: \ring_modulator_top
Used module: \ring_modulator
3.2. Analyzing design hierarchy..
Top module: \ring_modulator_top
Used module: \ring_modulator
Removed 0 unused modules.
4. Executing SYNTH pass.
4.1. Executing HIERARCHY pass (managing design hierarchy).
4.1.1. Analyzing design hierarchy..
Top module: \ring_modulator_top
Used module: \ring_modulator
4.1.2. Analyzing design hierarchy..
Top module: \ring_modulator_top
Used module: \ring_modulator
Removed 0 unused modules.
4.2. Executing PROC pass (convert processes to netlists).
4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$ring_modulator.v:9$1 in module ring_modulator.
Removed a total of 0 dead cases.
4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 0 assignments to connections.
4.2.4. Executing PROC_INIT pass (extract init attributes).
4.2.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \rst_n in `\ring_modulator.$proc$ring_modulator.v:9$1'.
4.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
4.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\ring_modulator.$proc$ring_modulator.v:9$1'.
1/1: $0\mod_out[15:0]
4.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
4.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\ring_modulator.\mod_out' using process `\ring_modulator.$proc$ring_modulator.v:9$1'.
created $adff cell `$procdff$9' with positive edge clock and positive level reset.
4.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
4.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `ring_modulator.$proc$ring_modulator.v:9$1'.
Cleaned up 0 empty switches.
4.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator_top.
Optimizing module ring_modulator.
<suppressed ~3 debug messages>
4.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator_top.
Optimizing module ring_modulator.
4.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator_top..
Finding unused cells or wires in module \ring_modulator..
Removed 2 unused cells and 4 unused wires.
<suppressed ~3 debug messages>
4.5. Executing CHECK pass (checking for obvious problems).
Checking module ring_modulator...
Checking module ring_modulator_top...
Found and reported 0 problems.
4.6. Executing OPT pass (performing simple optimizations).
4.6.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ring_modulator..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \ring_modulator_top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \ring_modulator.
Optimizing cells in module \ring_modulator_top.
Performed a total of 0 changes.
4.6.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.6.6. Executing OPT_DFF pass (perform DFF optimizations).
4.6.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.6.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.6.9. Finished fast OPT passes. (There is nothing left to do.)
4.7. Executing FSM pass (extract and optimize FSM).
4.7.1. Executing FSM_DETECT pass (finding FSMs in design).
4.7.2. Executing FSM_EXTRACT pass (extracting FSM from design).
4.7.3. Executing FSM_OPT pass (simple optimizations of FSMs).
4.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.7.5. Executing FSM_OPT pass (simple optimizations of FSMs).
4.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
4.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
4.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
4.8. Executing OPT pass (performing simple optimizations).
4.8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ring_modulator..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \ring_modulator_top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \ring_modulator.
Optimizing cells in module \ring_modulator_top.
Performed a total of 0 changes.
4.8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.8.6. Executing OPT_DFF pass (perform DFF optimizations).
4.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.8.9. Finished fast OPT passes. (There is nothing left to do.)
4.9. Executing WREDUCE pass (reducing word size of cells).
Removed top 15 bits (of 16) from FF cell ring_modulator.$procdff$9 ($adff).
4.10. Executing PEEPOPT pass (run peephole optimizers).
4.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.12. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module ring_modulator:
creating $macc model for $mul$ring_modulator.v:13$3 ($mul).
creating $macc cell for $mul$ring_modulator.v:13$3: $auto$alumacc.cc:382:replace_macc$10
created 0 $alu and 1 $macc cells.
Extracting $alu and $macc cells in module ring_modulator_top:
created 0 $alu and 0 $macc cells.
4.13. Executing SHARE pass (SAT-based resource sharing).
4.14. Executing OPT pass (performing simple optimizations).
4.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ring_modulator..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \ring_modulator_top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \ring_modulator.
Optimizing cells in module \ring_modulator_top.
Performed a total of 0 changes.
4.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.14.6. Executing OPT_DFF pass (perform DFF optimizations).
4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.14.9. Finished fast OPT passes. (There is nothing left to do.)
4.15. Executing MEMORY pass.
4.15.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.
4.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.
4.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
4.15.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
4.15.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
4.15.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.15.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
4.15.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.
4.15.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.15.10. Executing MEMORY_COLLECT pass (generating $mem cells).
4.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.17. Executing OPT pass (performing simple optimizations).
4.17.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.17.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.17.3. Executing OPT_DFF pass (perform DFF optimizations).
4.17.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.17.5. Finished fast OPT passes.
4.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
4.19. Executing OPT pass (performing simple optimizations).
4.19.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.19.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \ring_modulator..
Creating internal representation of mux trees.
No muxes found in this module.
Running muxtree optimizer on module \ring_modulator_top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
4.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \ring_modulator.
Optimizing cells in module \ring_modulator_top.
Performed a total of 0 changes.
4.19.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 2 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.19.6. Executing OPT_SHARE pass.
4.19.7. Executing OPT_DFF pass (perform DFF optimizations).
4.19.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
4.19.9. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.19.10. Finished fast OPT passes. (There is nothing left to do.)
4.20. Executing TECHMAP pass (map to technology primitives).
4.20.1. Executing Verilog-2005 frontend: /foss/tools/yosys/bin/../share/yosys/techmap.v
Parsing Verilog input from `/foss/tools/yosys/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `$__div_mod_u'.
Generating RTLIL representation for module `$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Generating RTLIL representation for module `$connect'.
Generating RTLIL representation for module `$input_port'.
Successfully finished Verilog frontend.
4.20.2. Continuing TECHMAP pass.
Using extmapper maccmap for cells of type $macc_v2.
add \signal_in * \carrier_in (16x16 bits, signed)
Using extmapper simplemap for cells of type $adff.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010000 for cells of type $fa.
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~417 debug messages>
4.21. Executing OPT pass (performing simple optimizations).
4.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
<suppressed ~845 debug messages>
Optimizing module ring_modulator_top.
4.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 807 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.21.3. Executing OPT_DFF pass (perform DFF optimizations).
4.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
Removed 100 unused cells and 220 unused wires.
<suppressed ~101 debug messages>
4.21.5. Finished fast OPT passes.
4.22. Executing ABC pass (technology mapping using ABC).
4.22.1. Extracting gate netlist of module `\ring_modulator' to `<abc-temp-dir>/input.blif'..
4.22.1.1. Executed ABC.
Extracted 706 gates and 738 wires to a netlist network with 32 inputs and 1 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 01:00:48)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_library /tmp/yosys-abc-AMnJM6/stdcells.genlib
ABC: + strash
ABC: + dretime
ABC: + map
ABC: + write_blif <abc-temp-dir>/output.blif
ABC:
ABC: YOSYS_ABC_DONE
4.22.1.2. Re-integrating ABC results.
ABC RESULTS: AND cells: 135
ABC RESULTS: ANDNOT cells: 180
ABC RESULTS: NAND cells: 38
ABC RESULTS: NOR cells: 24
ABC RESULTS: NOT cells: 1
ABC RESULTS: OR cells: 36
ABC RESULTS: ORNOT cells: 46
ABC RESULTS: XNOR cells: 57
ABC RESULTS: XOR cells: 189
ABC RESULTS: internal signals: 705
ABC RESULTS: input signals: 32
ABC RESULTS: output signals: 1
Removing temp directory.
4.22.2. Extracting gate netlist of module `\ring_modulator_top' to `<abc-temp-dir>/input.blif'..
Don't call ABC as there is nothing to map.
4.22.2.1. Executed ABC.
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Removing temp directory.
Removing global temp directory.
4.23. Executing OPT pass (performing simple optimizations).
4.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module ring_modulator.
Optimizing module ring_modulator_top.
4.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\ring_modulator'.
Computing hashes of 707 cells of `\ring_modulator'.
Finding duplicate cells in `\ring_modulator'.
Finding identical cells in module `\ring_modulator_top'.
Computing hashes of 1 cells of `\ring_modulator_top'.
Finding duplicate cells in `\ring_modulator_top'.
Removed a total of 0 cells.
4.23.3. Executing OPT_DFF pass (perform DFF optimizations).
4.23.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \ring_modulator..
Finding unused cells or wires in module \ring_modulator_top..
Removed 0 unused cells and 147 unused wires.
<suppressed ~1 debug messages>
4.23.5. Finished fast OPT passes.
4.24. Executing HIERARCHY pass (managing design hierarchy).
Attribute `top' found on module `ring_modulator_top'. Setting top module to ring_modulator_top.
4.24.1. Analyzing design hierarchy..
Top module: \ring_modulator_top
Used module: \ring_modulator
4.24.2. Analyzing design hierarchy..
Top module: \ring_modulator_top
Used module: \ring_modulator
Removed 0 unused modules.
4.25. Printing statistics.
=== ring_modulator ===
+----------Local Count, excluding submodules.
|
711 wires
771 wire bits
5 public wires
50 public wire bits
5 ports
50 port bits
707 cells
180 $_ANDNOT_
135 $_AND_
1 $_DFF_PN0_
38 $_NAND_
24 $_NOR_
1 $_NOT_
46 $_ORNOT_
36 $_OR_
57 $_XNOR_
189 $_XOR_
=== ring_modulator_top ===
+----------Local Count, excluding submodules.
|
5 wires
50 wire bits
5 public wires
50 public wire bits
5 ports
50 port bits
1 submodules
1 ring_modulator
=== design hierarchy ===
+----------Count including submodules.
|
707 ring_modulator_top
707 ring_modulator
+----------Count including submodules.
|
716 wires
821 wire bits
10 public wires
100 public wire bits
10 ports
100 port bits
- memories
- memory bits
- processes
707 cells
180 $_ANDNOT_
135 $_AND_
1 $_DFF_PN0_
38 $_NAND_
24 $_NOR_
1 $_NOT_
46 $_ORNOT_
36 $_OR_
57 $_XNOR_
189 $_XOR_
1 submodules
1 ring_modulator
4.26. Executing CHECK pass (checking for obvious problems).
Checking module ring_modulator...
Checking module ring_modulator_top...
Found and reported 0 problems.
5. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell sky130_fd_sc_hd__dfxtp_1 (noninv, pins=3, area=20.02) is a direct match for cell type $_DFF_P_.
cell sky130_fd_sc_hd__dfrtn_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_NN0_.
cell sky130_fd_sc_hd__dfrtp_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_PN0_.
cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
cell sky130_fd_sc_hd__edfxtp_1 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFFE_PP_.
cell sky130_fd_sc_hd__dfbbn_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_NNN_.
cell sky130_fd_sc_hd__dfbbp_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_PNN_.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\sky130_fd_sc_hd__dfxtp_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
\sky130_fd_sc_hd__dfrtn_1 _DFF_NN0_ (.CLK_N( C), .D( D), .Q( Q), .RESET_B( R));
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\sky130_fd_sc_hd__dfrtp_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
\sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
unmapped dff cell: $_DFFE_NN_
unmapped dff cell: $_DFFE_NP_
unmapped dff cell: $_DFFE_PN_
\sky130_fd_sc_hd__edfxtp_1 _DFFE_PP_ (.CLK( C), .D( D), .DE( E), .Q( Q));
\sky130_fd_sc_hd__dfbbn_1 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
\sky130_fd_sc_hd__dfbbp_1 _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
5.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
<suppressed ~24 debug messages>
Mapping DFF cells in module `\ring_modulator':
mapped 1 $_DFF_PN0_ cells to \sky130_fd_sc_hd__dfrtp_1 cells.
Mapping DFF cells in module `\ring_modulator_top':
6. Executing ABC pass (technology mapping using ABC).
6.1. Extracting gate netlist of module `\ring_modulator' to `<abc-temp-dir>/input.blif'..
6.1.1. Executed ABC.
Extracted 706 gates and 738 wires to a netlist network with 32 inputs and 1 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 01:00:48)
ABC: abc 01> empty
ABC: abc 01> source <abc-temp-dir>/abc.script
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lib -w /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
ABC: Parsing finished successfully. Parsing time = 0.06 sec
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__diode_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_0".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_8".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_8".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_bleeder_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__lpflow_inputisolatch_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" has 334 cells (94 skipped: 63 seq; 13 tri-state; 18 no func; 0 dont_use; 0 with 2 outputs; 0 with 3+ outputs). Time = 0.09 sec
ABC: Memory = 19.85 MB. Time = 0.09 sec
ABC: Warning: Detected 9 multi-output cells (for example, "sky130_fd_sc_hd__fa_1").
ABC: + strash
ABC: + &get -n
ABC: + &fraig -x
ABC: + &put
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + &get -n
ABC: + &dch -f
ABC: + &nf
ABC: + &put
ABC: + write_blif <abc-temp-dir>/output.blif
ABC:
ABC: YOSYS_ABC_DONE
6.1.2. Re-integrating ABC results.
ABC RESULTS: sky130_fd_sc_hd__a21boi_0 cells: 2
ABC RESULTS: sky130_fd_sc_hd__a21o_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__a21oi_1 cells: 4
ABC RESULTS: sky130_fd_sc_hd__a22o_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__a22oi_1 cells: 12
ABC RESULTS: sky130_fd_sc_hd__a2bb2oi_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__a31oi_1 cells: 2
ABC RESULTS: sky130_fd_sc_hd__and2_0 cells: 4
ABC RESULTS: sky130_fd_sc_hd__and4_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__clkinv_1 cells: 13
ABC RESULTS: sky130_fd_sc_hd__lpflow_inputiso1p_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__lpflow_isobufsrc_1 cells: 9
ABC RESULTS: sky130_fd_sc_hd__maj3_1 cells: 55
ABC RESULTS: sky130_fd_sc_hd__nand2_1 cells: 127
ABC RESULTS: sky130_fd_sc_hd__nand2b_1 cells: 7
ABC RESULTS: sky130_fd_sc_hd__nand3_1 cells: 8
ABC RESULTS: sky130_fd_sc_hd__nand4_1 cells: 4
ABC RESULTS: sky130_fd_sc_hd__nor2_1 cells: 29
ABC RESULTS: sky130_fd_sc_hd__nor2b_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__o21ai_0 cells: 13
ABC RESULTS: sky130_fd_sc_hd__o21ba_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__o21bai_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__o22a_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__o22ai_1 cells: 6
ABC RESULTS: sky130_fd_sc_hd__o31a_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__o31ai_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__o32a_1 cells: 2
ABC RESULTS: sky130_fd_sc_hd__or3_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__xnor2_1 cells: 95
ABC RESULTS: sky130_fd_sc_hd__xnor3_1 cells: 29
ABC RESULTS: sky130_fd_sc_hd__xor2_1 cells: 32
ABC RESULTS: sky130_fd_sc_hd__xor3_1 cells: 14
ABC RESULTS: internal signals: 705
ABC RESULTS: input signals: 32
ABC RESULTS: output signals: 1
Removing temp directory.
6.2. Extracting gate netlist of module `\ring_modulator_top' to `<abc-temp-dir>/input.blif'..
Don't call ABC as there is nothing to map.
6.2.1. Executed ABC.
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Removing temp directory.
Removing global temp directory.
Removed 0 unused cells and 738 unused wires.
7. Executing HILOMAP pass (mapping to constant drivers).
8. Printing statistics.
=== ring_modulator ===
+----------Local Count, excluding submodules.
| +-Local Area, excluding submodules.
| |
494 - wires
554 - wire bits
5 - public wires
50 - public wire bits
5 - ports
50 - port bits
490 3.93E+03 cells
2 15.014 sky130_fd_sc_hd__a21boi_0
3 22.522 sky130_fd_sc_hd__a21o_1
4 20.019 sky130_fd_sc_hd__a21oi_1
3 26.275 sky130_fd_sc_hd__a22o_1
12 90.086 sky130_fd_sc_hd__a22oi_1
1 8.758 sky130_fd_sc_hd__a2bb2oi_1
2 12.512 sky130_fd_sc_hd__a31oi_1
4 25.024 sky130_fd_sc_hd__and2_0
3 26.275 sky130_fd_sc_hd__and4_1
13 48.797 sky130_fd_sc_hd__clkinv_1
1 25.024 sky130_fd_sc_hd__dfrtp_1
1 6.256 sky130_fd_sc_hd__lpflow_inputiso1p_1
9 56.304 sky130_fd_sc_hd__lpflow_isobufsrc_1
55 550.528 sky130_fd_sc_hd__maj3_1
127 476.707 sky130_fd_sc_hd__nand2_1
7 43.792 sky130_fd_sc_hd__nand2b_1
8 40.038 sky130_fd_sc_hd__nand3_1
4 25.024 sky130_fd_sc_hd__nand4_1
29 108.854 sky130_fd_sc_hd__nor2_1
3 18.768 sky130_fd_sc_hd__nor2b_1
13 65.062 sky130_fd_sc_hd__o21ai_0
1 10.01 sky130_fd_sc_hd__o21ba_1
1 7.507 sky130_fd_sc_hd__o21bai_1
3 26.275 sky130_fd_sc_hd__o22a_1
6 37.536 sky130_fd_sc_hd__o22ai_1
1 8.758 sky130_fd_sc_hd__o31a_1
1 7.507 sky130_fd_sc_hd__o31ai_1
2 20.019 sky130_fd_sc_hd__o32a_1
1 6.256 sky130_fd_sc_hd__or3_1
95 832.048 sky130_fd_sc_hd__xnor2_1
29 653.126 sky130_fd_sc_hd__xnor3_1
32 280.269 sky130_fd_sc_hd__xor2_1
14 332.819 sky130_fd_sc_hd__xor3_1
Chip area for module '\ring_modulator': 3933.772800
of which used for sequential elements: 25.024000 (0.64%)
=== ring_modulator_top ===
+----------Local Count, excluding submodules.
| +-Local Area, excluding submodules.
| |
5 - wires
50 - wire bits
5 - public wires
50 - public wire bits
5 - ports
50 - port bits
1 - submodules
1 - ring_modulator
Chip area for module '\ring_modulator_top': 0.000000
of which used for sequential elements: 0.000000 (nan%)
=== design hierarchy ===
+----------Count including submodules.
| +-Area including submodules.
| |
490 3.93E+03 ring_modulator_top
490 3.93E+03 ring_modulator
+----------Count including submodules.
| +-Area including submodules.
| |
499 - wires
604 - wire bits
10 - public wires
100 - public wire bits
10 - ports
100 - port bits
- - memories
- - memory bits
- - processes
490 3.93E+03 cells
2 15.014 sky130_fd_sc_hd__a21boi_0
3 22.522 sky130_fd_sc_hd__a21o_1
4 20.019 sky130_fd_sc_hd__a21oi_1
3 26.275 sky130_fd_sc_hd__a22o_1
12 90.086 sky130_fd_sc_hd__a22oi_1
1 8.758 sky130_fd_sc_hd__a2bb2oi_1
2 12.512 sky130_fd_sc_hd__a31oi_1
4 25.024 sky130_fd_sc_hd__and2_0
3 26.275 sky130_fd_sc_hd__and4_1
13 48.797 sky130_fd_sc_hd__clkinv_1
1 25.024 sky130_fd_sc_hd__dfrtp_1
1 6.256 sky130_fd_sc_hd__lpflow_inputiso1p_1
9 56.304 sky130_fd_sc_hd__lpflow_isobufsrc_1
55 550.528 sky130_fd_sc_hd__maj3_1
127 476.707 sky130_fd_sc_hd__nand2_1
7 43.792 sky130_fd_sc_hd__nand2b_1
8 40.038 sky130_fd_sc_hd__nand3_1
4 25.024 sky130_fd_sc_hd__nand4_1
29 108.854 sky130_fd_sc_hd__nor2_1
3 18.768 sky130_fd_sc_hd__nor2b_1
13 65.062 sky130_fd_sc_hd__o21ai_0
1 10.01 sky130_fd_sc_hd__o21ba_1
1 7.507 sky130_fd_sc_hd__o21bai_1
3 26.275 sky130_fd_sc_hd__o22a_1
6 37.536 sky130_fd_sc_hd__o22ai_1
1 8.758 sky130_fd_sc_hd__o31a_1
1 7.507 sky130_fd_sc_hd__o31ai_1
2 20.019 sky130_fd_sc_hd__o32a_1
1 6.256 sky130_fd_sc_hd__or3_1
95 832.048 sky130_fd_sc_hd__xnor2_1
29 653.126 sky130_fd_sc_hd__xnor3_1
32 280.269 sky130_fd_sc_hd__xor2_1
14 332.819 sky130_fd_sc_hd__xor3_1
1 3.93E+03 submodules
1 3.93E+03 ring_modulator
Chip area for top module '\ring_modulator_top': 3933.772800
of which used for sequential elements: 25.024000 (0.64%)
9. Executing Verilog backend.
9.1. Executing BMUXMAP pass.
9.2. Executing DEMUXMAP pass.
Dumping module `\ring_modulator'.
Dumping module `\ring_modulator_top'.
10. Executing JSON backend.
============================================
Synthesis complete!
Netlist: build/ring_modulator_top_synth.v
JSON: build/ring_modulator_top_synth.json
============================================
End of script. Logfile hash: e713400855, CPU: user 0.18s system 0.02s, MEM: 62.70 MB peak
Yosys 0.62 (git sha1 7326bb7d6, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)
Time spent: 61% 2x abc (0 sec), 10% 2x stat (0 sec), ...
cd ring_modulator && \
TOP=ring_modulator_top \
SDC=ring_modulator_top.sdc \
OUT_DIR=build \
openroad -exit ../flow/pnr.tcl
OpenROAD 26Q1-990-g15af3a5c0
Features included (+) or not (-): +GPU +GUI +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
============================================
Place & Route: ring_modulator_top
Build dir: build
PDK: /foss/pdks
============================================
[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef, created 14 layers, 25 vias
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef at line 2.
[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef at line 2.
[INFO ODB-0227] LEF file: /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef, created 8 library cells
[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.
Initializing floorplan...
[INFO IFP-0107] Defining die area using utilization: 40.00% and aspect ratio: 1.
[WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.060, 5.440).
[INFO IFP-0001] Added 36 rows of 215 site unithd.
[INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 109.170 109.170 ) um
[INFO IFP-0101] Core BBox: ( 5.060 5.440 ) ( 103.960 103.360 ) um
[INFO IFP-0102] Core area: 9684.288 um^2
[INFO IFP-0103] Total instances area: 3933.773 um^2
[INFO IFP-0104] Effective utilization: 0.406
[INFO IFP-0105] Number of instances: 490
Placing I/O pins...
Found 0 macro blocks.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0001] Number of available slots 386
[INFO PPL-0002] Number of I/O 50
[INFO PPL-0003] Number of I/O w/sink 50
[INFO PPL-0004] Number of I/O w/o sink 0
[INFO PPL-0005] Slots per section 200
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 3304.25 um.
Building power grid...
[INFO PDN-0001] Inserting grid: core_grid
Running placement...
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: ( 0.460 2.720 ) um
[INFO GPL-0004] CoreBBox: ( 5.060 5.440 ) ( 103.960 103.360 ) um
[INFO GPL-0036] Movable instances area: 6386.125 um^2
[INFO GPL-0037] Total instances area: 6386.125 um^2
[INFO GPL-0035] Pin density area adjust: 490.888 um^2
[INFO GPL-0032] ---- Initialize Region: Top-level
[INFO GPL-0006] Number of instances: 490
[INFO GPL-0007] Movable instances: 490
[INFO GPL-0008] Fixed instances: 0
[INFO GPL-0009] Dummy instances: 0
[INFO GPL-0010] Number of nets: 524
[INFO GPL-0011] Number of pins: 1717
[INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 109.170 109.170 ) um
[INFO GPL-0013] Core BBox: ( 5.060 5.440 ) ( 103.960 103.360 ) um
[INFO GPL-0016] Core area: 9684.288 um^2
[INFO GPL-0014] Region name: top-level.
[INFO GPL-0015] Region area: 9684.288 um^2
[INFO GPL-0017] Fixed instances area: 0.000 um^2
[INFO GPL-0018] Movable instances area: 6877.013 um^2
[INFO GPL-0019] Utilization: 71.012 %
[INFO GPL-0020] Standard cells area: 6877.013 um^2
[INFO GPL-0021] Large instances area: 0.000 um^2
[INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
[INFO GPL-0051] Source of initial instance position counters:
Odb location = 0 Core center = 490 Region center = 0
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000010 HPWL: 5749200
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000006 HPWL: 4713313
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000009 HPWL: 4735765
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000012 HPWL: 4749788
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000004 HPWL: 4750385
[INFO GPL-0033] ---- Initialize Nesterov Region: Top-level
[WARNING GPL-0302] Target density 0.7000 is too low for the available free area.
Automatically adjusting to uniform density 0.7200.
[INFO GPL-0023] Placement target density: 0.7200
[INFO GPL-0024] Movable insts average area: 14.035 um^2
[INFO GPL-0025] Ideal bin area: 19.493 um^2
[INFO GPL-0026] Ideal bin count: 496
[INFO GPL-0027] Total bin area: 9684.288 um^2
[INFO GPL-0028] Bin count (X, Y): 16 , 16
[INFO GPL-0029] Bin size (W * H): 6.181 * 6.120 um
[INFO GPL-0030] Number of bins: 256
[INFO GPL-0007] ---- Execute Nesterov Global Placement.
[INFO GPL-0031] HPWL: Half-Perimeter Wirelength
Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group
---------------------------------------------------------------
0 | 0.9721 | 1.690016e+03 | +0.00% | 1.71e-15 |
10 | 0.9697 | 1.703130e+03 | +0.78% | 2.78e-15 |
20 | 0.9686 | 1.706909e+03 | +0.22% | 4.52e-15 |
30 | 0.9688 | 1.704814e+03 | -0.12% | 7.37e-15 |
40 | 0.9688 | 1.704243e+03 | -0.03% | 1.20e-14 |
50 | 0.9686 | 1.705145e+03 | +0.05% | 1.96e-14 |
60 | 0.9686 | 1.704798e+03 | -0.02% | 3.18e-14 |
70 | 0.9686 | 1.704741e+03 | -0.00% | 5.19e-14 |
80 | 0.9686 | 1.705189e+03 | +0.03% | 8.45e-14 |
90 | 0.9685 | 1.705610e+03 | +0.02% | 1.38e-13 |
100 | 0.9684 | 1.706827e+03 | +0.07% | 2.24e-13 |
110 | 0.9683 | 1.710250e+03 | +0.20% | 3.65e-13 |
120 | 0.9681 | 1.718186e+03 | +0.46% | 5.95e-13 |
130 | 0.9676 | 1.735125e+03 | +0.99% | 9.69e-13 |
140 | 0.9671 | 1.767713e+03 | +1.88% | 1.58e-12 |
150 | 0.9670 | 1.829738e+03 | +3.51% | 2.57e-12 |
160 | 0.9584 | 1.932507e+03 | +5.62% | 4.19e-12 |
170 | 0.9549 | 2.101337e+03 | +8.74% | 6.82e-12 |
180 | 0.9410 | 2.374973e+03 | +13.02% | 1.11e-11 |
190 | 0.9241 | 2.695306e+03 | +13.49% | 1.81e-11 |
200 | 0.8952 | 3.015124e+03 | +11.87% | 2.95e-11 |
210 | 0.8703 | 3.352696e+03 | +11.20% | 4.80e-11 |
220 | 0.8422 | 3.771854e+03 | +12.50% | 7.82e-11 |
230 | 0.8046 | 4.166832e+03 | +10.47% | 1.27e-10 |
240 | 0.7689 | 4.575070e+03 | +9.80% | 2.07e-10 |
250 | 0.7257 | 5.023283e+03 | +9.80% | 3.38e-10 |
260 | 0.6900 | 5.371840e+03 | +6.94% | 5.51e-10 |
270 | 0.6406 | 5.790993e+03 | +7.80% | 8.97e-10 |
280 | 0.5907 | 6.122783e+03 | +5.73% | 1.46e-09 |
290 | 0.5416 | 6.435077e+03 | +5.10% | 2.38e-09 |
300 | 0.4851 | 6.747776e+03 | +4.86% | 3.87e-09 |
310 | 0.4371 | 6.995606e+03 | +3.67% | 6.31e-09 |
320 | 0.3833 | 7.168243e+03 | +2.47% | 1.03e-08 |
330 | 0.3343 | 7.383342e+03 | +3.00% | 1.62e-08 |
340 | 0.3045 | 7.587597e+03 | +2.77% | 2.39e-08 |
350 | 0.2686 | 7.708573e+03 | +1.59% | 3.53e-08 |
360 | 0.2366 | 7.792539e+03 | +1.09% | 5.19e-08 |
370 | 0.2059 | 7.859382e+03 | +0.86% | 7.65e-08 |
380 | 0.1861 | 7.933469e+03 | +0.94% | 1.13e-07 |
390 | 0.1690 | 7.994180e+03 | +0.77% | 1.66e-07 |
400 | 0.1493 | 8.025525e+03 | +0.39% | 2.45e-07 |
410 | 0.1229 | 8.054774e+03 | +0.36% | 3.60e-07 |
420 | 0.1005 | 8.080061e+03 | +0.31% | 5.31e-07 |
421 | 0.0993 | 8.084645e+03 | | 5.74e-07 |
---------------------------------------------------------------
[INFO GPL-1001] Global placement finished at iteration 421
[INFO GPL-1002] Placed Cell Area 6877.0129
[INFO GPL-1003] Available Free Area 9684.2880
[INFO GPL-1004] Minimum Feasible Density 0.7200 (cell_area / free_area)
[INFO GPL-1006] Suggested Target Densities:
[INFO GPL-1007] - For 90% usage of free space: 0.7890
[INFO GPL-1008] - For 80% usage of free space: 0.8877
[INFO GPL-1014] Final placement area: 6877.01 (+0.00%)
Placement Analysis
---------------------------------
total displacement 877.2 u
average displacement 1.8 u
max displacement 5.5 u
original HPWL 8130.1 u
legalized HPWL 8971.7 u
delta HPWL 10 %
Running clock tree synthesis...
[WARNING EST-0027] no estimated parasitics. Using wire load models.
Iteration | Area | Resized | Buffers | Nets repaired | Remaining
---------------------------------------------------------------------
0 | +0.0% | 0 | 0 | 0 | 524
final | +0.0% | 0 | 0 | 0 | 0
---------------------------------------------------------------------
[INFO CTS-0050] Root buffer is sky130_fd_sc_hd__clkbuf_16.
[INFO CTS-0051] Sink buffer is sky130_fd_sc_hd__clkbuf_4.
[INFO CTS-0052] The following clock buffers will be used for CTS:
sky130_fd_sc_hd__clkbuf_4
sky130_fd_sc_hd__clkbuf_8
sky130_fd_sc_hd__clkbuf_16
[INFO CTS-0049] Characterization buffer is sky130_fd_sc_hd__clkbuf_16.
[INFO CTS-0007] Net "clk" found for clock "clk".
[WARNING CTS-0041] Net "clk" has 1 sinks. Skipping...
[WARNING CTS-0083] No clock nets have been found.
[INFO CTS-0008] TritonCTS found 0 clock nets.
[WARNING CTS-0082] No valid clock nets in the design.
[WARNING EST-0027] no estimated parasitics. Using wire load models.
Placement Analysis
---------------------------------
total displacement 0.0 u
average displacement 0.0 u
max displacement 0.0 u
original HPWL 8971.7 u
legalized HPWL 8971.7 u
delta HPWL 0 %
Running routing...
[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
Units: 1000
Number of layers: 13
Number of macros: 445
Number of vias: 29
Number of viarulegen: 25
[INFO DRT-0150] Reading design.
Design: ring_modulator_top
Die area: ( 0 0 ) ( 109170 109170 )
Number of track patterns: 12
Number of DEF vias: 0
Number of components: 490
Number of terminals: 52
Number of snets: 2
Number of nets: 524
[INFO DRT-0167] List of default vias:
Layer via
default via: M1M2_PR
Layer via2
default via: M2M3_PR
Layer via3
default via: M3M4_PR
Layer via4
default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
[INFO DRT-0164] Number of unique instances = 57.
[INFO DRT-0168] Init region query.
[INFO DRT-0024] Complete FR_MASTERSLICE.
[INFO DRT-0024] Complete licon.
[INFO DRT-0024] Complete li1.
[INFO DRT-0024] Complete mcon.
[INFO DRT-0024] Complete met1.
[INFO DRT-0024] Complete via.
[INFO DRT-0024] Complete met2.
[INFO DRT-0024] Complete via2.
[INFO DRT-0024] Complete met3.
[INFO DRT-0024] Complete via3.
[INFO DRT-0024] Complete met4.
[INFO DRT-0024] Complete via4.
[INFO DRT-0024] Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] licon shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 11903.
[INFO DRT-0033] mcon shape region query size = 0.
[INFO DRT-0033] met1 shape region query size = 1535.
[INFO DRT-0033] via shape region query size = 370.
[INFO DRT-0033] met2 shape region query size = 272.
[INFO DRT-0033] via2 shape region query size = 296.
[INFO DRT-0033] met3 shape region query size = 222.
[INFO DRT-0033] via3 shape region query size = 296.
[INFO DRT-0033] met4 shape region query size = 90.
[INFO DRT-0033] via4 shape region query size = 8.
[INFO DRT-0033] met5 shape region query size = 16.
[INFO DRT-0165] Start pin access.
[INFO DRT-0078] Complete 457 pins.
[INFO DRT-0081] Complete 57 unique inst patterns.
[INFO DRT-0084] Complete 302 groups.
#scanned instances = 490
#unique instances = 57
#stdCellGenAp = 1624
#stdCellValidPlanarAp = 4
#stdCellValidViaAp = 1344
#stdCellPinNoAp = 0
#stdCellPinCnt = 1667
#instTermValidViaApCnt = 0
#macroGenAp = 0
#macroValidPlanarAp = 0
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:10, elapsed time = 00:00:10, memory = 230.09 (MB), peak = 229.98 (MB)
[INFO DRT-0157] Number of guides: 3396
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 15 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 15 STEP 6900 ;
[INFO DRT-0028] Complete FR_MASTERSLICE.
[INFO DRT-0028] Complete licon.
[INFO DRT-0028] Complete li1.
[INFO DRT-0028] Complete mcon.
[INFO DRT-0028] Complete met1.
[INFO DRT-0028] Complete via.
[INFO DRT-0028] Complete met2.
[INFO DRT-0028] Complete via2.
[INFO DRT-0028] Complete met3.
[INFO DRT-0028] Complete via3.
[INFO DRT-0028] Complete met4.
[INFO DRT-0028] Complete via4.
[INFO DRT-0028] Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035] Complete FR_MASTERSLICE (guide).
[INFO DRT-0035] Complete licon (guide).
[INFO DRT-0035] Complete li1 (guide).
[INFO DRT-0035] Complete mcon (guide).
[INFO DRT-0035] Complete met1 (guide).
[INFO DRT-0035] Complete via (guide).
[INFO DRT-0035] Complete met2 (guide).
[INFO DRT-0035] Complete via2 (guide).
[INFO DRT-0035] Complete met3 (guide).
[INFO DRT-0035] Complete via3 (guide).
[INFO DRT-0035] Complete met4 (guide).
[INFO DRT-0035] Complete via4 (guide).
[INFO DRT-0035] Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] licon guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 1280.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 1039.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 511.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 0.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 0.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 230.09 (MB), peak = 229.98 (MB)
[INFO DRT-0245] skipped writing guide updates to database.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 1791 vertical wires in 1 frboxes and 1039 horizontal wires in 1 frboxes.
[INFO DRT-0186] Done with 151 vertical wires in 1 frboxes and 305 horizontal wires in 1 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 230.28 (MB), peak = 230.17 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 230.41 (MB), peak = 230.17 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:01, memory = 234.31 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:01, memory = 234.31 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:01, memory = 234.40 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:01, memory = 234.40 (MB).
Completing 50% with 53 violations.
elapsed time = 00:00:03, memory = 234.40 (MB).
Completing 60% with 53 violations.
elapsed time = 00:00:03, memory = 234.40 (MB).
Completing 70% with 99 violations.
elapsed time = 00:00:05, memory = 234.40 (MB).
Completing 80% with 99 violations.
elapsed time = 00:00:06, memory = 234.40 (MB).
Completing 100% with 174 violations.
elapsed time = 00:00:07, memory = 234.40 (MB).
[INFO DRT-0199] Number of violations = 189.
Viol/Layer met1 met2
Metal Spacing 40 7
Recheck 12 3
Short 120 7
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:07, memory = 577.62 (MB), peak = 577.45 (MB)
Total wire length = 10817 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 5475 um.
Total wire length on LAYER met2 = 5326 um.
Total wire length on LAYER met3 = 16 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 3377.
Up-via summary (total 3377):
-----------------------
FR_MASTERSLICE 0
li1 1690
met1 1683
met2 4
met3 0
met4 0
-----------------------
3377
[INFO DRT-0195] Start 1st optimization iteration.
Completing 10% with 189 violations.
elapsed time = 00:00:00, memory = 577.62 (MB).
Completing 20% with 189 violations.
elapsed time = 00:00:00, memory = 577.62 (MB).
Completing 30% with 189 violations.
elapsed time = 00:00:00, memory = 577.62 (MB).
Completing 40% with 189 violations.
elapsed time = 00:00:00, memory = 577.62 (MB).
Completing 50% with 172 violations.
elapsed time = 00:00:01, memory = 577.62 (MB).
Completing 60% with 172 violations.
elapsed time = 00:00:01, memory = 577.62 (MB).
Completing 70% with 153 violations.
elapsed time = 00:00:03, memory = 577.62 (MB).
Completing 80% with 153 violations.
elapsed time = 00:00:03, memory = 577.62 (MB).
Completing 100% with 75 violations.
elapsed time = 00:00:04, memory = 577.62 (MB).
[INFO DRT-0199] Number of violations = 75.
Viol/Layer met1 met2
Metal Spacing 23 2
Short 50 0
[INFO DRT-0267] cpu time = 00:00:04, elapsed time = 00:00:04, memory = 577.66 (MB), peak = 577.45 (MB)
Total wire length = 10699 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 5440 um.
Total wire length on LAYER met2 = 5230 um.
Total wire length on LAYER met3 = 28 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 3337.
Up-via summary (total 3337):
-----------------------
FR_MASTERSLICE 0
li1 1687
met1 1642
met2 8
met3 0
met4 0
-----------------------
3337
[INFO DRT-0195] Start 2nd optimization iteration.
Completing 10% with 75 violations.
elapsed time = 00:00:00, memory = 577.66 (MB).
Completing 20% with 75 violations.
elapsed time = 00:00:00, memory = 577.66 (MB).
Completing 30% with 75 violations.
elapsed time = 00:00:00, memory = 577.66 (MB).
Completing 40% with 75 violations.
elapsed time = 00:00:00, memory = 577.66 (MB).
Completing 50% with 72 violations.
elapsed time = 00:00:00, memory = 577.66 (MB).
Completing 60% with 72 violations.
elapsed time = 00:00:01, memory = 577.66 (MB).
Completing 70% with 77 violations.
elapsed time = 00:00:01, memory = 577.66 (MB).
Completing 80% with 77 violations.
elapsed time = 00:00:02, memory = 577.66 (MB).
Completing 100% with 32 violations.
elapsed time = 00:00:04, memory = 577.66 (MB).
[INFO DRT-0199] Number of violations = 32.
Viol/Layer met1
Metal Spacing 11
Short 21
[INFO DRT-0267] cpu time = 00:00:04, elapsed time = 00:00:04, memory = 577.72 (MB), peak = 577.61 (MB)
Total wire length = 10711 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 5433 um.
Total wire length on LAYER met2 = 5255 um.
Total wire length on LAYER met3 = 22 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 3349.
Up-via summary (total 3349):
-----------------------
FR_MASTERSLICE 0
li1 1686
met1 1657
met2 6
met3 0
met4 0
-----------------------
3349
[INFO DRT-0195] Start 3rd guides tiles iteration.
Completing 10% with 32 violations.
elapsed time = 00:00:00, memory = 577.72 (MB).
Completing 20% with 32 violations.
elapsed time = 00:00:00, memory = 577.72 (MB).
Completing 30% with 32 violations.
elapsed time = 00:00:00, memory = 577.72 (MB).
Completing 50% with 32 violations.
elapsed time = 00:00:00, memory = 577.72 (MB).
Completing 60% with 9 violations.
elapsed time = 00:00:01, memory = 577.72 (MB).
Completing 70% with 9 violations.
elapsed time = 00:00:01, memory = 577.72 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:01, memory = 577.72 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:01, memory = 577.72 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 577.72 (MB), peak = 577.61 (MB)
Total wire length = 10716 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 5252 um.
Total wire length on LAYER met2 = 5274 um.
Total wire length on LAYER met3 = 189 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 3360.
Up-via summary (total 3360):
-----------------------
FR_MASTERSLICE 0
li1 1686
met1 1650
met2 24
met3 0
met4 0
-----------------------
3360
[INFO DRT-0198] Complete detail routing.
Total wire length = 10716 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 5252 um.
Total wire length on LAYER met2 = 5274 um.
Total wire length on LAYER met3 = 189 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 3360.
Up-via summary (total 3360):
-----------------------
FR_MASTERSLICE 0
li1 1686
met1 1650
met2 24
met3 0
met4 0
-----------------------
3360
[INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:17, memory = 577.78 (MB), peak = 577.61 (MB)
[INFO DRT-0180] Post processing.
Adding filler cells...
[INFO DPL-0001] Placed 1225 filler instances.
Running final analysis...
[WARNING EST-0018] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance.
Design area 3934 um^2 41% utilization.
Writing outputs...
============================================
Place & Route complete!
DEF: build/ring_modulator_top.def
Netlist: build/ring_modulator_top_pnr.v
Reports: build/ring_modulator_top_*.rpt
============================================
cd ring_modulator && \
klayout -zz -r ../flow/def2gds.rb \
-rd def_file=build/ring_modulator_top.def \
-rd gds_file=build/ring_modulator_top.gds
============================================
DEF to GDS Conversion
============================================
Loading standard cell GDS...
Reading DEF: build/ring_modulator_top.def
Writing GDS: build/ring_modulator_top.gds
============================================
GDS written successfully!
File size: 4737040 bytes
============================================
Ring Modulator Top build complete: ring_modulator/build/ring_modulator_top.gds
/foss/designs/ring_modulator_final_proyect >
Run final DRC/LVS on your design¶
run_magic_drc.tcl¶
To perform the final physical verification, I prepared a run_magic_drc.tcl script to run a Design Rule Check (DRC) in Magic using the final DEF generated by OpenROAD. The script first loads the SKY130 technology and standard-cell LEF files, then reads the final physical design from ring_modulator_top.def. After loading and expanding the top cell, Magic activates the DRC engine and checks the complete layout against the manufacturing rules of the process.
At the end of the script, Magic counts the total number of DRC violations and prints the result. If any errors are found, it also lists the reasons for those violations, which helps identify issues such as spacing, width, or geometry problems in the layout. This step is important because it confirms whether the final routed design is physically valid for fabrication.
# run_magic_drc.tcl
# DRC from DEF using Magic + SKY130A
crashbackups stop
drc off
lef read /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef
lef read /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
def read ./results/openroad/ring_modulator_top.def
load ring_modulator_top
select top cell
expand
drc on
drc catchup
drc check
set drc_count [drc count total]
puts "DRC TOTAL ERRORS: $drc_count"
if {$drc_count > 0} {
drc listall why
}
quit -noprompt
magic -dnull -noconsole -rcfile /foss/pdks/sky130A/libs.tech/magic/sky130A.magicrc run_magic_drc.tcl | tee results/openroad/magic_drc.log
run_magic_extract.tcl¶
For this, a run_magic_extract.tcl script was also prepared, generating the file ring_modulator_top_layout.spice.
Then, Netgen is used to compare the extracted layout netlist with the synthesized reference netlist.
The final objective of these steps is to complete the design verification with two checks:
- DRC clean, meaning there are no physical rule violations
- LVS correct, meaning the final layout matches the intended circuit
If both checks pass, the design can be considered a verified final version.
# run_magic_extract.tcl
# Extract SPICE from DEF using Magic for LVS
crashbackups stop
drc off
lef read /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef
lef read /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
def read ./results/openroad/ring_modulator_top.def
load ring_modulator_top
select top cell
expand
extract do local
extract no all
extract all
ext2spice lvs
ext2spice -p ./results/openroad
ext2spice -o ./results/openroad/ring_modulator_top_layout.spice
quit -noprompt
magic -dnull -noconsole -rcfile /foss/pdks/sky130A/libs.tech/magic/sky130A.magicrc run_magic_extract.tcl | tee results/openroad/magic_extract.log
LVS Verification with Netgen¶
After extracting the layout netlist from Magic, the next step is to run LVS (Layout Versus Schematic) using Netgen. The goal of LVS is to verify that the circuit implemented in the physical layout is electrically equivalent to the reference design generated during synthesis.
The Netgen command compares two netlists: the SPICE netlist extracted from the layout (ring_modulator_top_layout.spice) and the synthesized reference netlist (ring_modulator_top_synth.v). The SKY130 setup file (sky130A_setup.tcl) is also provided so that Netgen understands the device models and equivalences defined by the PDK.
netgen -batch lvs \
"./results/openroad/ring_modulator_top_layout.spice ring_modulator_top" \
"./ring_modulator_top_synth.v ring_modulator_top" \
/foss/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl \
./results/openroad/lvs.log
Once the Netgen LVS command was executed, the final report showed the message Circuits match uniquely. This confirms that the netlist extracted from the layout matches the synthesized reference netlist, meaning that the physical implementation is electrically equivalent to the intended circuit design. In other words, the LVS verification passed successfully and the design can be considered consistent between schematic and layout.
Final result:
Circuits match uniquely.
Chip Documentation¶
Functionality¶
The chip implements a digital ring modulator. Its function is to multiply two signed input signals, signal_in and carrier_in, and generate a modulated output mod_out. Internally, the design performs a signed multiplication between both 16-bit input samples and scales the result to keep the output within the same 16-bit range.
This type of circuit is useful for signal processing and audio applications, where ring modulation produces new frequency components based on the interaction between the carrier and modulation signals. In this implementation, the design is synchronous and processes the input samples on the rising edge of the system clock.
Pin Assignments¶
The main chip interface includes the following signals:
clk: system clock inputrst_n: active-low reset inputsignal_in[15:0]: 16-bit signed input signalcarrier_in[15:0]: 16-bit signed carrier signalmod_out[15:0]: 16-bit signed output signal
If power pins are explicitly used, the design also includes:
vccd1: power supplyvssd1: ground
Interface Details¶
The design is fully synchronous and operates with a single clock domain.
- Clock frequency: the design was constrained with a 20 ns clock period, equivalent to 50 MHz
- Reset:
rst_nis an active-low synchronous reset - Input format: signed 16-bit values
- Output format: signed 16-bit value
- Timing reference: all inputs and outputs are referenced to
clk - Input delay used in constraints: 2 ns
- Output delay used in constraints: 2 ns
- Clock uncertainty: 0.2 ns
This chip does not use a serial protocol such as UART, SPI, or I2C, so parameters such as baud rate are not applicable in this version. The interface is a direct parallel sample-based interface driven by the system clock.
Chip Packaging Overview¶
After completing the physical design and verification stages (DRC and LVS), the next step in the chip development process is packaging. Chip packaging is the process of placing the silicon die inside a protective enclosure that provides mechanical protection, electrical connections to the outside world, and proper thermal dissipation.
There are several types of chip packages depending on the application, manufacturing cost, and assembly requirements. Some common categories include through-hole packages (such as DIP), surface mount packages (such as SOIC or QFN), and more complex packages like BGA used in high-density designs.
Based on the material presented during the class and considering simplicity, availability, and ease of prototyping, I decided to use a Surface Mount Package (SMD) for the chip. Specifically, the chosen package is an SOIC-8 (Small Outline Integrated Circuit, 8 pins). This type of package is widely used, compact, easy to solder, and well suited for small designs with a limited number of input and output pins. It also integrates well with standard PCB manufacturing and assembly processes.
Verification test plan¶
Once the chip is fabricated and packaged, the first step in testing would be a basic power-on check. Before performing any measurements, I would connect the chip to the power supply and verify that the current consumption is within the expected range. The goal of this first step is simply to ensure that the chip powers up safely and that there are no obvious faults such as excessive current draw, overheating, or, in practical terms, that the chip does not “smoke” when connected to power.
After confirming that the device powers up correctly, I would proceed with functional testing. I would use a signal generator to apply several sinusoidal input signals to the signal_in and carrier_in inputs of the chip. By varying the frequencies and amplitudes of these sine waves, I could observe how the circuit performs under different operating conditions.
Finally, I would connect the output of the chip to an oscilloscope to analyze the resulting waveform. Since the circuit implements a ring modulation operation, the output should show the expected modulation products derived from the multiplication of the input signals. By comparing the observed waveform with the expected theoretical behavior, I could confirm whether the chip is functioning correctly.
Kicad¶
The circuit schematic of the ring modulator module was designed using KiCad’s schematic editor (Eeschema). The objective was to integrate the analog ring modulation core together with the signal conditioning stages and the power supply section.
The schematic diagram clearly shows the signal flow from the input stages to the ring modulator core and finally to the output amplifier.
In the Eurorack standard, the available power rails are +12 V, -12 V, +5 V, and GND. In this design, the +5 V rail is used to power the digital part of the circuit. From this voltage, an MCP1700 regulator converts 5 V down to 1.8 V, which is the voltage required by the RM001 microcontroller / digital chip.
In this way, the analog section can operate with the typical Eurorack supply, while the digital section receives a lower and stable voltage suitable for proper operation. This also helps integrate the circuit correctly into a real modular synthesizer environment.
Several capacitors (100 nF and 10 µF) are used for power supply decoupling and filtering, improving stability and reducing noise.
Once the schematic was completed and verified, the design was transferred to KiCad’s PCB editor (PCBnew) to create the printed circuit board.
This view shows the final routing of the PCB, including component placement, signal traces, and ground areas.
KiCad also provides a 3D viewer, which allows visual inspection of the assembled PCB before manufacturing.
The 3D viewer generates a real-time rendering of the PCB using the footprints’ 3D models.
The design also includes a Bill of Materials (BOM) that lists all required components.
The BOM ensures that all components required to assemble the module are properly specified and organized before manufacturing.
