Final Project: RM001 - Ring Modulator¶
Project overview¶
My final project is the design of a ring modulator implemented as an integrated circuit using the Sky130 open-source technology and toolchain. The main goal of this project was to go through the complete chip design workflow, from the behavioral description of the circuit to the generation of its physical layout, while understanding and documenting each stage of the process.
A ring modulator combines two input signals, usually called carrier and modulator, and produces a new signal containing the sum and difference frequencies of both inputs. This creates a distinctive metallic, bell-like, and non-harmonic sound that is very common in synthesizers and experimental audio electronics.
The initial idea¶
For this project, I implemented the ring modulator concept as a digital multiplication between two signals, creating a hardware block capable of producing the characteristic modulation effect.
The system receives two signed digital input signals, signal_in and carrier_in, and produces one output, mod_out. At a conceptual level, the circuit behaves like a digital multiplier that combines both signals sample by sample. This was the starting point that allowed me to translate an audio idea into a hardware design.
Carrier In ────> Buffer ───> ─┐
├─> Ring Mod ─> Gain ─> Buffer ─> Out
Modulator In ──> Buffer ───> ─┘
V(out) <+ vout_offset + k * V(in_car) * V(in_mod);
Hardware description¶
The starting point of the design was the Verilog description of the circuit. This step was important because it allowed me to transform the original concept into a concrete hardware structure that could move through the next stages of the chip design flow.
At this stage, I was not yet dealing with the physical chip itself, but with the logical description of how the system should behave. Defining the project in Verilog helped me understand how a sound-processing idea can be expressed as digital logic.
module ring_modulator (
input wire clk,
input wire rst_n,
input wire signed [15:0] signal_in,
input wire signed [15:0] carrier_in,
output reg signed [15:0] mod_out
);
reg signed [31:0] product;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
product <= 32'sd0;
mod_out <= 16'sd0;
end else begin
product <= signal_in * carrier_in;
mod_out <= product[30:15];
end
end
endmodule
Logic synthesis¶
Once the RTL design was defined, the next step was logic synthesis using Yosys. In this stage, the Verilog code was translated into a gate-level netlist and mapped to the Sky130 standard-cell library.
This was a key moment in the project, because it showed how an abstract circuit description can become a real implementation based on a specific semiconductor technology. It was also one of the first times where the design stopped being only an idea and became a structure made of actual standard cells.
Physical implementation¶
After synthesis, I worked on the physical implementation of the design using OpenROAD. In this stage, the logical netlist is transformed into a physical structure: standard cells are placed inside the design area and the interconnections between them are routed to generate the final layout. This is the moment when the project starts to become visible as a real chip. The result of this stage is the final GDS file, which represents the complete physical description of the integrated circuit.
Design area 10793 um^2 43% utilization.
Startpoint: carrier_in[5] (input port clocked by clk)
Endpoint: _2607_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
5.00 5.00 ^ input external delay
0.00 5.00 ^ carrier_in[5] (in)
0.13 5.13 ^ _1564_/X (sky130_fd_sc_hd__and2_0)
0.44 5.57 v _1639_/X (sky130_fd_sc_hd__xor3_1)
0.39 5.96 v _1643_/X (sky130_fd_sc_hd__xor3_1)
0.10 6.06 ^ _1644_/Y (sky130_fd_sc_hd__nand2_1)
0.41 6.47 v _1663_/X (sky130_fd_sc_hd__xnor3_1)
0.37 6.84 v _1664_/X (sky130_fd_sc_hd__maj3_1)
0.38 7.22 v _1750_/X (sky130_fd_sc_hd__xor3_1)
0.11 7.33 ^ _1751_/Y (sky130_fd_sc_hd__o22ai_1)
0.09 7.43 ^ _1752_/X (sky130_fd_sc_hd__a21o_1)
0.05 7.48 v _1756_/Y (sky130_fd_sc_hd__a21oi_1)
0.34 7.82 v _1757_/X (sky130_fd_sc_hd__maj3_1)
0.20 8.02 ^ _1761_/Y (sky130_fd_sc_hd__o221ai_1)
0.16 8.18 ^ _1764_/X (sky130_fd_sc_hd__a211o_1)
0.06 8.25 v _1910_/Y (sky130_fd_sc_hd__a211oi_1)
0.20 8.45 ^ _2046_/Y (sky130_fd_sc_hd__o211ai_1)
0.11 8.56 v _2170_/Y (sky130_fd_sc_hd__a211oi_1)
0.22 8.78 v _2226_/X (sky130_fd_sc_hd__o21a_1)
0.36 9.14 ^ _2337_/Y (sky130_fd_sc_hd__o311ai_0)
0.16 9.30 v _2388_/Y (sky130_fd_sc_hd__a21boi_0)
0.22 9.52 ^ _2432_/Y (sky130_fd_sc_hd__o21ai_0)
0.12 9.65 v _2482_/Y (sky130_fd_sc_hd__a21oi_1)
0.18 9.83 ^ _2524_/Y (sky130_fd_sc_hd__o21ai_0)
0.10 9.93 v _2527_/Y (sky130_fd_sc_hd__nand2_1)
0.36 10.29 v _2556_/X (sky130_fd_sc_hd__maj3_1)
0.13 10.42 v _2575_/Y (sky130_fd_sc_hd__xnor2_1)
0.00 10.42 v _2607_/D (sky130_fd_sc_hd__dfrtp_1)
10.42 data arrival time
50.00 50.00 clock clk (rise edge)
0.00 50.00 clock network delay (ideal)
-0.50 49.50 clock uncertainty
0.00 49.50 clock reconvergence pessimism
49.50 ^ _2607_/CLK (sky130_fd_sc_hd__dfrtp_1)
-0.12 49.38 library setup time
49.38 data required time
---------------------------------------------------------
49.38 data required time
-10.42 data arrival time
---------------------------------------------------------
38.96 slack (MET)
Verification¶
Verification was a very important part of my work. I performed Design Rule Check (DRC) using Magic to verify that the layout respected the manufacturing rules of the Sky130 process. I also performed Layout Versus Schematic (LVS) verification with Netgen, confirming that the final layout matched the intended circuit.
Finally, I inspected the result visually in KLayout, exploring the generated GDS file and understanding the structure of the final layout. These steps were essential to confirm that the design was not only complete, but also coherent and manufacturable.
From chip to product¶
The project did not stop at the chip itself. In addition to the integrated circuit design, I also worked on the PCB design and on the concept of the final product as a functional Eurorack module.
Within the Eurorack standard, the available power rails are +12 V, -12 V, +5 V, and GND. In this design, the +5 V rail is used to supply the digital section of the circuit. An MCP1700 regulator then converts those 5 V into 1.8 V, which is the voltage required by the RM001 digital chip.
This allows the analog section to operate within the typical Eurorack environment, while the digital part receives a stable lower voltage adapted to its requirements. In this way, the module can be integrated more naturally into a real modular synthesizer system.
At this stage, I did not include dedicated test connections or test points on the PCB. The board was mainly focused on validating the main signal path and building a first functional prototype of the module. However, in a future revision it would be interesting to improve the design by adding test points for debugging and measurement, making the board easier to characterize and troubleshoot.
A further possible improvement would be to implement a dual ring modulator, allowing two independent ring modulation channels in the same Eurorack module. This would make better use of the available panel space and open the door to a richer and more flexible musical device.
This part is especially meaningful to me, because it connects microelectronics design with a real and usable object, closely related to my interest in sound synthesis and musical electronics. Thinking about the project as a complete Eurorack module allowed me to move beyond the chip itself and imagine how the circuit could live inside a real system, with power supply, audio inputs and outputs, PCB integration, and interaction with other synthesizer modules.
To make the project easier to replicate in other maker spaces or laboratories, I tried to use 1206 SMD components available in the Fab Lab inventory. This decision makes the assembly more accessible and easier to reproduce, while avoiding, as much as possible, parts that are difficult to source or too specific.
The PCB was designed as a single-layer board and manufactured by milling it on our CNC machine, following a local, fast, and affordable production approach. In this way, the circuit can be fabricated and assembled using the kind of tools commonly found in a Fab Lab, reinforcing the idea of a module that can be easily replicated in other labs.
Front Panel Manufacturing Process¶
The front panel of the module was manufactured at A Industriosa using a 2 mm thick aluminum sheet. First, the design was prepared with the final panel dimensions of 128.5 × 50 mm, following the module format. Then, the CNC machine was used to cut the piece and accurately machine the holes for the jacks and mounting screws.
Once the panel was cut and machined, attention was given to its visual finish. To add color and character to the front panel, a graphic design was prepared and engraved directly onto the metal using the diode laser machine. In this way, the panel not only fulfills its mechanical and structural function, but also gives a distinctive visual identity to the final module.
Future perspective¶
This broader view of the project opens a very inspiring direction for the future. It makes me think about the possibility of creating much more complete products, combining chip design, electronics, interface, and product development. It also makes me imagine, from a new perspective, how some of the legendary synthesizers in the history of electronic music may have been designed and manufactured. In that sense, this project has not only been a way to learn a technology, but also a way to get closer to understanding how an electronic idea can become a real musical instrument.
What I learned¶
Beyond the technical results, my work during this project focused on understanding, connecting, and documenting every stage of the open-source chip design flow, from hardware description to final verification, while also projecting the circuit as part of a functional product.
This gave me a much clearer view of how an initial idea can evolve into a complete design, both at chip level and as part of a full electronic system. Little by little, session after session, I felt that I was getting closer to the fascinating world of open-source silicon design.
Acknowledgements¶
I am sincerely grateful to the Fab Futures professors and mentors, Jennifer, Andreas, Alex, Neil, Julian, and Jean-Michel, as well as my classmates, for making this experience possible.
Their explanations, patience, feedback, and shared enthusiasm made a huge difference. Learning something as challenging as microelectronics becomes much more meaningful when it happens in such a generous and collaborative environment.