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Session 4: Fabrication Basics

Link to class

My learnings

Project homework:

Block diagram: Sketch your project’s architecture showing major modules and data flow (e.g., Pocket Synth: button inputs → tone selector → oscillator → PWM output)

A Physical Unclonable Function (PUF) is a “digital fingerprint” for semiconductor devices, using unique, uncontrollable physical variations in silicon to generate secure keys and authenticate chips. It provides a secure, unclonable identifier for microprocessors.

Strong PUFs generate a massive set of Challenge-Response Pairs (CRPs) based on manufacturing process variations (delays, capacitance), making them suitable for authentication, as opposed to weak PUFs used for key generation.

For each manufactured PUF installed on a device, a huge amount of pairs are recorded in a database. This is the digital device fingerprint. Once deployed, the device generates a challenge, submit it to the PUF and sends the challenge-response pair to the server. Server answers with a Go-NoGo and mark the pair as used in the database, to prevent replay attacks.

Implementing strong PUFs in Verilog often involves Arbiter-based or Ring Oscillator-based architectures, often enhanced with XOR structures to resist machine learning modeling attacks

My goal is to implement a RO-based strong PUF, based on this work work and this Tiny Tapeout project. This is not my work, this is from Pablo Aravena, I’m leveraging it as a learning tool for my own education. My contribution is to document, to test and to run it through the tools.

At high level, the device provides a 8 bits challenge and gets back a 8 bits response.

At lower level, a ring oscillator (RO) PUF is a delay-based PUF which uses frequency variations in inverter chains to generate unique IDs. ROs are made up of an odd numbers of inverters connected in a chain which oscillates at a specific frequency. Process variation introduced during IC manufacturing causes the frequencies in each RO to be slightly different. An RO PUF consists of identically-laid out ring oscillators fed into a two MUXs. The PUF challenge feeds into the MUX select lines and chooses which two ROs to compare. The MUX outputs are fed into a counter, each of which counts up to a preset value. If the top or the bottom counter reaches the preset value, the race arbiter will output a ‘1’ or a ‘0’ as the response depending which counter finishes first.

Here are the modules we need:

  • Ring oscillator (RO):
    • input: a signal to enable it. Then it oscillates on its own in a loop.
    • output: the output of the inverter chain, i.e a pulse with a tiny difference in frequency.
    • job to do: manage a n odd numbers of inverters connected in a chain which oscillates at a specific frequency.
  • MUX
    • input: half the challenge, i.e 16 possible values + 16 RO outputs
    • output: the output of one of the 16 ROs
    • job to do: manage a set of Ros (Hint: not a set of heroes :-). Route the selected RO pulse to the MUX output.
  • Counter:
    • input: items to count, coming from the MUX, in a pulse
    • output: a bit
    • job to do: flip the bit when the count > a given threshold
  • Arbiter
    • input: the signals coming from the two counters
    • output: a bit, the value depends on which counter won
    • job to to: decide which counter wins (i.e trigs first)
  • An orchestrator
    • input = the 8 bits challenge
    • output = the 8 bits response
    • job to to: manage the MUXes, ROs, Counters and Arbiter to get the job done. Basically, it manages a race between to ROs, the first one being choosen by the MSB of the challenge and the second one being selected by the LSB.
  • Scrambler is optionnal and is used to increase internal entropy in the system.
  • Buffer:
    • input: abriter’s decision
    • output: 8 sequential bits, i.e “The response”
    • job to to: wait, pack and deliver

In summary, with a 8 bits challenge, there are 256 differents possible races. Each one is a race between a RO in the first set and another RO in the other set. Since the ROs oscillates a different frequencies, repeating the same race 8 times in sequence does not guarantee that each race result will be identical. Hopefully, otherwise the Response would be always 00000000 or 11111111

What I’m not sure about is whether the Challenge-Response pairs set is 100% stable for a given PUF. What if the temperature varies, what is the power is not stable.. ???

According to my IA friend,…

To ensure CRPs remain consistent despite temperature changes, several techniques are used: * Error Correcting Codes (ECC) and Helper Data: These are standard methods to correct unstable bits, ensuring the PUF output is reliable. * Temperature-Aware Design: Specialized designs like the “Temperature-aware RO-PUF” pair ring oscillators that cooperate, allowing them to produce stable bits across different environmental conditions. * Masking/Filtering: Techniques such as 1-out-of-k masking (selecting the fastest/slowest resonators) or filtering out “unstable” bits (those that change frequently) can improve stability, though they may require high hardware overhead. * Calibration: Utilizing phase calibration processes can reduce bit errors to less than 1% in RO-PUFs.

Explore a standard cell: Open the sky130 standard cell library in KLayout and find an inverter (sky130_fd_sc_hd__inv_1). Identify metal, poly, and diffusion layers.

```
klayout /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
```

The list of cells is displayed on the top-left panel. Here is the sky130_fd_sc_hd__inv_1

The list of layers is displayed on the top-right side. We can hide empty layers from the list using contextual menu. Layers are desribed in the PDK reference

According to the documentation and to the layer list for this cell:

  • Metal is Meta5 and layers 64, 67, 68 and 122
  • Polysilicon layer is layer 66
  • Diffusion layer (the active area for transistors) is layer 65

Here are the details:

  • 64/5 = nwell label
  • 64/16 = pins
  • 64/20 = drawing
  • 64/59 = label
  • 65/20 = diff - Active (diffusion) area (type opposite of well/substrate underneath)
  • 66/20 = Polysilicon - drawing, text
  • 66/44 - drawing - Contact to local interconnect
  • 67/5 - li1 - label
  • 67/16 - li1 - pin
  • 68/5 - met1 - label
  • 68/16 - met1 - pin
  • 68/20 - met 1 - drawing and text
  • 78/44 - High-Vt LVPMOS implant - drawing
  • 81/4 - Cells in the standard cell library (over standard cell IP blocks only) .
  • 83/44 - text - label
  • 93/44 - N+ source/drain implant - drawing
  • 94/20 - P+ source/drain implant - drawing
  • 95/20 - Nitride poly cut (under licon1 areas) - drawing
  • 122/16 - pwell - pin
  • 236/0- ???

Connect the dots: Pick one block from your diagram — what standard cells might implement it? (e.g., “counter” needs flip-flops, “tone selector” needs muxes)

See above, at the end of the block diagram section