Final project - MUX module

Code

`timescale 1ns/1ps

module mux (
    input  wire[15:0]  ro_inputs,        // The output of each of the 16 ROs
    input  wire[3:0]   challenge, // Half of the provided challenge
    output wire        out        // The output of the selected RO for that challenge
);

   assign out = ro_inputs[challenge];

endmodule

Lint

verilator --lint-only -Wall -Ilib puf/mux.v
- V e r i l a t i o n   R e p o r t: Verilator 5.044 2026-01-01 rev v5.044
- Verilator: Built from 0.031 MB sources in 2 modules, into 0.009 MB in 3 C++ files needing 0.000 MB
- Verilator: Walltime 0.004 s (elab=0.000, cvt=0.001, bld=0.000); cpu 0.004 s on 1 threads; alloced 30.348 MB

Test harness

`timescale 1ns/1ps

module test_mux;
    // Inputs are reg (we drive them)
    reg[15:0]  ro_inputs;        // The output of each of the 16 ROs
    reg[3:0]   challenge;        // Half of the provided challenge     
    // Outputs are wire (DUT drives them)
    wire out;

    // Instantiate Device Under Test
    mux myMux(
        .ro_inputs(ro_inputs),      
        .challenge(challenge),
        .out(out)
    );


    // Test stimulus
    initial begin
        $dumpfile("waves.vcd");
        $dumpvars(0, test_mux);

        // Initialize
        $display("==> Initialize");
        #10            
        display;

        // Test case 1
        $display("==> RO 3 answer should be 1");          
        ro_inputs = 15'b000000000001000;
        challenge = 3'b011;
        display;

        // Test case 2
        $display("==> RO 5 answer is should be 0");        
        ro_inputs = 15'b111111111011111;
        challenge = 3'b101;
        display;

        #100 
        $finish;
    end
    task display;
    #1 $display("challenge:%0h, out:%0h",
                 challenge, out);
  endtask

endmodule

Test run in simulation

==> Initialize
challenge:x, out:x
==> RO 3 answer should be 1
challenge:3, out:1
==> RO 5 answer is should be 0
challenge:5, out:0
puf/test_mux.v:41: $finish called at 113000 (1ps)

Waves