Final project - Top level module

Code

/*
 *
 * Based on Pablo Aravena's work
 * Updated by Philippe Libioulle for Fab Futures 
 *
 */

module puf_top (
    input  wire [7:0] ui_in,    // Dedicated inputs - challenge
    output wire [7:0] uo_out,   // Dedicated outputs - response
    // verilator lint_off UNUSEDSIGNAL
    input  wire [7:0] uio_in,   // IOs: Input path - not used 
    output wire [7:0] uio_out,  // IOs: Output path - not used
    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output) - not used 
    // verilator lint_on UNUSEDSIGNAL
    input  wire       ena,      // always 1 when the design is powered, so you can ignore it
    input  wire       clk,      // clock
    input  wire       rst_n     // reset_n - low to reset
);

  // All output pins must be assigned. If not used, assign to 0.
  assign uio_out = 8'b00000000;
  assign uio_oe  = 8'b00000000;

  // List all unused inputs to prevent warnings
  wire _unused = &{1'b0};

  localparam n_bits = 8;

  // verilator lint_off UNUSEDSIGNAL
  wire[n_bits-1:0] finish;
  // verilator lint_on UNUSEDSIGNAL

  genvar i;

  generate
    for (i = 0; i < n_bits; i = i+1) begin
      puf_bit myBuffer(.challenge(ui_in[n_bits-1:0]), .clk(clk), .rst_n(rst_n), .enable(ena), .response(uo_out[i]), .done(finish[i]));
    end
  endgenerate

endmodule

Lint

/foss/designs/philippelibioulle/designs > make lint-top
verilator --lint-only -Wall -Ilib puf/puf_bit.v puf/ro.v puf/mux.v puf/counter.v puf/arbiter.v puf/puf_top.v  config.vlt
- V e r i l a t i o n   R e p o r t: Verilator 5.044 2026-01-01 rev v5.044
- Verilator: Built from 0.131 MB sources in 7 modules, into 23.107 MB in 26 C++ files needing 0.000 MB
- Verilator: Walltime 1.591 s (elab=0.003, cvt=1.261, bld=0.000); cpu 1.591 s on 1 threads; alloced 233.344 MB