Session 1: Introduction & Development Pipeline¶

What this session is about¶

Setting up the IIC-OSIC-TOOLS Docker environment, connecting via noVNC, exploring the example projects, and writing a first Hello World Verilog module.

Step 1 — Starting the Container¶

The Fab Futures tools run inside a Docker container called IIC-OSIC-TOOLS. Everything needed for chip design — ngspice, iverilog, KLayout, OpenROAD, Yosys — is pre-installed inside.

Container stopped, ready to start:

IIC-OSIC-TOOLS dashboard — container stopped

Container running — VNC connection details:

IIC-OSIC-TOOLS dashboard — container running, showing VNC address and password

Step 2 — Connecting via noVNC¶

Opening the Browser VNC link gives a full Linux desktop running inside the container. Right-clicking the background opens the application menu.

noVNC — JKU / Fab Futures desktop with right-click menu open

All work is saved to /foss/designs/ so it persists between container restarts.

Step 3 — Running the Example Simulations¶

The /foss/examples/ directory contains four example Verilog projects with a Makefile that automates compilation and simulation.

Directory listing and Makefile:

ls output showing example projects: fortune_teller, pocket_synth, dice_roller, morse_beacon

Makefile contents — sim-fortune, sim-synth, sim-dice, sim-led, sim-all, build targets

make sim-fortune — Fortune Teller:

The fortune teller simulates button presses and responds with random predictions over UART.

make sim-fortune — "Pressing button... Cannot predict." / "Yes definitely!" — Test complete

make sim-synth — Pocket Synth:

The pocket synth generates musical notes. The testbench verifies the correct frequencies: C=262 Hz, E=330 Hz, G=392 Hz, B=494 Hz.

make sim-synth — Playing C/E/G/B, measured frequencies match expected values

make sim-dice — Dice Roller:

The dice roller simulates 5 button presses, each producing a random number 1–6 via UART.

make sim-dice — Rolling dice 5 times: 1, 5, 3, 1, 5 — Test complete!

make sim-led — Morse Beacon:

The Morse beacon encodes “HELLO” as Morse code and drives an LED. The testbench verifies the LED on/off transitions.

make sim-led — Morse Beacon Testbench, Message: HELLO, Expected: .... . .-.. .-.. --- — Test complete, 2559 frames captured

make sim-all — All simulations at once:

make sim-all — all four simulations running in sequence

make sim-all — continued output

GTKWave — viewing the dice roller waveform:

After simulation, the .vcd file can be opened in GTKWave to inspect signals. Here the dice roller testbench signals are visible including rolling_led, rx_byte, seg[6:0], and state machine signals.

GTKWave — dice_roller_tb.vcd, signal list and waveform view

Step 4 — Hello World in Verilog¶

After exploring the examples, the first task is to write an original Verilog module.

Creating the working directory:

cd /foss/designs
mkdir hello_world
cd hello_world

Terminal — mkdir hello_world and cd hello_world

Writing hello.v in gvim:

module hello;
    initial
        $display("Hello Microcontroller !:)");
endmodule

gvim — hello.v with the Hello Microcontroller module

Compiling and running:

First attempt had a missing closing quote error. After fixing in gvim, it compiled and ran successfully:

iverilog -g2012 -o hello.vvp hello.v
vvp hello.vvp
Hello Microcontroller !

Terminal — iverilog compile error, fix in gvim, successful compile and vvp run

What I learned¶

The IIC-OSIC-TOOLS container gives you a complete chip design environment in a browser — no local installation needed. The four example projects cover a range of Verilog patterns: state machines (fortune teller), counters and frequency generation (pocket synth), UART serial output (dice roller), and timing-based LED control (Morse beacon).

Verilog syntax is strict about quotes and string literals — the $display function requires standard ASCII quotes, not curly ones. The -g2012 flag selects SystemVerilog 2012 compatibility mode which is needed for some features. iverilog compiles to a .vvp bytecode file which is then executed with vvp.