Session 2: Analog Basics¶

What this session is about¶

Electronics fundamentals — how transistors work, how to build logic gates from transistors, and how to simulate circuits using SPICE. The homework was to modify an AND gate netlist to create an OR gate, analyze a Schmitt trigger, and optionally explore circuits in TinkerCAD.

Assignment 1 — AND gate to OR gate (SPICE)¶

Starting from the AND gate netlist provided in the lecture, I ran it first to confirm it works, then modified it to create an OR gate.

First step: run ngspice

ngspice 45.2 startup

AND gate netlist in nano editor:

AND gate netlist — and_gate.sp

AND gate simulation result:

The output v(out) goes HIGH only when both inputs A and B are HIGH simultaneously (25–50 ns window). This confirms correct AND behavior.

AND gate waveform — v(a), v(b), v(out)

AND gate terminal output — initial conditions

Converting AND to OR:

The key change is swapping the PMOS and NMOS transistor arrangements:

Gate	PMOS	NMOS
NAND	Parallel	Series
NOR	Series	Parallel
AND	NAND + Inverter	—
OR	NOR + Inverter	—

For OR: PMOS transistors go in series (pull-up only when both inputs are LOW), NMOS transistors go in parallel (pull-down when either input is HIGH). Then add an inverter.

OR gate simulation result:

The output goes HIGH when either A or B is HIGH — correct OR behavior.

OR gate — terminal and waveform

OR gate — waveform detail

Assignment 2 — Schmitt Trigger Analysis¶

A Schmitt trigger has two switching thresholds instead of one. This gap between thresholds is called hysteresis — once the output switches, small noise won’t cause it to switch back.

In a CMOS Schmitt trigger there are 6 transistors: P1, P2, P3 (PMOS) and N1, N2, N3 (NMOS).

Upper threshold V_H is set by the NMOS side — N3 is a feedback transistor that raises the threshold for switching LOW→HIGH
Lower threshold V_L is set by the PMOS side — P3 is a feedback transistor that lowers the threshold for switching HIGH→LOW

The feedback transistors make the trigger “remember” its last state slightly, which is what creates the hysteresis window.

Assignment 3 — Falstad Circuit Simulator (Optional)¶

I explored the CMOS NAND gate in the Falstad browser-based circuit simulator at falstad.com/circuit. This is a good tool for visualizing how current flows through the transistors in real time.

Finding the CMOS NAND gate:
Circuits → Logic Families → CMOS → CMOS NAND

Falstad — Circuits menu, CMOS NAND selected

CMOS NAND running with both inputs HIGH:

The output is LOW (L) when both inputs are HIGH (H) — correct NAND behavior. The green lines show where current is flowing.

Falstad — CMOS NAND simulation, both inputs HIGH, output LOW

What I learned¶

An AND gate is actually a NAND gate followed by an inverter. This seems inefficient but it is how CMOS works — NAND and NOR are the “natural” gates because they map directly to the complementary transistor structure. AND and OR require an extra inversion step.

The water pipe analogy from the lecture is surprisingly accurate. PMOS transistors in parallel behave like pipes in parallel — if either path is open, current flows. PMOS in series requires both paths to be open. Swapping series and parallel is literally the difference between AND and OR logic.

SPICE simulation gives you exact numbers — voltage levels, timing, current. This is much more precise than a breadboard and faster than building actual silicon.