Session 4: Layout & Fabrication¶

Assignment 1 — Block Diagram: RGB Mixer¶

For my chip project I chose to build an RGB Mixer — a chip that uses 3 rotary encoders to independently control the brightness of Red, Green, and Blue LEDs through PWM signals. Inspired by the silicon-proven RGB Mixer on Tiny Tapeout (tt05, Matt Venn).

The architecture has 3 identical parallel channels, one for each color:

Encoder → Debounce → Counter → PWM Generator → LED

Encoder — a rotary encoder generates two signals (A and B). Direction and speed of rotation determines how the value changes.
Debounce — mechanical encoders produce noisy signals. This block filters the noise and produces clean transitions.
Counter — keeps track of encoder position as an 8-bit value (0–255). Turning up increments, turning down decrements.
PWM Generator — converts the 8-bit counter value into a PWM signal. Higher value = longer duty cycle = brighter LED.
Clock (10 MHz) — synchronizes all three counter modules for consistent timing across channels.

The three channels operate independently — any combination of red, green, and blue can be mixed. Like mixing paint, but with electricity.

Block diagram — RGB Mixer architecture

Assignment 2 — Exploring sky130_fd_sc_hd__inv_1 in KLayout¶

I opened the Sky130 standard cell library in KLayout:

klayout /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds

Found sky130_fd_sc_hd__inv_1 in the Cells panel, right-clicked and selected “Show as new top”. After hiding empty layers, layer numbers became visible in GDS layer.datatype format (e.g. 68/20).

Layer	GDS	What I saw
Metal	68/20	Power rails (VDD top, GND bottom) and output connection
Poly	66/20	Transistor gate — thin vertical strip through the middle
N+ Diffusion	93/44	Source/drain of NMOS transistor in lower half
P+ Diffusion	94/20	Source/drain of PMOS transistor in upper half

Where poly crosses diffusion, a transistor is formed. Together these layers make a complete CMOS inverter — one PMOS pull-up and one NMOS pull-down sharing the same poly gate.

Assignment 3 — Comparing inv_1 and dfxtp_1¶

For the RGB Mixer PWM Generator, the most important standard cell is the D flip-flop (sky130_fd_sc_hd__dfxtp_1). I opened it in KLayout and compared the same four layers.

dfxtp_1 — all layers

Poly (66/20)

The inverter had a single gate line. The flip-flop has approximately 12 gate structures — forming the D-latch and feedback inverter chain inside.

dfxtp_1 — Poly layer 66/20

P+ Diffusion (94/20)

Instead of a simple rectangle, the flip-flop shows a large irregular shape with notches — each notch is where a poly gate crosses the diffusion to form a PMOS transistor.

dfxtp_1 — P+ Diffusion 94/20

Metal (68/20)

Same VDD and GND rails at top and bottom, but the flip-flop also has two internal horizontal metal wires connecting the D input through the latch to the Q output.

dfxtp_1 — Metal layer 68/20

N+ Diffusion (93/44)

One large rectangle in the lower half of the cell, covering all NMOS transistors together.

dfxtp_1 — N+ Diffusion 93/44

Conclusion

An inverter uses 2 transistors. A D flip-flop uses approximately 20 transistors. The PWM Generator in the RGB Mixer needs 8 flip-flops for the 8-bit counter — roughly 160 transistors just for one color channel. Three channels means around 480 transistors for the counters alone.

What I learned¶

Looking at a chip layout makes the abstraction concrete. A single standard cell is 1–2 µm wide. The flip-flop is about 10× more complex than the inverter, which explains why synthesizing a design with lots of state (flip-flops) uses more area than combinational logic.

The power rails (VDD and GND) run horizontally through every cell at the same height. This is how the standard cell row system works — cells snap together and the power rails connect automatically.