Session 6: Synthesis & Physical Design¶

Assignment 1 — Synthesize the design¶

I used Yosys to synthesize the RGB Mixer design. First I ran a generic synthesis to check the gate count and verify there were no unintended latches.

The generic synthesis produced 318 cells with 51 flip-flops and zero latches — confirming the RTL was clean. I then mapped the design to the Sky130 standard cell library using dfflibmap and abc, which reduced the cell count to 270 real Sky130 cells including 48 dfrtp_1 flip-flops.

Yosys generic synthesis — 318 cells, 0 latches

Yosys Sky130 mapping — 270 cells

Assignment 2 — Place and Route¶

I used OpenROAD to run place and route on the synthesized netlist. After several attempts fixing layer names and track definitions, I got the flow working by adding make_tracks before place_pins.

The floorplan was set to 200×200 µm with a 20 µm border. OpenROAD successfully placed all 270 instances with 11 I/O pins and completed global and detailed placement in 414 iterations.

OpenROAD floorplan — 270 instances, 11 I/O pins

OpenROAD — Place & Route complete

Assignment 3 — Analyze timing reports¶

I ran report_checks inside OpenROAD after place and route completed. The critical path goes through the PWM counter in the blue channel, passing through a flip-flop, a maj3 gate, an a31oi gate, an o31a gate, an xnor2 gate, and a mux2 gate.

The data arrival time was 1.58 ns against a clock period of 100 ns, giving a slack of 98.29 ns — MET ✓. No timing violations.

report_design_area showed 2658 µm² at 11% utilization. report_power showed a total power consumption of 54.3 µW — suitable for a battery-powered LED controller.

OpenROAD timing report — slack 98.29 ns MET

OpenROAD design area and power report

Assignment 4 — Generate GDS¶

GDS generation with strm2gds failed in this Docker environment due to a conflict between the input and output layout files. The DEF file was successfully generated at rgb_top.def and contains the complete physical layout. For a real tapeout, this DEF would be converted to GDS using the OpenLane flow or Tiny Tapeout’s GitHub Actions workflow.

Problems I ran into¶

Error 1: ERROR IFP-0035: use -site to add placement rows Fix: added -site unithd to the initialize_floorplan command.

Error 2: ERROR IFP-0018: Unable to find site: unithd The site name was correct but the tech LEF was missing. Fix: added sky130_fd_sc_hd__nom.tlef as the first read_lef command.

Error 3: ERROR PPL-0021: Horizontal routing tracks not found for layer met2 This one took the longest. The fix came from reading Þórarinn’s documentation — make_tracks must be called before place_pins. Adding that single line solved it completely.

Error 4: GDS export strm2gds returned ERROR: Cannot copy shapes within the same layout regardless of output filename. KLayout also had conflicts with the default IHP PDK in this Docker environment. Both Yosuke and Þórarinn had the same issue — GDS export requires a more complete OpenLane flow.

What I learned¶

Going from Verilog to a physical chip layout is a two-step process. Yosys converts the code into logic gates. OpenROAD decides where each gate goes and how to connect them with wires.

270 standard cells sounds abstract — it represents roughly 2000–3000 real transistors in a 2658 µm² area.

The timing result surprised me. The design only needs 1.58 ns to process data, but the clock period is 100 ns. The chip could run much faster — but for controlling LED brightness, slow and simple is fine.

The biggest practical lesson: read other students’ documentation carefully. The make_tracks fix came directly from Þórarinn’s notes and saved hours of debugging.