Session 2: Analog Basics¶

Summary¶

Electrons flow through conductors like water through pipes Passive components (R, L, C) modify current flow without amplification Transistors (NMOS, PMOS) are voltage-controlled switches CMOS logic uses complementary transistor pairs to build gates SPICE simulates circuits from text netlists Clock distribution (H-tree) ensures synchronized operation Schmitt triggers clean up noisy signals with hysteresis

Homework¶

Modify the AND gate netlist to create an OR gate instead Hint: Swap the series/parallel arrangement of transistors

Schmitt trigger analysis: Look up a CMOS Schmitt trigger schematic and identify which transistors set the upper vs lower threshold

Optional: Build a simple circuit (LED + resistor + button) in TinkerCAD and observe current flow

Assignment 1¶

Building Logic Gates with Transistors

This is a netlist of AND gate which provided from our teacher.

* AND gate ngspice example

* NGSPICE transistor models
.model mosn NMOS level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16
.model mosp PMOS level=49 version=3.3.0 tox=10n nch=1e17 nsub=5e16

* 1 V power supply
vsup VDD 0 1


* AND pull-up network -- two pmos in parallel
Mp1 nOUT A VDD VDD mosp L=0.35u W=2u
Mp2 nOUT B VDD VDD mosp L=0.35u W=2u


* Pull-down network -- two nmos in series
Mn1 nOUT A npd 0 mosn L=0.35u W=2u
Mn2 npd B 0 0 mosn L=0.35u W=2u

* Inverter, or a logical NOT
Mp3 AND nOUT VDD VDD mosp L=0.35u W=2u
Mn3 AND nOUT 0 0 mosn L=0.35u W=2u

* Input voltage source, ramps up to VDD then back down
vin1 A 0 PWL(0 0 2mS 0 2.001mS 1V 3mS 1V 3.001mS 0)
vin2 B 0 PWL(0 0 1mS 0 1.001mS 1V 2.5mS 1V 2.5001mS 0)

.control
* transient simulation using vin sweep
  tran 100n 4m

* plot vout against vin 
  plot v(A)
  plot v(B)
  plot v(AND)
.endc

I refer the exsample of “AND” netlist. It is provided by course material.

Then I made “OR” netlist. First I tried to make netlist in pink area. This area has 2 PMOS as series. Purple part has 2 NMOS as parallel.

Assignment 2¶

Schmitt trigger analysis: Look up a CMOS Schmitt trigger schematic and identify which transistors set the upper vs lower threshold

I put command as “ngspice schmitt.sp” then it start analysing.

Shmitt trigger is a device that have 2 different threshold voltage for rising up voltage and falling down voltage.

This chart is showing the behavior of schmitt trigger. Red line describing input voltage. Blue line describing out put voltage. I could see that it has different threshold voltage.

This chart is showing the diffrence between falling input and rifing input. When we put falling input, it has threshold voltage as 0.34v. In the other hand, it has 0.62v threashold voltage. So it has 0.28v difference between rising input and falling input.