Session 6 - Synthesis & Physical Design¶
Summary¶
Synthesis converts RTL to gates Place & Route creates physical layout Timing analysis ensures your design meets speed requirements GDS is the final output for manufacturing
What You’ll Submit¶
For tapeout, you typically need:
A GDS file (generated by the flow) Documentation (README, pinout diagram) The Tiny Tapeout GitHub template handles most of this automatically - see tinytapeout.com for the submission guide.
Homework¶
- Synthesize your design
- review gate count and check for unintended latches
- Run place and route flow Analyze timing reports
- identify and fix any violations Generate GDS and review layout in KLayout
Course memo¶
Assignment 01¶
Synthesize your design¶
There are 3 ways to run Yosys command.
# Interactive
yosys
# Then, type commands.
# Script
yosys -s synth.tcl
# write script in .tcl file and run in one time
# One-liner
yosys -p "read_verilog design.v; synth -top top; write_verilog out.v"
yosys
read_verilog debounce.v
read_verilog note_c_generator.v
read_verilog top.v
hierarchy -check -top top
synth -top top
//I got responce The responce seems ok.
show top
# Map to Sky130 cells
dfflibmap -liberty /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
ログを見ると、無事に Verilog 上の抽象的なフリップフロップ（$DFF_PN0 など）が、Sky130 プロセスの具体的な部品（sky130_fd_sc_hd__dfrtp_1）にマッピングされました。
debounce: 17個の DFF がマッピング成功
note_c_generator: 1個の DFF がマッピング成功
次にすべきこと：論理ゲートのマッピング（abc） 現在の状態では「フリップフロップ」だけが Sky130 用に置き換わっており、「AND」や「OR」などの論理ゲートはまだ抽象的なままです。これらを Sky130 の部品に変換するために、次は abc コマンドを実行
abc -liberty /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
yosys> clean
Removed 0 unused cells and 106 unused wires.
write_verilog -noattr synth.v
Assignment 02¶
review gate count and check for unintended latches¶
stat
I got the response by stat command. Then I got response that using 104 cells totaly.
=== design hierarchy ===
+----------Count including submodules.
|
104 top
102 debounce
2 note_c_generator
+----------Count including submodules.
|
89 wires
115 wire bits
16 public wires
29 public wire bits
12 ports
12 port bits
- memories
- memory bits
- processes
104 cells
I could synthesis with Yosys.
Assignment 03¶
Run place and route flow¶
Analyze timing reports¶
Following this standard for this course, I will check the size of my project.
Our course projects (Fortune Teller, Pocket Synth, etc.) are designed to fit in 1 tile with room to spare.
What is tile?¶
Tile is rectangle area that have 160µm × 100µm.
Why we need room to spare?¶
Becuase no spare will cause of routing Congestion.
Let’s run place and route flow.¶
I added following command to run_openoard.tcl
read_lef $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tech.lef
I fixed some command in stl. Then I could complete command.
run_openroad.tcl¶
# run_openroad.tcl - Place & Route script
read_liberty /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_lef /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
read_lef /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
read_verilog synth.v
link_design top
read_sdc constraints.sdc
initialize_floorplan \
-utilization 50 \
-aspect_ratio 1 \
-core_space 2 \
-site unithd
make_tracks li1 -x_offset 0.23 -x_pitch 0.46 -y_offset 0.17 -y_pitch 0.34
make_tracks met1 -x_offset 0.17 -x_pitch 0.34 -y_offset 0.17 -y_pitch 0.34
make_tracks met2 -x_offset 0.23 -x_pitch 0.46 -y_offset 0.23 -y_pitch 0.46
make_tracks met3 -x_offset 0.34 -x_pitch 0.68 -y_offset 0.34 -y_pitch 0.68
make_tracks met4 -x_offset 0.46 -x_pitch 0.92 -y_offset 0.46 -y_pitch 0.92
make_tracks met5 -x_offset 1.70 -x_pitch 3.40 -y_offset 1.70 -y_pitch 3.40
place_pins -hor_layers met3 -ver_layers met2
pdngen
global_placement
detailed_placement
check_placement -verbose
clock_tree_synthesis
detailed_placement
# ? ?????????????
set_routing_layers -signal li1-met5 -clock met3-met5
global_route \
-congestion_iterations 30
detailed_route \
-verbose 1
write_def c_note_generator_output.def
write_verilog c_note_generator_output.v
# run timing analysis and show the result
estimate_parasitics -placement
report_checks -path_delay max -format full_clock_expanded
report_worst_slack -max
constraints.sdc¶
# Define a 50 MHz clock (20 ns period) on the 'clk' input
create_clock -name clk -period 20 [get_ports clk]
# Input signals arrive 5 ns after clock edge
set_input_delay -clock clk 5 [all_inputs]
# Output signals must be valid 5 ns before next clock edge
set_output_delay -clock clk 5 [all_outputs]
# Reset is asynchronous - don't check timing on it
set_false_path -from [get_ports rst_n]
# Account for clock jitter/skew
set_clock_uncertainty 0.5 [get_clocks clk]
# determine the area size for 1 tile 160µm x 100µm
initialize_floorplan -site unithd -die_area "0 0 160 100" -core_area "10 10 150 90"
From this report I could know the result of simulation.
- 13.81 slack (MET)
- “SLACK” refers to the “margin of time” in my timing budget.
- “MET” means the timing constraints have been “satisfied.” As long as this does not say VIOLATED, it guarantees that the physical chip will operate exactly as calculated under the specified conditions.
- “13.81 (ns)” indicates that it have a margin of 13.81ns relative to your clock period of 20ns (50MHz). This is a very robust and safe design.
| Item | Value (ns) | Description |
|---|---|---|
| Data Arrival Time | 0.69 | The time it takes for data to reach the destination (spk_out) after the clock edge rises. |
| Data Required Time | 14.5 | The “deadline” by which the data must arrive to be successfully captured by the next clock cycle. |
| Slack | 13.81 | Calculated as 14.50 - 0.69 = 13.81. This indicates a very high design margin. |
Power consumption¶
I added following lines in run_openroad.tlc.
# 消費電力の解析
estimate_parasitics -placement
report_power
I got this report.
| Power Group | Power (Watts) | Share (%) | Description |
|---|---|---|---|
| Sequential | 3.76E-05 | 72.20% | Power consumed by flip-flops (registers). This is the dominant factor. |
| Clock | 1.34E-05 | 25.80% | Power used to toggle the clock tree (buffers, etc.). |
| Combinational | 1.05E-06 | 2.00% | Power used by logic gates like AND/OR. Surprisingly low. |
| Leakage | 3.41E-10 | 0.00% | Static power loss when the circuit is idle. Negligible in this case. |
| Total | 5.20E-05 | 100% | Total: Approx. 52 μW |
As a result this circuit will consume about 0.052 mW.
Comparison to a Single LED: A standard LED used in typical electronics projects (consuming 20mA) requires approximately 60mW of power to stay lit. In contrast, your entire circuit is running on less than 1/1000th of the power required for just one LED.
Assignment 04¶
identify and fix any violations¶
Generate GDS and review layout in KLayout¶
export_gds_magic.script¶
cat << 'EOF' > expoert_gds_magic.script
drc off
gds read /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
lef read /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
lef read /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
def read c_note_generator_output.def
gds merge true
gds write c_note_generator_output.gds
quit
EOF
Then Run this script¶
magic -noconsole -dnull -rcfile /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.tech/magic/sky130A.magicrc < expoert_gds_magic.script
I could get gds file.
I opend this gds file with klayout.
klayout c_note_generator_output.gds
Wow!! I could design the chip layout!! Still I don’t understand these steps yet. But this is amazing experience. Thank you for our faculty.