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Session 7 - Packaging & Board Design

Course material

class video

Summary

  • Packaging protects the die and provides connectivity
  • Wirebonding connects die pads to package pins
  • Eval boards provide power, clock, and I/O access
  • FPGAs let you prototype before silicon arrives
  • Testing verifies your chip works in silicon
  • Debug requires planning and systematic approach

Homework

  • Run final DRC/LVS on your design
  • Document your chip: functionality, pin assignments, and interface details (e.g., timing parameters, frequencies, baud rates)
  • Develop a verification test plan
  • Prepare your presentation for Thursday!

—

Assignment 01

  • Run final DRC/LVS on your design

Run DRC

I ran DRC by following command

/foss/tools/klayout/klayout \
  -m drc_report.xml \
  c_note_generator_output.gds

I got resutl.

# check number of viorations
grep -c "item" drc_report.xml

# check the detail of viorations
grep -A2 "description" drc_report.xml

This is the report of DRC. image Result of this command is bellow.

/foss/examples/take_project > grep -c "item" drc_report.xml
2
/foss/examples/take_project > grep -A2 "description" drc_report.xml
 <description>SKY130 DRC runset</description>
 <original-file/>
 <generator>drc: script='/foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.tech/klayout/drc/sky130A_mr.drc'</generator>
/foss/examples/take_project >

It don’t have any vioration for DRC!

Run LVS

extract spice netlist

cat << 'EOF' > extract_spice.script
drc off
gds read /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
lef read /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
lef read /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
def read c_note_generator_output.def
extract all
ext2spice hierarchy on
ext2spice format ngspice
ext2spice -o c_note_generator_layout.spice
quit
EOF

magic -noconsole -dnull -rcfile /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.tech/magic/sky130A.magicrc < extract_spice.script

Run LVS with Netgen

netgen -batch lvs \
  "c_note_generator_layout.spice top" \
  "c_note_generator_output.v top" \
  /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A/libs.tech/netgen/sky130A_setup.tcl \
  lvs_report.txt

Then I got the result of LVS.

It is saying.

Circuit 1 contains 78 devices, Circuit 2 contains 69 devices. *** MISMATCH ***
Circuit 1 contains 115 nets,    Circuit 2 contains 348 nets. *** MISMATCH ***

It don`t match the number.

I asked to Cloude about this result. It said it because of extra capacitor was created by Magic when it extracted capacitance.

Second issue is that number of nets don’t match. I looked into what caused the issue, but I couldn’t quite figure out why there was a difference in the number of wires.

Assignment 02

  • Document your chip: functionality, pin assignments, and interface details (e.g., timing parameters, frequencies, baud rates)

    • Voltage Standardss : 1.8V

    • pin assignments

    • interface detail

      • CLK frequency : 10MHz

    • Package type : QFN