Session 2: Analog Basics¶

Homework¶

Homework

Modify the AND gate netlist to create an OR gate instead
Hint: Swap the series/parallel arrangement of transistors
Schmitt trigger analysis: Look up a CMOS Schmitt trigger schematic and identify which transistors set the upper vs lower threshold
Optional: Build a simple circuit (LED + resistor + button) in TinkerCAD and observe current flow

Words¶

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Netlistjp

A netlist is a text description of your circuit — what components you have and how they’re connected. Each line describes one component. It is used as input data to describe the configuration of a circuit in circuit simulation software such as SPICE (e.g., NgSPICE or LTspice).

The designer writes the circuit they want to create as a “code” (script) called a netlist, and by loading it into the simulator, they can calculate the behavior of voltages and currents.

Basic Device Syntax

Component	Syntax	Example
Resistor	Rx n1 n2 R=value	R1 in out R=1k
Capacitor	Cx n1 n2 C=value	C1 out gnd C=1p
Inductor	Lx n1 n2 L=value	L1 in out L=1n
MOSFET	Mx drain gate source bulk model L=len W=wid	M1 out in vdd vdd pmos L=1u W=2u

n1, n2 are node names (connection points)
k = kilo (1000), p = pico (10⁻¹²), n = nano (10⁻⁹), u = micro (10⁻⁶)

Netlistとは「電子回路をテキスト形式で記述した設計図」のこと。回路シミュレーションソフトウェアであるSPICE（NgSPICEやLTspiceなど）において、回路の構成を伝えるための入力データとして使用される。設計者は、自分が作りたい回路をネットリストという「コード（スクリプト）」として記述し、シミュレータに読み込ませることで、電圧や電流の挙動を計算させる

CMOS Schmitt trigger schematicjp

CMOS Schmitt trigger schematic is a special circuit configuration designed to clean up noisy input signals and prevent false switching.

Problem It Solves: Input Noise
Real-world signals (such as push buttons or sensor outputs) are not perfect and often contain noise, meaning the voltage fluctuates unpredictably. A normal logic gate may misinterpret this noise as multiple transitions. A Schmitt trigger eliminates this problem.
Circuit Feature: Hysteresis
The key feature of a Schmitt trigger is hysteresis, meaning it has two different threshold voltages.
- Upper threshold (\(V_H\)): The higher voltage that must be exceeded for the output to switch ON when the input changes from LOW to HIGH.
- Lower threshold (\(V_L\)): The lower voltage that must be crossed for the output to switch OFF when the input changes from HIGH to LOW.
Because there is a gap between these two thresholds, small noise within this range does not cause repeated switching.
Transistor-Level Circuit Configuration (Schematic) In the CMOS Schmitt trigger schematic shown in the reference (an example consisting of six transistors, M1–M6), the structure is as follows:
- Main Stack (M1, M2, M4, M5): A central series connection of NMOS transistors (M1, M2) and PMOS transistors (M4, M5).
- Feedback Transistors (M3, M6): These are the key elements that create hysteresis.
- M3 (NMOS): Receives feedback from the output node and controls the timing of the pull-down (ground-side) path. It primarily determines the upper threshold (\(V_H\)).
- M6 (PMOS): Receives feedback from the output node and controls the timing of the pull-up (power-side) path. It primarily determines the lower threshold (\(V_L\)).
Symbol and Applications Circuit Symbol: A triangle (buffer or inverter symbol) with a small squiggly mark inside representing the hysteresis characteristic. Main Applications: Button debouncing (chatter suppression), sensor interfaces, and cleanup of noisy signals.

CMOS Schmitt trigger（シュミットトリガ）の回路図（schematic）は、ノイズの多い入力信号をきれいに整え、誤作動を防ぐための特殊な回路構成。

解決する問題：入力ノイズ
現実世界の信号（ボタンの押し下げやセンサーの出力など）は完璧ではなく、電圧が不安定に上下する「ノイズ」を含んでいます。通常の論理ゲートでは、このノイズを「複数の切り替え」として誤認してしまうことがありますが、シュミットトリガはこれを取り除きます。　　
回路の特徴：ヒステリシス
シュミットトリガの最大の特徴は、「ヒステリシス」と呼ばれる2つの異なるしきい値（閾値）を持つことです
- 上側しきい値 (\(V_H\)): 入力がLOWからHIGHへ変わる際に、ONになるために超えなければならない高い電圧
- 下側しきい値 (\(V_L\)): 入力がHIGHからLOWへ変わる際に、OFFになるために下回らなければならない低い電圧
  この2つの値の間に「隙間」があることで、小さなノイズが入力されても出力が頻繁に切り替わるのを防ぎます。
トランジスタレベルの回路構成 (Schematic) 資料に示されているCMOSシュミットトリガの回路図（M1〜M6の6つのトランジスタで構成される例）では、以下のような構造になっています
- メインのスタック (M1, M2, M4, M5): 中央に直列に並んだNMOS（M1, M2）とPMOS（M4, M5）のペアです
- フィードバック・トランジスタ (M3, M6): これらがヒステリシスを生み出す鍵となります
- M3 (NMOS): 出力ノードからフィードバックを受け、プルダウン（接地側）のタイミングを制御します。これが主に上側しきい値 (\(V_H\))の設定に関与します
- M6 (PMOS): 出力ノードからフィードバックを受け、プルアップ（電源側）のタイミングを制御します。これが主に下側しきい値 (\(V_L\))の設定に関与します
シンボルと用途回路記号: バッファやインバータの三角形の中に、ヒステリシス曲線を表す小さな「～」のような記号（スクイグル）が描かれます。主な用途: ボタンのデバウンシング（チャタリング防止）、センサーインターフェース、ノイズの多い信号のクリーンアップなどに使用されます。

Homework 1¶

Homework

Modify the AND gate netlist to create an OR gate instead
Hint: Swap the series/parallel arrangement of transistors

AND gate and OR gate¶

AND gate
Output is 1 only if BOTH inputs are 1.

A	B	A AND B
0	0	0
0	1	0
1	0	0
1	1	1

OR Gate
Output is 1 if EITHER or BOTH inputs are 1.

A	B	A OR B
0	0	0
0	1	1
1	0	1
1	1	1

NOT Gate (Inverter)
Output is the opposite of input.

A	NOT A
0	1
1	0

AND gate¶

An AND gate is constructed from a NAND(NOT-AND) gate and an NOT(inverter) gate. alt text

NAND gate

NAND gate in Transistor level,

Pull-up: two PMOS transistors in parallel
Pull-down: two NMOS transistors in series

alt text

PMOS behaves Normally Open Switch

When Gate signal is 0, Drain is connected to VDD
When Gate signal is 1, Drain is disconnected

NMOS behaves Normally Closed Switch

When Gate signal is 0, Drain is connected to GND
When Gate signal is 1, Drain is disconnected

alt text

A(P1)	B(P2)	PMOS(Parallel) nOUT	A(N1)	B(N2)	NMOS(Series) nOUT	NAND output
0	0	VDD	0	0	OFF	VDD(1)
0	1	VDD	0	1	OFF	VDD(1)
1	0	VDD	1	0	OFF	VDD(1)
1	1	OFF	1	1	GND	GND(0)

NOT gate

NAND output	NOT output
VDD(1)	0
GND(0)	1

AND gate

A	B	output
0	0	0
0	1	0
1	0	0
1	1	1

AND gate netlist¶

Basic Device Syntax

Component	Syntax	Example
MOSFET	Mx drain gate source bulk model L=len W=wid	M1 out in vdd vdd pmos L=1u W=2u

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AND Gate using CMOS (Click to open)

* AND Gate using CMOS

* Power supply
Vdd vdd gnd 1.8
* Defines the voltage level for Logic HIGH (1). 1.8V is a common voltage standard used in modern processors [4].

* Input signals (PWL)
Va a gnd PWL(0n 0 10n 0 11n 1.8 50n 1.8 51n 0 100n 0)
Vb b gnd PWL(0n 0 25n 0 26n 1.8 75n 1.8 76n 0 100n 0)
* These lines define test signals A and B using PWL (Piecewise Linear) syntax.
* Signal A rises to 1.8V at 10ns, and Signal B rises at 25ns. 
* Based on the AND truth table, the output should only be HIGH when both A and B are HIGH (between 25ns and 50ns).


* NAND gate
* PMOS pull-up (parallel)
Mp1 nand_out a vdd vdd pmos L=1u W=2u
Mp2 nand_out b vdd vdd pmos L=1u W=2u
*
* Syntax of MOSFET
* Mx drain gate source bulk model L=len W=wid
* 
* PMOS acts like a "normally closed faucet"—it turns ON when the gate signal is LOW (0).
* If EITHER input A or B is 0, the output node (nand_out) is pulled up to VDD.

* NMOS pull-down (series)
Mn1 nand_out a mid gnd nmos L=1u W=1u
Mn2 mid b gnd gnd nmos L=1u W=1u
*
* Syntax of MOSFET
* Mx drain gate source bulk model L=len W=wid
* 
* NMOS acts like a "normally open faucet"—it turns ON when the gate signal is HIGH (1).
* The path to ground (GND) is only completed if BOTH A and B are HIGH.


* Inverter (to make AND from NAND)
Mp3 out nand_out vdd vdd pmos L=1u W=2u
Mn3 out nand_out gnd gnd nmos L=1u W=1u
* Since the first stage is a NAND (output is 0 when both are 1), an inverter is added to "flip" the logic to an AND function.


* Transistor models
.model nmos nmos (vth0=0.4)
.model pmos pmos (vth0=-0.4)
* These lines define how the transistors behave. "vth0" refers to the threshold voltage where the transistor switches between ON and OFF.

* Simulation control
* The .control block contains the commands for the SPICE simulator [5, 13].
.control

* "tran" performs a transient analysis, calculating voltages and currents over a 100ns time period [5, 13].
tran 0.1n 100n

* "plot" generates a waveform to verify the logic functionality [5, 7].
plot v(a) v(b) v(out)
.endc

.end

bulk in MOSFET Syntax of SPICE Netlist

bulkjp

It refers to the fourth terminal (connection point) of a MOSFET, also known as the Substrate or Internal reference.
1. Role of the Bulk (Substrate)
While transistors are typically known as three-terminal devices (drain, gate, and source), designing for integrated circuits in a netlist requires specifying a connection to the silicon substrate upon which the device is formed. This is called the bulk or substrate.
2. Connection Rules
To ensure the circuit functions correctly, the general rules for connection are as follows:
For NMOS: The bulk is connected to Ground (GND / 0).
For PMOS: The bulk is connected to the Power Supply (VDD / 1).

MOSFETの4番目の端子（接続ポイント）のことで、Substrate（基板）やInternal reference（内部リファレンス）とも呼ばれます。
1. bulk（Substrate）の役割
トランジスタは通常、ドレイン・ゲート・ソースの3端子デバイスとして知られていますが、集積回路上の設計（ネットリスト）では、デバイスが形成されているシリコン基板そのものへの接続を指定する必要があります。これをbulkまたはsubstrateと呼びます。
2. 接続のルール
回路を正しく動作させるための一般的なルールとして、以下のように接続されます。
NMOSの場合: bulkは接地（GND / 0）に接続
PMOSの場合: bulkは電源（VDD / 1）に接続

OR gate¶

AI-generated summary

This section includes to be summarized using NotebookLM (Source: lecture page)

AND gate: NAND gate + Inverter
OR gate: NOR gate + Inverter

NOR gate

A	B	OR output	NOR Output
0	0	0	1
0	1	0	0
1	0	0	0
1	1	1	0

NOR gate + NOT gate

A	B	OR output	NOR Output	NOT gate
0	0	0	1	0
0	1	0	0	1
1	0	0	0	1
1	1	1	0	1

OR gate

A	B	OR gate
0	0	0
0	1	1
1	0	1
1	1	1

OR gate netlist¶

Difference of NAND and NOR gates in Transistor level,

	NAND gate	NOR gate
PMOS(Pull-up)	2 PMOS Parallel	2 PMOS Series
NMOS(pull-down)	2 NMOS Series	2 NMOS Parallel

NAND gate

    * NAND gate
    * PMOS pull-up (parallel)
    Mp1 nand_out a vdd vdd pmos L=1u W=2u
    Mp2 nand_out b vdd vdd pmos L=1u W=2u

    * NMOS pull-down (series)
    Mn1 nand_out a mid gnd nmos L=1u W=1u
    Mn2 mid b gnd gnd nmos L=1u W=1u
    *
    * Syntax of MOSFET
    * Mx drain gate source bulk model L=len W=wid

NOR gate

                     VDD
                      |
                      |
                   Source
                      |             PMOS Pull-up(Series)
                  ----|            (Mx  drain gate source bulk model L=len W=wid)
          A ---  Gate o| PMOS       Mp1 mid   a    vdd    vdd  pmos  L=1u  W=2u
                  ----|             
                      |             
                      |
                   Drain
                      |
                    (mid)
                      |
                   Source
                      |
                  ----|            (Mx  drain   gate source bulk model L=len W=wid)
          B ---  Gate o| PMOS       Mp2 nor_out b    mid    vdd  pmos  L=1u  W=2u
                  ----|
                      |
                      |
                   Drain
                      |
                      |
                      +---------------- NOR output
                      |
                      |
            +---------+-------+
            |                 |
         Drain             Drain        NMOS Pull-down(Parallel)
            |                 |        (Mx  drain   gate source bulk model L=len W=wid) 
        ----|             ----|         Mn1 nor_out a    gnd    gnd  nmos  L=1u  W=1u
  A --- Gate| NMOS   B--- Gate| NMOS    Mn2 nor_out b    gnd    gnd  nmos  L=1u  W=1u
        ----|             ----|         
            |                 |
        Source            Source
            |                 |
            +---------+-------+
                      |
                      |
                     GND

PMOS Pull-up(Series)
Mp1 mid a vdd vdd pmos L=1u W=2u
Mp2 nor_out b mid vdd pmos L=1u W=2u

NMOS Pull-down(Parallel)
Mn1 nor_out a gnd gnd nmos L=1u W=1u
Mn2 nor_out b gnd gnd nmos L=1u W=1u

Invertor

* Inverter (to make OR from NOR)
Mp3 out nor_out vdd vdd pmos L=1u W=2u
Mn3 out nor_out gnd gnd nmos L=1u W=1u

OR Gate using CMOS (Click to open)

* Power supply
Vdd vdd gnd 1.8

* Input signals (PWL)
Va a gnd PWL(0n 0 10n 0 11n 1.8 50n 1.8 51n 0 100n 0)
Vb b gnd PWL(0n 0 25n 0 26n 1.8 75n 1.8 76n 0 100n 0)

* =====================================
* NOR gate
* PMOS pull-up (series)
Mp1 mid a vdd vdd pmos L=1u W=2u
Mp2 nor_out b mid vdd pmos L=1u W=2u

* NMOS pull-down (parallel)
Mn1 nor_out a gnd gnd nmos L=1u W=1u
Mn2 nor_out b gnd gnd nmos L=1u W=1u

* Inverter (to make OR from NOR)
Mp3 out nor_out vdd vdd pmos L=1u W=2u
Mn3 out nor_out gnd gnd nmos L=1u W=1u
* =====================================

* Transistor models
.model nmos nmos (vth0=0.4)
.model pmos pmos (vth0=-0.4)

* Simulation control
.control
tran 0.1n 100n
plot v(a) v(b) v(out)
.endc

.end

Homework 2¶

Homework

2.　Schmitt trigger analysis: Look up a CMOS Schmitt trigger schematic and identify which transistors set the upper vs lower threshold


	Bouncing in real world
	de-bouncing
	Schmitte triger schematic

How Schmitt trigger schematic works?

alt text

Vg=0, Vo=Vdd, M3=ON(Vdd)
Vg=1, Vo=GND, M6=ON(GND)

Upper threshold(\(V_H\)): M3
Lower threshold(\(V_L\)): M6

AI-generated summary

This section includes to be summarized using NotebookLM (Source: lecture page)

Why and How?jp

Upper Threshold (\(V_H\)) and M3 Placement: In the circuit diagram (M1–M6), M3 (NMOS) is connected between the intermediate node and VDD (power supply).
Operation: When the input rises from LOW to HIGH, the output is still HIGH (1), so M3 remains ON. This M3 acts as a “resistive” path that holds the intermediate node toward VDD, meaning a higher input voltage is required for the circuit to switch. This forms the upper threshold (\(V_H\) / Upper Threshold).
Lower Threshold (\(V_L\)) and M6 Placement: M6 (PMOS) is connected between the intermediate node and GND (ground). Operation: When the input falls from HIGH to LOW, the output is still LOW (0), so M6 remains ON. This M6 “resists” by pulling the intermediate node toward GND, meaning the input voltage must drop further for the circuit to switch back. This forms the lower threshold (\(V_L\) / Lower Threshold).

上側しきい値 (\(V_H\))とM3
配置: 回路図（M1〜M6）において、M3 (NMOS) は中間ノードから VDD（電源）側に接続されています。
動作: 入力がLOWからHIGHへ上昇する際、出力はまだHIGH(1)であるため、M3がONの状態です。このM3が中間ノードをVDDに引き止める「抵抗」として働くため、回路が切り替わるのにより高い電圧が必要になります。これが上側しきい値 (\(V_H\)/ Upper Threshold) を形成します。
下側しきい値 (\(V_L\))とM6
配置: M6 (PMOS) は中間ノードから接地（GND）側に接続されています。
動作: 入力がHIGHからLOWへ低下する際、出力はまだLOW(0)であるため、M6がONの状態です。このM6が中間ノードをGNDに引き下げようと「抵抗」するため、回路が元に戻るのにより低い電圧まで下がる必要があります。これが下側しきい値 (\(V_L\)/ Lower Threshold) を形成します。

Homework

3.　Optional: Build a simple circuit (LED + resistor + button) in TinkerCAD and observe current flow

I will not do this optional homework.