4. Executing SYNTH pass. 4.1. Executing HIERARCHY pass (managing design hierarchy). 4.1.1. Analyzing design hierarchy.. Top module: \alu_top Used module: $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx Used module: \alu Used module: \ctr_down Used module: \ctr_up 4.1.2. Analyzing design hierarchy.. Top module: \alu_top Used module: $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx Used module: \alu Used module: \ctr_down Used module: \ctr_up Removed 0 unused modules. 4.2. Executing PROC pass (convert processes to netlists). 4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 6 switch rules as full_case in process $proc$lib/uart_tx.v:95$24 in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Marked 3 switch rules as full_case in process $proc$up_dw_alu_uart.v:69$7 in module alu. Marked 1 switch rules as full_case in process $proc$up_dw_alu_uart.v:53$4 in module ctr_down. Marked 1 switch rules as full_case in process $proc$up_dw_alu_uart.v:38$1 in module ctr_up. Removed a total of 0 dead cases. 4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 1 redundant assignment. Promoted 1 assignment to connection. 4.2.4. Executing PROC_INIT pass (extract init attributes). 4.2.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \rst_n in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. 4.2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. 1/6: $0\tx[0:0] 2/6: $0\shift_reg[7:0] 3/6: $0\bit_idx[2:0] 4/6: $0\clk_ctr[3:0] 5/6: $0\state[1:0] 6/6: $0\ready[0:0] Creating decoders for process `\alu.$proc$up_dw_alu_uart.v:69$7'. 1/3: $3\result[7:0] 2/3: $2\result[7:0] 3/3: $1\result[7:0] Creating decoders for process `\ctr_down.$proc$up_dw_alu_uart.v:53$4'. 1/1: $0\out_d[3:0] Creating decoders for process `\ctr_up.$proc$up_dw_alu_uart.v:38$1'. 1/1: $0\out_u[3:0] 4.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\alu.\result' from process `\alu.$proc$up_dw_alu_uart.v:69$7'. 4.2.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.\tx' using process `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. created $adff cell `$procdff$131' with positive edge clock and positive level reset. Creating register for signal `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.\ready' using process `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. created $adff cell `$procdff$136' with positive edge clock and positive level reset. Creating register for signal `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.\state' using process `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. created $adff cell `$procdff$141' with positive edge clock and positive level reset. Creating register for signal `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.\clk_ctr' using process `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. created $adff cell `$procdff$146' with positive edge clock and positive level reset. Creating register for signal `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.\bit_idx' using process `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. created $adff cell `$procdff$151' with positive edge clock and positive level reset. Creating register for signal `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.\shift_reg' using process `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. created $adff cell `$procdff$156' with positive edge clock and positive level reset. Creating register for signal `\ctr_down.\out_d' using process `\ctr_down.$proc$up_dw_alu_uart.v:53$4'. created $dff cell `$procdff$157' with positive edge clock. Creating register for signal `\ctr_up.\out_u' using process `\ctr_up.$proc$up_dw_alu_uart.v:38$1'. created $dff cell `$procdff$158' with positive edge clock. 4.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 6 empty switches in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. Removing empty process `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$proc$lib/uart_tx.v:95$24'. Found and cleaned up 3 empty switches in `\alu.$proc$up_dw_alu_uart.v:69$7'. Removing empty process `alu.$proc$up_dw_alu_uart.v:69$7'. Found and cleaned up 2 empty switches in `\ctr_down.$proc$up_dw_alu_uart.v:53$4'. Removing empty process `ctr_down.$proc$up_dw_alu_uart.v:53$4'. Found and cleaned up 2 empty switches in `\ctr_up.$proc$up_dw_alu_uart.v:38$1'. Removing empty process `ctr_up.$proc$up_dw_alu_uart.v:38$1'. Cleaned up 13 empty switches. 4.2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module ctr_down. Optimizing module ctr_up. Optimizing module alu_top. 4.3. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module ctr_down. Optimizing module ctr_up. Optimizing module alu_top. 4.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. Finding unused cells or wires in module \alu_top.. Removed 9 unused cells and 53 unused wires. 4.5. Executing CHECK pass (checking for obvious problems). Checking module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx... Checking module alu... Checking module alu_top... Checking module ctr_down... Checking module ctr_up... Found and reported 0 problems. 4.6. Executing OPT pass (performing simple optimizations). 4.6.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.6.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 49 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 35 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 12 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 4 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 4 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 14 cells. 4.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $procmux$103. dead port 1/2 on $mux $procmux$106. dead port 1/2 on $mux $procmux$112. Running muxtree optimizer on module \alu_top.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_down.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \ctr_up.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 3 multiplexer ports. 4.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. New ctrl vector for $pmux cell $procmux$32: { $procmux$35_CMP $procmux$34_CMP $auto$opt_reduce.cc:137:opt_pmux$160 } Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing cells in module \alu. Optimizing cells in module \alu_top. Optimizing cells in module \ctr_down. Optimizing cells in module \ctr_up. Performed a total of 1 changes. 4.6.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 36 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 35 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 4 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 4 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 1 cells. 4.6.6. Executing OPT_DFF pass (perform DFF optimizations). 4.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. Removed 0 unused cells and 18 unused wires. 4.6.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.6.9. Rerunning OPT passes. (Maybe there is more to do..) 4.6.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu_top.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_down.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \ctr_up.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. New ctrl vector for $pmux cell $procmux$60: { $procmux$36_CMP $auto$opt_reduce.cc:137:opt_pmux$162 $procmux$33_CMP } Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing cells in module \alu. Optimizing cells in module \alu_top. Optimizing cells in module \ctr_down. Optimizing cells in module \ctr_up. Performed a total of 1 changes. 4.6.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 36 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 4 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 4 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 0 cells. 4.6.13. Executing OPT_DFF pass (perform DFF optimizations). 4.6.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. 4.6.15. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.6.16. Rerunning OPT passes. (Maybe there is more to do..) 4.6.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu_top.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_down.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \ctr_up.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.6.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing cells in module \alu. Optimizing cells in module \alu_top. Optimizing cells in module \ctr_down. Optimizing cells in module \ctr_up. Performed a total of 0 changes. 4.6.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 36 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 4 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 4 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 0 cells. 4.6.20. Executing OPT_DFF pass (perform DFF optimizations). 4.6.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. 4.6.22. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.6.23. Finished fast OPT passes. (There is nothing left to do.) 4.7. Executing FSM pass (extract and optimize FSM). 4.7.1. Executing FSM_DETECT pass (finding FSMs in design). Found FSM state register $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.state. 4.7.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\state' from module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. found $adff cell for state register: $procdff$141 root of input selection tree: $0\state[1:0] found reset state: 2'00 (from async reset) found ctrl input: $procmux$33_CMP found ctrl input: $procmux$34_CMP found ctrl input: $procmux$35_CMP found ctrl input: $procmux$36_CMP found ctrl input: \tick found ctrl input: $eq$lib/uart_tx.v:162$28_Y found state code: 2'11 found state code: 2'10 found ctrl input: \valid found state code: 2'01 found ctrl output: $procmux$33_CMP found ctrl output: $procmux$34_CMP found ctrl output: $procmux$35_CMP found ctrl output: $procmux$36_CMP ctrl inputs: { $eq$lib/uart_tx.v:162$28_Y \tick \valid } ctrl outputs: { $procmux$36_CMP $procmux$35_CMP $procmux$34_CMP $procmux$33_CMP $0\state[1:0] } transition: 2'00 3'--0 -> 2'00 6'100000 transition: 2'00 3'--1 -> 2'01 6'100001 transition: 2'10 3'-0- -> 2'10 6'001010 transition: 2'10 3'01- -> 2'10 6'001010 transition: 2'10 3'11- -> 2'11 6'001011 transition: 2'01 3'-0- -> 2'01 6'010001 transition: 2'01 3'-1- -> 2'10 6'010010 transition: 2'11 3'-0- -> 2'11 6'000111 transition: 2'11 3'-1- -> 2'00 6'000100 4.7.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\state$163' from module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. 4.7.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. Removed 11 unused cells and 11 unused wires. 4.7.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\state$163' from module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Removing unused output signal $0\state[1:0] [0]. Removing unused output signal $0\state[1:0] [1]. 4.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\state$163' from module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- 4.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\state$163' from module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx': ------------------------------------- Information on FSM $fsm$\state$163 (\state): Number of input signals: 3 Number of output signals: 4 Number of state bits: 4 Input signals: 0: \valid 1: \tick 2: $eq$lib/uart_tx.v:162$28_Y Output signals: 0: $procmux$33_CMP 1: $procmux$34_CMP 2: $procmux$35_CMP 3: $procmux$36_CMP State encoding: 0: 4'---1 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 3'--0 -> 0 4'1000 1: 0 3'--1 -> 2 4'1000 2: 1 3'-0- -> 1 4'0010 3: 1 3'01- -> 1 4'0010 4: 1 3'11- -> 3 4'0010 5: 2 3'-1- -> 1 4'0100 6: 2 3'-0- -> 2 4'0100 7: 3 3'-1- -> 0 4'0001 8: 3 3'-0- -> 3 4'0001 ------------------------------------- 4.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\state$163' from module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. 4.8. Executing OPT pass (performing simple optimizations). 4.8.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 45 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 43 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 4 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 4 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 2 cells. 4.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu_top.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_down.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \ctr_up.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing cells in module \alu. Optimizing cells in module \alu_top. Optimizing cells in module \ctr_down. Optimizing cells in module \ctr_up. Performed a total of 0 changes. 4.8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 43 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 4 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 4 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 0 cells. 4.8.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $procdff$156 ($adff) from module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx (D = \data, Q = \shift_reg). Adding EN signal on $procdff$151 ($adff) from module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx (D = $0\bit_idx[2:0], Q = \bit_idx). Adding EN signal on $procdff$146 ($adff) from module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx (D = $0\clk_ctr[3:0], Q = \clk_ctr). Adding EN signal on $procdff$136 ($adff) from module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx (D = $procmux$95_Y, Q = \ready). Adding SRST signal on $procdff$157 ($dff) from module ctr_down (D = $procmux$117_Y, Q = \out_d, rval = 4'1111). Adding EN signal on $auto$ff.cc:337:slice$237 ($sdff) from module ctr_down (D = $sub$up_dw_alu_uart.v:58$6_Y [3:0], Q = \out_d). Adding SRST signal on $procdff$158 ($dff) from module ctr_up (D = $procmux$122_Y, Q = \out_u, rval = 4'0000). Adding EN signal on $auto$ff.cc:337:slice$239 ($sdff) from module ctr_up (D = $add$up_dw_alu_uart.v:44$3_Y [3:0], Q = \out_u). 4.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. Removed 7 unused cells and 19 unused wires. 4.8.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.8.9. Rerunning OPT passes. (Maybe there is more to do..) 4.8.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu_top.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_down.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_up.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.8.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing cells in module \alu. Optimizing cells in module \alu_top. Optimizing cells in module \ctr_down. Optimizing cells in module \ctr_up. Performed a total of 0 changes. 4.8.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 50 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 2 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 2 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 0 cells. 4.8.13. Executing OPT_DFF pass (perform DFF optimizations). 4.8.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. 4.8.15. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.8.16. Finished fast OPT passes. (There is nothing left to do.) 4.9. Executing WREDUCE pass (reducing word size of cells). Removed top 1 bits (of 2) from port B of cell $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$auto$opt_dff.cc:235:make_patterns_logic$224 ($ne). Removed top 1 bits (of 2) from port B of cell $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$auto$opt_dff.cc:235:make_patterns_logic$220 ($ne). Removed top 1 bits (of 2) from port B of cell $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$auto$fsm_map.cc:77:implement_pattern_cache$187 ($eq). Removed top 31 bits (of 32) from port B of cell $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$add$lib/uart_tx.v:146$26 ($add). Removed top 28 bits (of 32) from port Y of cell $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$add$lib/uart_tx.v:146$26 ($add). Removed top 31 bits (of 32) from port B of cell $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$add$lib/uart_tx.v:166$29 ($add). Removed top 29 bits (of 32) from port Y of cell $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$add$lib/uart_tx.v:166$29 ($add). Removed top 28 bits (of 32) from wire $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$add$lib/uart_tx.v:146$26_Y. Removed top 29 bits (of 32) from wire $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.$add$lib/uart_tx.v:166$29_Y. Removed top 4 bits (of 8) from port A of cell alu.$add$up_dw_alu_uart.v:71$9 ($add). Removed top 4 bits (of 8) from port B of cell alu.$add$up_dw_alu_uart.v:71$9 ($add). Removed top 3 bits (of 8) from port Y of cell alu.$add$up_dw_alu_uart.v:71$9 ($add). Removed top 1 bits (of 2) from port B of cell alu.$eq$up_dw_alu_uart.v:73$10 ($eq). Removed top 4 bits (of 8) from port A of cell alu.$sub$up_dw_alu_uart.v:74$11 ($sub). Removed top 4 bits (of 8) from port B of cell alu.$sub$up_dw_alu_uart.v:74$11 ($sub). Removed top 3 bits (of 8) from port Y of cell alu.$sub$up_dw_alu_uart.v:74$11 ($sub). Removed top 4 bits (of 8) from port A of cell alu.$and$up_dw_alu_uart.v:77$13 ($and). Removed top 4 bits (of 8) from port B of cell alu.$and$up_dw_alu_uart.v:77$13 ($and). Removed top 4 bits (of 8) from port Y of cell alu.$and$up_dw_alu_uart.v:77$13 ($and). Removed top 4 bits (of 8) from mux cell alu.$procmux$100 ($mux). Removed top 4 bits (of 8) from wire alu.$3\result[7:0]. Removed top 3 bits (of 8) from wire alu.$add$up_dw_alu_uart.v:71$9_Y. Removed top 4 bits (of 8) from wire alu.$and$up_dw_alu_uart.v:77$13_Y. Removed top 5 bits (of 8) from wire alu.$sub$up_dw_alu_uart.v:74$11_Y. Removed top 31 bits (of 32) from port B of cell ctr_down.$sub$up_dw_alu_uart.v:58$6 ($sub). Removed top 28 bits (of 32) from port Y of cell ctr_down.$sub$up_dw_alu_uart.v:58$6 ($sub). Removed top 28 bits (of 32) from wire ctr_down.$sub$up_dw_alu_uart.v:58$6_Y. Removed top 31 bits (of 32) from port B of cell ctr_up.$add$up_dw_alu_uart.v:44$3 ($add). Removed top 28 bits (of 32) from port Y of cell ctr_up.$add$up_dw_alu_uart.v:44$3 ($add). Removed top 28 bits (of 32) from wire ctr_up.$add$up_dw_alu_uart.v:44$3_Y. 4.10. Executing PEEPOPT pass (run peephole optimizers). 4.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. Removed 0 unused cells and 8 unused wires. 4.12. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx: creating $macc model for $add$lib/uart_tx.v:146$26 ($add). creating $macc model for $add$lib/uart_tx.v:166$29 ($add). creating $alu model for $macc $add$lib/uart_tx.v:166$29. creating $alu model for $macc $add$lib/uart_tx.v:146$26. creating $alu cell for $add$lib/uart_tx.v:146$26: $auto$alumacc.cc:512:replace_alu$249 creating $alu cell for $add$lib/uart_tx.v:166$29: $auto$alumacc.cc:512:replace_alu$252 created 2 $alu and 0 $macc cells. Extracting $alu and $macc cells in module alu: creating $macc model for $add$up_dw_alu_uart.v:71$9 ($add). creating $macc model for $sub$up_dw_alu_uart.v:74$11 ($sub). creating $alu model for $macc $sub$up_dw_alu_uart.v:74$11. creating $alu model for $macc $add$up_dw_alu_uart.v:71$9. creating $alu cell for $add$up_dw_alu_uart.v:71$9: $auto$alumacc.cc:512:replace_alu$255 creating $alu cell for $sub$up_dw_alu_uart.v:74$11: $auto$alumacc.cc:512:replace_alu$258 created 2 $alu and 0 $macc cells. Extracting $alu and $macc cells in module alu_top: created 0 $alu and 0 $macc cells. Extracting $alu and $macc cells in module ctr_down: creating $macc model for $sub$up_dw_alu_uart.v:58$6 ($sub). creating $alu model for $macc $sub$up_dw_alu_uart.v:58$6. creating $alu cell for $sub$up_dw_alu_uart.v:58$6: $auto$alumacc.cc:512:replace_alu$261 created 1 $alu and 0 $macc cells. Extracting $alu and $macc cells in module ctr_up: creating $macc model for $add$up_dw_alu_uart.v:44$3 ($add). creating $alu model for $macc $add$up_dw_alu_uart.v:44$3. creating $alu cell for $add$up_dw_alu_uart.v:44$3: $auto$alumacc.cc:512:replace_alu$264 created 1 $alu and 0 $macc cells. 4.13. Executing SHARE pass (SAT-based resource sharing). 4.14. Executing OPT pass (performing simple optimizations). 4.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 50 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 2 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 2 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 0 cells. 4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu_top.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_down.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_up.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing cells in module \alu. Optimizing cells in module \alu_top. Optimizing cells in module \ctr_down. Optimizing cells in module \ctr_up. Performed a total of 0 changes. 4.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 50 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 2 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 2 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 0 cells. 4.14.6. Executing OPT_DFF pass (perform DFF optimizations). 4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. 4.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.14.9. Finished fast OPT passes. (There is nothing left to do.) 4.15. Executing MEMORY pass. 4.15.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 4.15.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 4.15.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 4.15.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. 4.15.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.15.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.15.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. 4.15.10. Executing MEMORY_COLLECT pass (generating $mem cells). 4.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. 4.17. Executing OPT pass (performing simple optimizations). 4.17.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.17.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 45 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 44 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 2 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 2 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 1 cells. 4.17.3. Executing OPT_DFF pass (perform DFF optimizations). 4.17.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. Removed 0 unused cells and 6 unused wires. 4.17.5. Finished fast OPT passes. 4.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 4.19. Executing OPT pass (performing simple optimizations). 4.19.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.19.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 44 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 2 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 2 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 0 cells. 4.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu_top.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_down.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_up.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing cells in module \alu. Consolidated identical input bits for $mux cell $procmux$109: Old ports: A={ 4'0000 $3\result[7:0] }, B={ $auto$wreduce.cc:514:run$246 [7] $auto$wreduce.cc:514:run$246 [7] $auto$wreduce.cc:514:run$246 [7] $auto$wreduce.cc:514:run$246 [7] $auto$wreduce.cc:514:run$246 [3:0] }, Y=$2\result[7:0] New ports: A={ 1'0 $3\result[7:0] }, B={ $auto$wreduce.cc:514:run$246 [7] $auto$wreduce.cc:514:run$246 [3:0] }, Y=$2\result[7:0] [4:0] New connections: $2\result[7:0] [7:5] = { $2\result[7:0] [4] $2\result[7:0] [4] $2\result[7:0] [4] } Optimizing cells in module \alu. Consolidated identical input bits for $mux cell $procmux$115: Old ports: A=$2\result[7:0], B={ 3'000 $add$up_dw_alu_uart.v:71$9_Y }, Y=\result New ports: A={ $2\result[7:0] [4] $2\result[7:0] [4:0] }, B={ 1'0 $add$up_dw_alu_uart.v:71$9_Y }, Y=\result [5:0] New connections: \result [7:6] = { \result [5] \result [5] } Optimizing cells in module \alu. Optimizing cells in module \alu_top. Optimizing cells in module \ctr_down. Optimizing cells in module \ctr_up. Performed a total of 2 changes. 4.19.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 44 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 2 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 2 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 0 cells. 4.19.6. Executing OPT_SHARE pass. 4.19.7. Executing OPT_DFF pass (perform DFF optimizations). 4.19.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. 4.19.9. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.19.10. Rerunning OPT passes. (Maybe there is more to do..) 4.19.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \alu_top.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_down.. Creating internal representation of mux trees. No muxes found in this module. Running muxtree optimizer on module \ctr_up.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 4.19.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing cells in module \alu. Optimizing cells in module \alu_top. Optimizing cells in module \ctr_down. Optimizing cells in module \ctr_up. Performed a total of 0 changes. 4.19.13. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 44 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 9 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 2 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 2 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 0 cells. 4.19.14. Executing OPT_SHARE pass. 4.19.15. Executing OPT_DFF pass (perform DFF optimizations). 4.19.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. 4.19.17. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.19.18. Finished fast OPT passes. (There is nothing left to do.) 4.20. Executing TECHMAP pass (map to technology primitives). 4.20.1. Executing Verilog-2005 frontend: /foss/tools/yosys/bin/../share/yosys/techmap.v Parsing Verilog input from `/foss/tools/yosys/bin/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.20.2. Continuing TECHMAP pass. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $xor. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using extmapper simplemap for cells of type $pos. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $and. Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_90_alu for cells of type $alu. Using template $paramod$b85fbb3374a1d9ba7ee4f4d6323c30f939df3ada\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $eq. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000101 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000101 for cells of type $lcu. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $adffe. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $adff. Using template $paramod$constmap:ee5af906ae0d3d414c6a0471604c553ef70c8e09$paramod$92adee9538f2381d8e5006822c900eb986d754e8\_90_shift_shiftx for cells of type $shiftx. Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. No more expansions possible. 4.21. Executing OPT pass (performing simple optimizations). 4.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 145 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 135 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 78 cells of `\alu'. Finding duplicate cells in `\alu'. Computing hashes of 74 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 20 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 16 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Computing hashes of 15 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 15 cells. 4.21.3. Executing OPT_DFF pass (perform DFF optimizations). 4.21.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. Removed 39 unused cells and 353 unused wires. 4.21.5. Finished fast OPT passes. 4.22. Executing ABC pass (technology mapping using ABC). 4.22.1. Extracting gate netlist of module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx' to `/input.blif'.. 4.22.1.1. Executed ABC. Extracted 92 gates and 113 wires to a netlist network with 20 inputs and 16 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 00:59:35) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /tmp/yosys-abc-ul3wJr/stdcells.genlib ABC: + strash ABC: + dretime ABC: + map ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.22.1.2. Re-integrating ABC results. ABC RESULTS: AND cells: 2 ABC RESULTS: ANDNOT cells: 29 ABC RESULTS: MUX cells: 7 ABC RESULTS: NAND cells: 4 ABC RESULTS: NOR cells: 1 ABC RESULTS: NOT cells: 5 ABC RESULTS: OR cells: 19 ABC RESULTS: ORNOT cells: 5 ABC RESULTS: XNOR cells: 2 ABC RESULTS: XOR cells: 3 ABC RESULTS: internal signals: 77 ABC RESULTS: input signals: 20 ABC RESULTS: output signals: 16 Removing temp directory. 4.22.2. Extracting gate netlist of module `\alu' to `/input.blif'.. 4.22.2.1. Executed ABC. Extracted 67 gates and 78 wires to a netlist network with 10 inputs and 6 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 00:59:35) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /tmp/yosys-abc-ul3wJr/stdcells.genlib ABC: + strash ABC: + dretime ABC: + map ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.22.2.2. Re-integrating ABC results. ABC RESULTS: AND cells: 4 ABC RESULTS: ANDNOT cells: 18 ABC RESULTS: MUX cells: 9 ABC RESULTS: NAND cells: 2 ABC RESULTS: NOR cells: 3 ABC RESULTS: OR cells: 6 ABC RESULTS: ORNOT cells: 2 ABC RESULTS: XNOR cells: 7 ABC RESULTS: XOR cells: 7 ABC RESULTS: internal signals: 62 ABC RESULTS: input signals: 10 ABC RESULTS: output signals: 6 Removing temp directory. 4.22.3. Extracting gate netlist of module `\alu_top' to `/input.blif'.. Don't call ABC as there is nothing to map. 4.22.3.1. Executed ABC. Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. Removing temp directory. 4.22.4. Extracting gate netlist of module `\ctr_down' to `/input.blif'.. 4.22.4.1. Executed ABC. Extracted 11 gates and 15 wires to a netlist network with 4 inputs and 4 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 00:59:35) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /tmp/yosys-abc-ul3wJr/stdcells.genlib ABC: + strash ABC: + dretime ABC: + map ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.22.4.2. Re-integrating ABC results. ABC RESULTS: ANDNOT cells: 1 ABC RESULTS: NOT cells: 2 ABC RESULTS: OR cells: 1 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 2 ABC RESULTS: internal signals: 7 ABC RESULTS: input signals: 4 ABC RESULTS: output signals: 4 Removing temp directory. 4.22.5. Extracting gate netlist of module `\ctr_up' to `/input.blif'.. 4.22.5.1. Executed ABC. Extracted 6 gates and 10 wires to a netlist network with 4 inputs and 4 outputs. Running ABC script: /abc.script ABC: UC Berkeley, ABC 1.01 (compiled Feb 14 2026 00:59:35) ABC: abc 01> empty ABC: abc 01> source /abc.script ABC: + read_blif /input.blif ABC: + read_library /tmp/yosys-abc-ul3wJr/stdcells.genlib ABC: + strash ABC: + dretime ABC: + map ABC: + write_blif /output.blif ABC: ABC: YOSYS_ABC_DONE 4.22.5.2. Re-integrating ABC results. ABC RESULTS: ANDNOT cells: 1 ABC RESULTS: NAND cells: 1 ABC RESULTS: NOT cells: 1 ABC RESULTS: XNOR cells: 1 ABC RESULTS: XOR cells: 2 ABC RESULTS: internal signals: 2 ABC RESULTS: input signals: 4 ABC RESULTS: output signals: 4 Removing temp directory. Removing global temp directory. 4.23. Executing OPT pass (performing simple optimizations). 4.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx. Optimizing module alu. Optimizing module alu_top. Optimizing module ctr_down. Optimizing module ctr_up. 4.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Computing hashes of 98 cells of `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding duplicate cells in `$paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx'. Finding identical cells in module `\alu'. Computing hashes of 58 cells of `\alu'. Finding duplicate cells in `\alu'. Computing hashes of 56 cells of `\alu'. Finding duplicate cells in `\alu'. Finding identical cells in module `\alu_top'. Computing hashes of 4 cells of `\alu_top'. Finding duplicate cells in `\alu_top'. Finding identical cells in module `\ctr_down'. Computing hashes of 11 cells of `\ctr_down'. Finding duplicate cells in `\ctr_down'. Finding identical cells in module `\ctr_up'. Computing hashes of 10 cells of `\ctr_up'. Finding duplicate cells in `\ctr_up'. Removed a total of 2 cells. 4.23.3. Executing OPT_DFF pass (perform DFF optimizations). 4.23.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx.. Finding unused cells or wires in module \alu.. Finding unused cells or wires in module \alu_top.. Finding unused cells or wires in module \ctr_down.. Finding unused cells or wires in module \ctr_up.. Removed 1 unused cells and 153 unused wires. 4.23.5. Finished fast OPT passes. 4.24. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `alu_top'. Setting top module to alu_top. 4.24.1. Analyzing design hierarchy.. Top module: \alu_top Used module: \alu Used module: \ctr_down Used module: $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx Used module: \ctr_up 4.24.2. Analyzing design hierarchy.. Top module: \alu_top Used module: \alu Used module: \ctr_down Used module: $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx Used module: \ctr_up Removed 0 unused modules. 4.25. Printing statistics. === $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx === +----------Local Count, excluding submodules. | 81 wires 108 wire bits 10 public wires 32 public wire bits 6 ports 13 port bits 97 cells 29 $_ANDNOT_ 2 $_AND_ 15 $_DFFE_PN0P_ 1 $_DFFE_PN1P_ 3 $_DFF_PN0_ 2 $_DFF_PN1_ 7 $_MUX_ 4 $_NAND_ 1 $_NOR_ 4 $_NOT_ 5 $_ORNOT_ 19 $_OR_ 2 $_XNOR_ 3 $_XOR_ === alu === +----------Local Count, excluding submodules. | 54 wires 68 wire bits 4 public wires 18 public wire bits 4 ports 18 port bits 56 cells 18 $_ANDNOT_ 4 $_AND_ 9 $_MUX_ 2 $_NAND_ 3 $_NOR_ 2 $_ORNOT_ 6 $_OR_ 6 $_XNOR_ 6 $_XOR_ === alu_top === +----------Local Count, excluding submodules. | 11 wires 25 wire bits 11 public wires 25 public wire bits 8 ports 9 port bits 4 submodules 1 $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx 1 alu 1 ctr_down 1 ctr_up === ctr_down === +----------Local Count, excluding submodules. | 8 wires 14 wire bits 4 public wires 7 public wire bits 4 ports 7 port bits 11 cells 1 $_ANDNOT_ 2 $_NOT_ 1 $_OR_ 4 $_SDFFE_PN1P_ 1 $_XNOR_ 2 $_XOR_ === ctr_up === +----------Local Count, excluding submodules. | 8 wires 17 wire bits 4 public wires 7 public wire bits 4 ports 7 port bits 10 cells 1 $_ANDNOT_ 1 $_NAND_ 1 $_NOT_ 4 $_SDFFE_PN0P_ 1 $_XNOR_ 2 $_XOR_ === design hierarchy === +----------Count including submodules. | 174 alu_top 97 $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx 56 alu 11 ctr_down 10 ctr_up +----------Count including submodules. | 162 wires 232 wire bits 33 public wires 89 public wire bits 26 ports 54 port bits - memories - memory bits - processes 174 cells 49 $_ANDNOT_ 6 $_AND_ 15 $_DFFE_PN0P_ 1 $_DFFE_PN1P_ 3 $_DFF_PN0_ 2 $_DFF_PN1_ 16 $_MUX_ 7 $_NAND_ 4 $_NOR_ 7 $_NOT_ 7 $_ORNOT_ 26 $_OR_ 4 $_SDFFE_PN0P_ 4 $_SDFFE_PN1P_ 10 $_XNOR_ 13 $_XOR_ 4 submodules 1 $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx 1 alu 1 ctr_down 1 ctr_up 4.26. Executing CHECK pass (checking for obvious problems). Checking module $paramod$f6ca900275f16cbf280bd6b10c3f9b8b97db50c1\uart_tx... Checking module alu... Checking module alu_top... Checking module ctr_down... Checking module ctr_up... Found and reported 0 problems.