Presentation
Functionality
- Small RISC-V SoC
- Includes Custom 1 KB ROM and GPIO and optional RAM
- Demonstrates a minimal micro-controller architecture
- Runs a hard-coded blink program
Design Flow Summary
The design was implemented using a fully open-source ASIC toolchain targeting the Sky130 process.
- The system was first written in Verilog RTL, describing a minimal RISC-V SoC architecture.
- Functional verification was performed using Icarus Verilog (iverilog),
vvp, and waveform inspection in Surfer. - The RTL was synthesized to a gate-level netlist using Yosys.
- Physical design was completed using the LibreLane flow, which orchestrates the open-source toolchain including OpenROAD, performing floorplanning, placement, and routing.
- The final layout was exported as a GDSII file.
- Verification was performed using Magic (DRC), KLayout (DRC), and Netgen (LVS).
| Pin | Direction | Description |
|---|---|---|
| clk | input | system clock |
| rst | input | reset |
| gpio[0] | output | LED / IO |
| gpio[7:1] | output | general purpose IO |
| Stage | Tools | Purpose |
|---|---|---|
| RTL Simulation | Icarus Verilog (iverilog), vvp, Surfer |
RTL simulation and waveform inspection |
| Synthesis | Yosys | Convert Verilog RTL to gate-level netlist |
| PnR Flow | OpenROAD, LibreLane | Placement, routing and ASIC flow automation |
| Layout / GDS | KLayout | Layout inspection and visualization |
| Process | Sky130 | open-source PDK |
| Verification | Magic, Netgen | DRC and LVS verification |
| Visualization | Inkscape, Blender | Diagrams and chip visualization |
Pinout
Package: SOIC-16 Pins: 16 Power: VDD / VSS Signals: GPIO[7:0], CLK, RESET
┌──────────────────┐
VDD ─┤ 1 16 ├─ VSS
GPIO0 ─┤ 2 15 ├─ GPIO7
GPIO1 ─┤ 3 14 ├─ GPIO6
GPIO2 ─┤ 4 smari 13 ├─ GPIO5
GPIO3 ─┤ 5 202b7 12 ├─ GPIO4
CLK ─┤ 6 11 ├─ RESET
NC ─┤ 7 10 ├─ NC
NC ─┤ 8 9 ├─ NC
└──────────────────┘
Pin Description
| Pin | Name | Description |
|---|---|---|
| 1 | VDD | Power supply |
| 16 | VSS | Ground |
| 6 | CLK | System clock |
| 11 | RESET | Reset input |
| 2–5 | GPIO0–GPIO3 | General purpose input/output |
| 12–15 | GPIO4–GPIO7 | General purpose input/output |
| 7–10 | NC | Not connected |
Packaging
Wirebonding
| Parameter | Value | Why It Matters |
|---|---|---|
| Wire diameter | 25 µm | Standard bond wire size for signal and power |
| Loop height | 100 µm | Clears the die and keeps inductance moderate |
| Bond pad size | 80 µm | Compatible with typical Sky130 pad sizes |
| Wire length | 3 mm | Short connections reduce resistance and inductance |
Wirebond Diagram
The die pads are wirebonded to a 16-pin package. Power (VDD) and ground (VSS) are placed on opposite sides of the package to simplify routing and reduce noise coupling. GPIO signals are grouped along the bottom of the die. Clock and reset pads are positioned close to the package pins to keep bond wires short.
Eval Board Components
+--------------------------------------------------+
| Evaluation Board |
| |
| +---------+ +-----------+ |
| | Power |---->| Regulator |----+ |
| | In | +-----------+ | |
| +---------+ | |
| v |
| +------+ |
| |Decap | |
| +------+ |
| | |
| +--------------+ |
| Clock Oscillator -------->| CLK | |
| Reset Button ------------>| RESET | |
| GPIO Header <-----------> | GPIO[7:0] | |
| LED <-------------------- | GPIO0 | |
| | smari | |
| +--------------+ |
| |
+--------------------------------------------------+
An LED connected to GPIO0 provides a simple visual indicator that the firmware is running by blinking when the GPIO output toggles.
DRC / LVS Verification
Final verification was performed using Magic, KLayout, and Netgen to ensure the layout meets design rules and matches the synthesized netlist.
I looked in a file called drc_violations.klayout.json and found no violations the first few lines looked like this:
{
"dnwell.1": 0,
"dnwell.2": 0,
"nwell.1": 0,
"nwell.2a": 0,
"nwell.6": 0,
"nwell.9": 0,
"hvtp.1": 0,
"hvtp.2": 0,
"pwde.1": 0,
"pwde.2": 0,
"hvtr.1": 0,
"hvtr.2": 0,
"hvtr.2_a": 0,
"lvtn.1a": 0,
"lvtn.2": 0,
"MR_lvtn.OVL.2": 0,
"ncm.1": 0,
"ncm.2a": 0,
"difftap.1": 0,
"difftap.1_a": 0,
"difftap.2": 0,
...
I also looked at drc_violations.magic.rpt
I then looked at netgen-lvs end of the file had this:
Class: sky130_fd_sc_hd__nor2_2 instances: 6
Class: sky130_fd_sc_hd__nor2_4 instances: 8
Class: sky130_fd_sc_hd__nor2_8 instances: 18
Circuit contains 3884 nets.
Circuit 1 contains 3898 devices, Circuit 2 contains 3898 devices.
Circuit 1 contains 3884 nets, Circuit 2 contains 3884 nets.
Final result:
Circuits match uniquely.
.
Logging to file "/foss/designs/s8/final_project/flow2_FemtoRV32/runs/RUN_2026-03-11_20-08-43/68-netgen-lvs/reports/lvs.netgen.rpt" disabled
LVS Done.
Both DRC checks reported zero violations and the LVS comparison confirmed that the layout matches the synthesized design, indicating that the chip is ready for fabrication.
Top module code
Detailed overview of the codes in spiral 1, source code: src.zip
Final Graphic Data System file can me found here: soc_top.gds
Acknowledgments
I knew microelectronics would be a challenge, but it turned out to be much deeper than I expected. Every time I thought I understood something, another layer appeared underneath it.
Four weeks ago I had never touched an ASIC design flow or any of these tools. Going from a few lines of Verilog to a routed layout that passes DRC and LVS felt pretty wild at times. Parts of it were confusing, parts frustrating, and some moments surprisingly satisfying when things finally worked. Having people around who were willing to answer questions and explain things made a big difference.
I'm grateful to the Fab Futures professors Jennifer, Andreas, Alex, and Neil. Also to the support team Julian and Jean-Michel, along with my classmates, for creating such a supportive learning environment.