FPGA
Board I'm working with - notes and links
- Gowin RUNBER FPGA Development Board
- RUNBER Development Board Hardware Instructions
- Board is red with - mini eye board gw1n 1.2 marked on it
- Where is the schematic for RUNBER FPGA Development Board Ver. 1.2?
- FPGA Model - GW1N-UV4LQ144C6/I5
- GW1N (Traditional FPGA)
- GW1N series of FPGA Products - Package & Pinout User Guide
- GW1N series of FPGA Products Data Sheet

Trouble shooting
We have version v1.2 in the lab and it seams like there may be some defects.
- Issue for Gowin RUNBER FPGA Ver. 1.2
- Cause and solution of Gowin RUNBER - this page is in Japanese
- Gowin notes
Toolchain
Basic Flow Example
# 1. Synthesize Verilog to JSON netlist
yosys -p "read_verilog design.v; synth_gowin -json design.json"
# 2. Place and route the design
nextpnr-himbaechel --json design.json --write placed.json \
--device GW1NR-LV9QN88PC6/I5 \
--vopt cst=constraints.cst
# 3. Generate bitstream
gowin_pack -d GW1N-9C -o final.fs placed.json
# 4. Program the FPGA
openFPGALoader -b tangnano9k final.fs
I'm trying this loads to the board but and status light done lights up but nothing else works.