Mermaid

Mermaid is a code-based diagram tool that I use frequently. Because diagrams are written as text, they are easy to version control, update and work well with markdown.

Mermaid - syntax-reference Theme Configuration

Excalidraw is also worth mentioning. It’s an online diagram tool that requires no signup, and it also supports Mermaid.

The diagrams below are not organized. Some eventually became part of the main documentation. Others remain as experiments or mental mappings.

updown counter from session 1

flowchart TD
    Start([Power On System]) --> Initialize[Initialize Counter to Zero]
    Initialize --> WaitClock{Wait for Clock Edge}

    WaitClock -- No --> WaitClock
    WaitClock -- Yes --> CheckReset{Reset Pressed?}

    CheckReset -- Yes --> Initialize
    CheckReset -- No --> ReadDirection{Read Up/Down Switch}

    ReadDirection -- Up --> CheckMax{Value == Max?}
    ReadDirection -- Down --> CheckMin{Value == 0?}

    CheckMax -- Yes --> RollOverMin[Set Counter to 0]
    CheckMax -- No --> Increment[Counter = Counter + 1]

    CheckMin -- Yes --> RollOverMax[Set Counter to Max]
    CheckMin -- No --> Decrement[Counter = Counter - 1]

    RollOverMin --> UpdateOutput[Update Output Display]
    Increment --> UpdateOutput
    RollOverMax --> UpdateOutput
    Decrement --> UpdateOutput

    UpdateOutput --> WaitClock

graph TD
    Start([System Power On]) --> Initialize[Initialize Counter to Zero]
    Initialize --> WaitClock{Wait for Clock Edge}

    WaitClock -- Rising Edge --> CheckReset{Reset Active?}

    CheckReset -- Yes --> ResetValue[Set Counter to 0]
    ResetValue --> UpdateDisplay

    CheckReset -- No --> CheckDirection{Direction Switch?}

    CheckDirection -- Up --> Increment[Current Value + 1]
    CheckDirection -- Down --> Decrement[Current Value - 1]

    Increment --> CheckOverflow{Value > Max?}
    CheckOverflow -- Yes --> WrapToZero[Set Value to 0]
    CheckOverflow -- No --> UpdateDisplay

    Decrement --> CheckUnderflow{Value < 0?}
    CheckUnderflow -- Yes --> WrapToMax[Set Value to Max]
    CheckUnderflow -- No --> UpdateDisplay

    WrapToZero --> UpdateDisplay
    WrapToMax --> UpdateDisplay

    UpdateDisplay[Send Binary to Decoder]
    UpdateDisplay --> SegmentDrive[Drive Seven Segment LEDs]
    SegmentDrive --> WaitClock

classDiagram
    class UpDownCounter {
        -int currentValue
        -int maxValue
        -bool direction
        -bool resetSignal
        +processClockEdge()
        +setDirection(bool dir)
        +triggerReset()
        -increment()
        -decrement()
    }

    class Clock {
        -float frequency
        -bool currentState
        +pulse()
    }

    class ControlSwitch {
        -bool state
        +toggle()
        +getState() bool
    }

    class SevenSegmentDisplay {
        -int inputData
        +decode()
        +refresh()
    }

    class FlipFlop {
        -bool q
        -bool qNot
        +trigger(bool j, bool k)
        +reset()
    }

    UpDownCounter "1" *-- "3" FlipFlop : contains
    Clock --> UpDownCounter : triggers
    ControlSwitch --> UpDownCounter : sets direction
    UpDownCounter --> SevenSegmentDisplay : provides data

sequenceDiagram
    participant User
    participant Clock
    participant Switch as ControlSwitch
    participant Counter as UpDownCounter
    participant FF as FlipFlops
    participant Display as SevenSegmentDisplay

    User->>Switch: Set Direction (Up/Down)
    Switch-->>Counter: Update direction state

    loop Every Clock Cycle
        Clock->>Counter: Pulse (Rising Edge)

        alt Reset Signal Active
            Counter->>FF: Clear All Bits
            FF-->>Counter: State = 0
        else Direction == Up
            Counter->>FF: Request Increment
            FF-->>Counter: New Binary State
        else Direction == Down
            Counter->>FF: Request Decrement
            FF-->>Counter: New Binary State
        end

        Counter->>Display: Send Current Value
        Display->>Display: Decode to Patterns
        Display-->>User: Show Decimal Value
    end

verilog overview

classDiagram
    class Verilog_Fundamentals {
        +Module Declaration
        +Port Mapping
        +Data Types
        +Operators
    }

    class Data_Types {
        +wire Physical_connection
        +reg Procedural_variable
        +integer Signed_32bit
        +parameter Constant_value
        +logic SV_universal_type
    }

    class Operators {
        +Arithmetic_Add_Sub_Mul_Div
        +Bitwise_NOT_AND_OR_XOR
        +Logical_NOT_AND_OR
        +Reduction_AND_NAND_OR_NOR
        +Relational_LT_GT_LE_GE_EQ_NE
        +Shift_Logical_Arithmetic
        +Concatenation_Braces
        +Replication_Braces
    }

    class Procedural_Blocks {
        +always_at_sensitivity_list
        +initial_Run_once_at_T0
        +always_ff_Sequential_logic
        +always_comb_Combinational_logic
        +always_latch_Latch_logic
    }

    class Assignments {
        +Continuous_assign_wire
        +Blocking_Equal_combinational
        +NonBlocking_LE_sequential
    }

    class Control_Flow {
        +if_else_statements
        +case_casex_casez
        +for_while_repeat_loops
        +begin_end_blocks
    }

    class Hierarchy {
        +Instantiation_module_instance
        +Positional_Mapping
        +Named_Mapping
        +Generate_blocks
    }

    Verilog_Fundamentals --> Data_Types
    Verilog_Fundamentals --> Operators
    Verilog_Fundamentals --> Procedural_Blocks
    Procedural_Blocks --> Assignments
    Procedural_Blocks --> Control_Flow
    Verilog_Fundamentals --> Hierarchy

PDK

flowchart TB

A["SkyWater Process\nsky130"]
B["Design Rules\nDRC / Layout Constraints"]
C["Device Models\nBSIM SPICE Models"]
D["Standard Cell Library\nfd / ef / osu"]
E["Library Flavor\nhd / hs / ms / hdl / ls"]
F["Logic Cell\ndfxbp_1, inv_1, nand2_1"]
G["Transistor-Level Implementation\nCMOS Network"]
H["Physical Layout\nGDSII Geometry"]

A --> B
B --> C
C --> D
D --> E
E --> F
F --> G
G --> H

flowchart LR

    P["Sky130 Process"]
    R["Design Rules"]
    M["Device Models"]
    L["Libraries\nfd / ef / osu"]
    F["Flavor\nhd / hs / ms"]
    C["Cells\ninv, nand, dff"]
    T["Transistor Network"]
    G["Layout"]

    P --> R --> M --> L --> F --> C --> T --> G

flowchart LR

    P["Process"]
    L["Libraries"]
    C["Cells"]
    T["Transistors"]
    G["Geometry"]

    P --> L --> C --> T --> G