Markdown
SKY130 Standard Cell Library Overview
| Layer | What It Is | Who Controls It | What Can Change | What Cannot Change |
|---|---|---|---|---|
| Process (Sky130) | The fabrication technology (130nm CMOS) | SkyWater Foundry | Nothing (fixed silicon process) | Transistor physics, layers, materials |
| Design Rules | Geometric rules for layout (spacing, width, enclosure) | SkyWater Foundry | Nothing (must follow rules) | Poly spacing, metal width, well spacing, etc. |
| Device Models | SPICE transistor models (BSIM) | SkyWater Foundry | Nothing (same models for all libraries) | Electrical behavior of MOSFETs |
Standard Cell Library (fd_sc_*, ef_sc_*, osu_sc_*) |
Pre-designed logic cells built using the process | Foundry or Third Parties | Transistor sizing, layout style, cell height, drive strength options | Must obey process rules |
Library Flavor (hd, hs, ms, hdl, ls) |
Performance/area/leakage tradeoff variant | Library Designer | Speed vs area vs leakage optimization | Logical functionality of the cell |
One Process, Multiple Libraries
| Category | Example | Meaning |
|---|---|---|
| Process | sky130 |
130nm SkyWater fabrication process |
| Source | fd, ef, osu |
Who created the library (Foundry, Efabless, OSU) |
| Type | sc |
Standard cell digital logic |
| Flavor | hd, hs, ms, hdl, ls |
Density/speed/leakage tradeoff |
| Cell | dfxbp_1 |
Specific logic function + drive strength |
Synthesis s6
| Stage | Command | Purpose |
|---|---|---|
| Read design | read_verilog |
Load the Verilog source files |
| Build hierarchy | hierarchy -check -top |
Define the top module and verify module connections |
| RTL synthesis | synth -top |
Convert behavioral RTL into generic logic gates |
| Flip-flop mapping | dfflibmap |
Map generic flip-flops to Sky130 sequential cells |
| Logic mapping | abc |
Map combinational logic to Sky130 standard cells |
| Cleanup | clean |
Remove unused wires and temporary structures |
| Output net-list | write_verilog |
Export the final gate-level net-list |