ROM@FABFUTURE
ROM
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    • ROM
    • DAY1 | INTRO
    • DAY2 | ANALOG BASICS
    • DAY3 | SCHEMATIC DESIGN AND SIMULATION
    • DAY4 | FABRICATION BASICS
    • DAY5 | RTL DESIGN
    • DAY6 | SYNTHESIS & PHYSICAL DESIGN
    • DAY7 | PACKAGING & BOARD DESIGN
    • DAY8 | PRESENTATIONS
    • ABOUT VERILOG
    • ROM
    • DAY1 | INTRO
    • DAY2 | ANALOG BASICS
    • DAY3 | SCHEMATIC DESIGN AND SIMULATION
    • DAY4 | FABRICATION BASICS
    • DAY5 | RTL DESIGN
    • DAY6 | SYNTHESIS & PHYSICAL DESIGN
    • DAY7 | PACKAGING & BOARD DESIGN
    • DAY8 | PRESENTATIONS
    • ABOUT VERILOG

    ROM
    I am here to dive into the microelectronics processes as much as possible. With a very busy schedule. I’ll take the lecture for sure. And I will struggle to make time to do the assignments. I already apologize for this.
    My XPRNS
    My LINKEDIN
    I run FABLAB UNIVERSITÉ PARIS-SACLAY
    I curate and produce EMPOWER UNIVERSITÉ PARIS-SACLAY
    March 1, 2026
    Copyright 2026 Romain Di Vozzo - Creative Commons Attribution Non Commercial
    Made with Material for MkDocs