Session2 - Analog Baisics¶
(Thur Feb 19) This course is full of the knowledge I’ve wanted to learn. I just don’t have enough time to make it my own
Homework¶
1. Modify the AND gate netlist to create an OR gate instead¶
(Hint: Swap the series/parallel arrangement of transistors) falstad
Original AND Gate
* CMOS AND Gate (1V supply) = NAND + Inverter
Vsup VDD 0 1
* NAND pull-up network (PMOS parallel)
Mp1 nNAND A VDD VDD mosp L=0.35u W=2u
Mp2 nNAND B VDD VDD mosp L=0.35u W=2u
* NAND pull-down network (NMOS series)
Mn1 nNAND A nPD 0 mosn L=0.35u W=2u
Mn2 nPD B 0 0 mosn L=0.35u W=2u
* Output inverter
Mp3 OUT nNAND VDD VDD mosp L=0.35u W=2u
Mn3 OUT nNAND 0 0 mosn L=0.35u W=2u
Abbreviation
VDD: Drain Supply Voltage
Mp: PMOS Transistor
Mn: NMOS Transistor
mosn: NMOS model
nNAND: NAND output node
nPD: Pull-Down node
nPU: Pull-Up node
Modified to OR gate
* CMOS OR Gate (1V supply) = NOR + Inverter
Vsup VDD 0 1
* NOR pull-up network (PMOS series)
Mp1 nNOR A nPU VDD mosp L=0.35u W=2u
Mp2 nPU B VDD VDD mosp L=0.35u W=2u
* NOR pull-down network (NMOS parallel)
Mn1 nNOR A 0 0 mosn L=0.35u W=2u
Mn2 nNOR B 0 0 mosn L=0.35u W=2u
* Output inverter
Mp3 OUT nNOR VDD VDD mosp L=0.35u W=2u
Mn3 OUT nNOR 0 0 mosn L=0.35u W=2u
Complete AND Gate Netlist Example
* AND Gate using CMOS
* Power supply (DC voltage source)
Vdd vdd gnd 1.8
* Input signals (PWL: Piecewise Linear)
Va a gnd PWL(0n 0 10n 0 11n 1.8 50n 1.8 51n 0 100n 0)
Vb b gnd PWL(0n 0 25n 0 26n 1.8 75n 1.8 76n 0 100n 0)
* NAND gate
* PMOS pull-up (parallel)
Mp1 nand_out a vdd vdd pmos L=1u W=2u
Mp2 nand_out b vdd vdd pmos L=1u W=2u
* NMOS pull-down (series)
Mn1 nand_out a mid gnd nmos L=1u W=1u
Mn2 mid b gnd gnd nmos L=1u W=1u
* Inverter (to make AND from NAND)
Mp3 out nand_out vdd vdd pmos L=1u W=2u
Mn3 out nand_out gnd gnd nmos L=1u W=1u
* Transistor models
.model nmos nmos (vth0=0.4)
.model pmos pmos (vth0=-0.4)
* Simulation control
.control
tran 0.1n 100n
plot v(a) v(b) v(out)
.endc
.end
Complete OR Gate Netlist Example
* OR Gate using CMOS (implemented as NOR + inverter)
* Power supply (DC voltage source)
Vdd vdd gnd 1.8
* Input signals (PWL: Piecewise Linear)
Va a gnd PWL(0n 0 10n 0 11n 1.8 50n 1.8 51n 0 100n 0)
Vb b gnd PWL(0n 0 25n 0 26n 1.8 75n 1.8 76n 0 100n 0)
* NOR gate
* PMOS pull-up (series)
Mp1 nor_out a mid_pu vdd pmos L=1u W=2u
Mp2 mid_pu b vdd vdd pmos L=1u W=2u
* NMOS pull-down (parallel)
Mn1 nor_out a gnd gnd nmos L=1u W=1u
Mn2 nor_out b gnd gnd nmos L=1u W=1u
* Inverter (to make OR from NOR)
Mp3 out nor_out vdd vdd pmos L=1u W=2u
Mn3 out nor_out gnd gnd nmos L=1u W=1u
* Transistor models
.model nmos nmos (vth0=0.4)
.model pmos pmos (vth0=-0.4)
* Simulation control
.control
tran 0.1n 100n
plot v(a) v(b) v(out)
.endc
.end
Homework¶
2. Schmitt trigger analysis: Look up a CMOS Schmitt trigger schematic and identify which transistors set the upper vs lower threshold¶
In this 6-transistor CMOS Schmitt trigger: M4, M5 are PMOS (gate bubbles) in the pull-up path. M2, M1 are NMOS (no bubbles) in the pull-down path. M3 and M6 are the positive-feedback devices controlled by the output Vo (that’s what creates hysteresis).
Generated by ChatGPT. Prompt is “CMOS Schmitt trigger schematic, identify which transistors set the upper vs lower threshold”
-
Upper threshold(VT+) is mainly set by M3. Why? M3 is an NMOS feedback transistor whose gate is driven by Vo. When Vin (Vg) rises, the output Vo is initially HIGH. With Vo = HIGH, M3 turns ON, and it pulls the internal NMOS stack node (between M2 and M1) upward toward Vdd. That reduces M2, so the pull-down path becomes harder to turn on. Therefore the input must rise higher before Vo can switch LOW → upper threshold increases.
-
Lower threshold(VT-) is mainly set by M6. Why? M6 is a PMOS feedback transistor whose gate is also driven by Vo. When Vin (Vg) falls, the output Vo is initially LOW. With Vo = LOW, M6 turns ON, and it pulls the internal PMOS stack node (between M4 and M5) downward toward GND. That makes the pull-up path harder to turn on (the PMOS stack needs an even lower Vin to conduct strongly enough). So the input must fall lower before Vo switches HIGH → lower threshold decreases.
Homework¶
3. Optional: Build a simple circuit (LED + resistor + button) in TinkerCAD and observe current flow¶
I will do using CMOS later. Link to TinkerCAD Circuit
Class Note¶
1. Electrons & Wires Based on the behavior of electrons, material types are divided into Conductors(e.g. Copper, Gold, Aluminum), Insulators(e.g. Rubber, Glass, Plastic), and Semiconductors(e.g. Silicon, Germanium).
Electronics is invisiable, but water in pipes behaves the same way. Higher voltage (pressure) pushes more current (flow) through the same resistance (pipe).
| Symbol | Meaning | Unit | Water Analogy |
|---|---|---|---|
| V | Voltage | Volts (V) | Pressure |
| I | Current | Amps (A) | Flow rate |
| R | Resistance | Ohms (Ω) | Pipe narrowness |
Ohm’s Law: V = I × R
2. Passive Components Passive components don’t amplify signals — they just modify how current flows.
| Component | Symbol | What It Does | Water Analogy |
|---|---|---|---|
| Resistor | R | Slows down all electrons | Narrow pipe |
| Capacitor | C | Blocks slow signals, passes fast ones | Flexible membrane |
| Inductor | L | Blocks fast signals, passes slow ones | Heavy paddle wheel |
Every wire naturally has some resistance, capacitance, and inductance — even if you don’t add components!
3. Active Components: Transistors
A transistor is a variable resistor controlled by voltage. It can act as:
A switch (digital circuits) — ON or OFF
An amplifier (analog circuits) — small signal in, large signal out
Modern chips use CMOS technology (Complementary MOS), which combines two types of transistors:
| Type | Turns ON when | Connects to | Think of it as |
|---|---|---|---|
| NMOS | Gate = HIGH (1) | Ground (GND) | Normally open valve |
| PMOS | Gate = LOW (0) | Power (VDD) | Normally closed valve |
NMOS and PMOS are complementary!
- NMOS: Gate HIGH → ON (connects to GND) → LOW
- PMOS: Gate LOW → ON (connects to VDD) → HIGH
4. Binary Logic: 1s and 0s
In digital circuit, Voltage Levels Represent Logic.
| Logic Level | Voltage (typical) | Meaning | Voltage (standard) |
|---|---|---|---|
| HIGH (1) | Near VDD (power) | True, ON | 5V, 3.3V, 1.8V |
| LOW (0) | Near GND (ground) | False, OFF | 0V |
5. Logic Gates & Truth Tables
AND Gate: Output is 1 only if BOTH inputs are 1. “Both must agree”
OR Gate: Output is 1 if EITHER input is 1. “Anyone says yes”
NOT Gate (Inverter): Output is the opposite of input. “Flip it”
6. Building Gates with Transistors
PMOS in parallel = OR function for pull-up
PMOS in series = AND function for pull-up
NMOS in parallel = OR function for pull-down
NMOS in series = AND function for pull-down
An AND gate is actually a NAND gate(NOT-AND) + NOT gate (inverter).
Pull-up: PMOS in parallel (either input LOW → output HIGH)
Pull-down: NMOS in series (both inputs HIGH → output LOW)
Then we add an inverter to flip the output → AND gate
In CMOS Design, (1) Design NMOS network first. (2) Build PMOS as the dual network (e.g. Series AND ↔ Parallel OR)
7. Circuit Simulation with SPICE SPICE (Simulation Program with Integrated Circuit Emphasis) is software that simulates electronic circuits. You describe your circuit in a text file called a netlist, and SPICE calculates voltages and currents.
| Component | Syntax | Example |
|---|---|---|
| Resistor | Rx n1 n2 R=value | R1 in out R=1k |
| Capacitor | Cx n1 n2 C=value | C1 out gnd C=1p |
| Inductor | Lx n1 n2 L=value | L1 in out L=1n |
| MOSFET | Mx drain gate source bulk model L=len W=wid | M1 out in vdd vdd pmos L=1u W=2u |
n1, n2 are node names (connection points. e.g. in, out) k = kilo (1000), p = pico (10⁻¹²), n = nano (10⁻⁹), u = micro (10⁻⁶)
Simulation Commands
.control Start of simulation commands
plot v(a) v(b) v(out) Plot voltages at nodes a, b, and out
endc End of control section
end End of netlist
8. Clock Distribution Digital circuits use a clock signal to coordinate operations. All flip-flops must receive the clock at (nearly) the same time.
Clock skew: The difference in clock arrival time between two flip-flops. If skew is too large → timing failures → chip doesn’t work!
Approach: H-tree, Clock mesh, Clock buffers
9. Schimitt Trigger
Real-world signals aren’t perfect. A button press or sensor might produce (Bouncing)
A Schmitt trigger has two different thresholds: V_H (upper), V_L(lower)
This gap between thresholds is called hysteresis.
Once the output switches, small noise won’t cause it to switch back — the input must cross the other threshold.
Words¶
- Logic gate is a transistor-based circuit that implements a logical rule to convert binary inputs into a binary output. A gate interprets analog voltage levels(HIGH and LOW) as digital meaning(0 and 1), turning continuous electrical signals into reliable binary logic(rules like AND, OR, and NOT).
- NMOS is a type of transistor that turns ON when the gate voltage is high. It allows current to flow from drain to source when activated and is typically used to pull signals down to ground (0) in digital circuits.
- PMOS is the complementary transistor that turns ON when the gate voltage is low. It usually pulls signals up to VDD (1) in digital logic.
- CMOS stands for Complementary Metal-Oxide-Semiconductor. It combines one NMOS and one PMOS in a complementary way to build logic gates. Very low static power consumption and strong noise margins.
- Netlist is a text-based description of circuit components and their electrical connections used for simulation and chip design. “wiring list of circuit”
- A netlist is a text description of your circuit — what components you have and how they’re connected. Each line describes one component. It is used as input data to describe the configuration of a circuit in circuit simulation software such as SPICE (e.g., NgSPICE or LTspice). The designer writes the circuit they want to create as a “code” (script) called a netlist, and by loading it into the simulator, they can calculate the behavior of voltages and currents.