Session3 - Schematic Design¶

(Mon Feb 23)Super high level in a day! Appreciate on the advanced classmates’ pages & Cheers!

Homework¶

1. 1. Reuse and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter) and¶

STEP 1. Found the file and.sp at /foss/examples/analog_basics/

STEP2. Copy and paste the file and.sp to /foss/designs/ and Rename as nand.sp

STEP3. Change the code in nand.sp to make a 2-input NAND gate (e.g., remove the output inverter) using gedit.

1.2. Change the models to refer to the PDK models¶

STEP4. Change the models to refer to the PDK models. No idea. Just copy from another advanced student’s code.

* NAND gate ngspice Sky130A PDK 

* Include the Sky130 device models
.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt

* Power supply: 1.8V
Vdd vdd 0 1.8

* Inputs (same timing as your original PWL but in ns scale)
VinA A 0 PWL(0 0 2m 0 2.001m 1.8 3m 1.8 3.001m 0)
VinB B 0 PWL(0 0 1m 0 1.001m 1.8 2.5m 1.8 2.5001m 0)

* PMOS pull-up network (parallel)
Xp1 nOUT A vdd vdd sky130_fd_pr__pfet_01v8_hvt  L=0.150  W=0.99
Xp2 nOUT B vdd vdd sky130_fd_pr__pfet_01v8_hvt  L=0.150  W=0.99

* NMOS pull-down network (series)
Xn1 nOUT A npd 0 sky130_fd_pr__pfet_01v8  L=0.150  W=0.495
Xn2 npd  B 0   0 sky130_fd_pr__pfet_01v8  L=0.150  W=0.495

* Output load capacitor
Cload nOUT 0 10f

* Transient analysis
.tran 100p 4m

.control 
run
plot v(A) v(B) v(nOUT)

meas tran tpd_hl trig v(A) val=0.9 rise=1 targ v(nOUT) val=0.9 fall=1
meas tran tpd_lh trig v(B) val=0.9 rise=1 targ v(nOUT) val=0.9


.endc

.end

At this point, I read the classmate’s page and then, decided to set up DockerBut, it didn’t work.

Homework¶

2. 1. Simulate it in SPICE,¶

* Run ngspice code
/foss/designs > ngspice hello_nand.sp

* Stop ngspice
ngspice 1 -> quit
ngspice-45.2 done
/foss/designs >

2.2. Verify truth table (it will look something like the right table), and¶

NAND gate truth table

A	B	NAND
0	0	1
0	1	1
1	0	1
1	1	0

2.3. Measure propagation delays (low-to-high and high-to-low)¶

Propagation delay (tpd) is the time difference between an input transition and the corresponding output transition. Propagation delay is usually measured at 50% voltage level. It determines the speed of a circuit. Faster delay → faster chip.

No idea. I asked to AI: “Add the code. Measure Propagation delays.”

tpd_ were measured and graph shape was changed.

* NAND gate ngspice Sky130A PDK 

* Include the Sky130 device models
.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt

* Power supply: 1.8V
Vdd vdd 0 1.8

* Inputs
VinA A 0 PWL(0 0 2m 0 2.001m 1.8 3m 1.8 3.001m 0)
VinB B 0 PWL(0 0 1m 0 1.001m 1.8 2.5m 1.8 2.5001m 0)

* PMOS pull-up network (parallel)
Xp1 nOUT A vdd vdd sky130_fd_pr__pfet_01v8_hvt L=0.150 W=0.99
Xp2 nOUT B vdd vdd sky130_fd_pr__pfet_01v8_hvt L=0.150 W=0.99

* NMOS pull-down network (series)
Xn1 nOUT A npd 0 sky130_fd_pr__nfet_01v8 L=0.150 W=0.495
Xn2 npd  B 0   0 sky130_fd_pr__nfet_01v8 L=0.150 W=0.495

* Output load capacitor
Cload nOUT 0 10f

* Transient analysis
.tran 100p 4m

.control 
run

* Plot signals
plot v(A) v(B) v(nOUT)

* ----------------------------
* Propagation delay measurement
* ----------------------------

* A input switching
meas tran tpd_hl_A TRIG v(A) VAL=0.9 RISE=1 TARG v(nOUT) VAL=0.9 FALL=1
meas tran tpd_lh_A TRIG v(A) VAL=0.9 FALL=1 TARG v(nOUT) VAL=0.9 RISE=1

* B input switching
meas tran tpd_hl_B TRIG v(B) VAL=0.9 RISE=1 TARG v(nOUT) VAL=0.9 FALL=1
meas tran tpd_lh_B TRIG v(B) VAL=0.9 FALL=1 TARG v(nOUT) VAL=0.9 RISE=1

* Print results
print tpd_hl_A tpd_lh_A tpd_hl_B tpd_lh_B

.endc

.end

I was consulted the code from the advanced classmate. It works and Thank you!

* NAND gate ngspice Sky130A PDK 
* Include the Sky130 device models
.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt
* Power supply: 1.8V
Vdd vdd 0 1.8

* PMOS pull-up network (parallel)
Xp1 nOUT A vdd vdd sky130_fd_pr__pfet_01v8_hvt  L=0.150  W=0.99
Xp2 nOUT B vdd vdd sky130_fd_pr__pfet_01v8_hvt  L=0.150  W=0.99

* NMOS pull-down network (series) ***// pfet to nfet
Xn1 nOUT A npd 0 sky130_fd_pr__nfet_01v8  L=0.150  W=0.495
Xn2 npd  B 0   0 sky130_fd_pr__nfet_01v8  L=0.150  W=0.495

* Inputs (same timing as your original PWL but in ns scale) **// moved below mosfet
Vin1 A 0 PWL(0 0 2m 0 2.001m 1.8 3m 1.8 3.001m 0)
Vin2 B 0 PWL(0 0 1m 0 1.001m 1.8 2.5m 1.8 2.5001m 0)
* Output load capacitor
Cload nOUT 0 10f

.control 
* Transient analysis **// changed to 10n and moved in control and removed dot in tran
tran 10n 4m uic
**run** commented out
plot v(A) v(B) v(nOUT)

**// old to compair
*meas tran tpd_hl trig v(A) val=0.9 rise=1 targ v(nOUT) val=0.9 fall=1
*meas tran tpd_lh trig v(B) val=0.9 rise=1 targ v(nOUT) val=0.9 

**// new added rise=1 in the end and change rise=1 to fall=1
meas tran tpd_hl trig v(A) val=0.9 rise=1 targ v(nOUT) val=0.9 fall=1
meas tran tpd_lh trig v(B) val=0.9 rise=1 targ v(nOUT) val=0.9 rise=1  

.endc
.end

Homework¶

3. Write an initial analog block that you can use in your chip project (e.g., an adder, counter, etc.)¶

Here’s a good starting point: https://analoghub.ie/category/verilogModels/article/counter

Without any idea, I asked to ChatGPT - my Internet Robot friend Your assignment asks you to write an initial block (behavioral model) for a circuit you might use in a chip project, such as a counter, adder, comparator, etc. A binary counter is a good starting point because it is simple and widely used in digital and mixed-signal designs. A counter increments its stored value on each clock transition and outputs the current count in binary form.

Initial Analog Block – Binary Counter (Verilog-A)

`include "constants.vams"
`include "disciplines.vams"

module counter (clk, out);

input clk;
output [3:0] out;          // 4-bit counter output
electrical clk;
electrical [3:0] out;

parameter real vdd = 1.8;
parameter real vss = 0.0;
parameter real vth = 0.9;  // clock threshold

integer count;

analog begin

    @(initial_step) begin
        count = 0;
    end

    // Detect rising clock edge
    @(cross(V(clk) - vth, +1)) begin
        count = count + 1;

        if (count > 15)
            count = 0;
    end

    // Output bits
    V(out[0]) <+ transition(((count>>0)&1)?vdd:vss, 1n, 1n);
    V(out[1]) <+ transition(((count>>1)&1)?vdd:vss, 1n, 1n);
    V(out[2]) <+ transition(((count>>2)&1)?vdd:vss, 1n, 1n);
    V(out[3]) <+ transition(((count>>3)&1)?vdd:vss, 1n, 1n);

end

endmodule

Class Note¶

Schematic capture is the first step in circuit design
SPICE simulates circuit behavior with detailed models
Analysis types: DC, AC, Transient, Operating Point
PDK libraries provide calibrated device models
Corner simulation ensures robustness across process variation

Language	Purpose
SPICE	Transistor-level circuit simulation
Verilog	Digital circuit design
Verilog-A	Analog circuit modeling
Verilog-AMS	Mixed-signal modeling (analog + digital)

Schematic Capture Basics - A schematic is a graphical representation of a circuit. - Schematic Capture Tools: Xschem, KiCad, Cadence Virtuoso

SPICE Simulation SPICE (Simulation Program with Integrated Circuit Emphasis) is the industry standard for analog circuit simulation.

SPICE Netlist Format

* Inverter circuit
.include "sky130.lib"

* Power supply
Vdd vdd gnd 1.8

* Input signal (rise/fall times realistic for 130nm)
Vin in gnd PULSE(0 1.8 0 100p 100p 1n 2n)

* PMOS: drain gate source body
Mp out in vdd vdd sky130_fd_pr__pfet_01v8 W=1u L=150n

* NMOS: drain gate source body
Mn out in gnd gnd sky130_fd_pr__nfet_01v8 W=0.5u L=150n

* Simulation commands
.tran 10p 10n
.end

Verilog-A Example

// Ideal voltage-controlled switch
module vcswitch(p, n, ctrl);
    inout p, n;
    input ctrl;
    electrical p, n, ctrl;

    parameter real ron = 1;      // On resistance
    parameter real roff = 1e9;   // Off resistance
    parameter real vth = 0.5;    // Threshold

    analog begin
        if (V(ctrl) > vth)
            I(p, n) <+ V(p, n) / ron;
        else
            I(p, n) <+ V(p, n) / roff;
    end
endmodule