Session4 - Layout & Fabrication¶
(Thur Feb 26) I’m doing documentation using AI. I’m not sure if it’s the right answer. I set the scope of my project within what I can currently handle, focusing on understanding the provided examples and making minor modifications. I am learning a lot through our process. I keep trying, and I feel grateful to myself for continuing.
Homework¶
1. Block diagram: Sketch your project’s architecture showing major modules and data flow¶
After reviewing the source code of the four examples provided from faculty, I decided to customize Morse beacon as my project. github examples
**HOW TO CUSTOMIZE: **¶
This time, I have generated code by Copilot in github to customize morse_beacon.v.
The AI prompt was this.
“Original Code is this. Add the code: the beep sound to play simultaneously to the Morse signal. A piezo buzzer (simple on/off), beep frequency 600Hz, beep stop between symbols, audio output as integrated into the existing code.”
Block Diagram for Color LED Buzzer Morse Beacon
Diagram tool: excalidraw
Diagram tool: mermaid diagram
Diagram tool: mermaid
| Module / Block | Main Signals | Role |
|---|---|---|
message memory |
message[char_idx] |
Stores the text to send |
get_morse() |
ch, morse_data |
Converts ASCII to Morse pattern |
| Morse FSM | morse_state, char_idx, symbol_idx, morse_timer |
Sequences symbols and gaps |
| Debounce | btn_color, btn_pressed |
Cleans button input |
| Color Controller | color_mode, on_color, off_color |
Chooses LED colors |
| Buzzer Generator | buzzer_counter, buzzer_tone |
Creates 600 Hz square wave |
| Buzzer Output Gate | leds_on |
Sounds buzzer only during dot/dash |
| WS2812 Driver | pixel_data, bit_idx, timer, data_out |
Sends timed serial LED data |
Homework¶
2.1. Explore a standard cell: Open the sky130 standard cell library in KLayout¶
In the container:
klayout /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
2.2. Find an inverter (sky130_fd_sc_hd__inv_1).¶
Tip: Use Edit → Find (Ctrl+F) to search for "inv_1"
2.3. Identify metal, poly, and diffusion layers.¶
- Refer from SkyWater SKY130 PDK’s documentation
- GDS table provides the meaning of ID number.
Show metal layer - metal 68
Show poly layer - poly 66
Show diffusion layer - diff 65
Homework¶
3. Connect the dots: Pick one block from your diagram. What standard cells might implement it?¶
(e.g., “counter” needs flip-flops, “tone selector” needs muxes) Generated by ChatGPT and then, read carefully
| Module | Standard Cell |
|---|---|
| Morse FSM | flip-flops, comparators, adders |
| Counters | flip-flops + adders |
| Buzzer PWM | counter + toggle flip-flops |
| WS2812 driver | state machine + registers |
| Color selector | muxes |
Class Note¶
========== Example: Your Pocket Synth project =====================
1. You write: always @(posedge clk) if (button_c) tone <= NOTE_C;
2. Yosys converts that to ~10 logic cells (flip-flops, muxes, comparators)
3. Each gate is made of transistors following the rules from Lecture 2
4. OpenROAD places those gates and routes wires following today's DRC rules
5. The fab builds it using the process we'll discuss at the end of this lecture
6. You get a chip that plays music!
Course Journey — how this all fits together
- Layout Tools & Schematic Connection — connecting to last lecture
Standard Cells: Pre-Verified Building Blocks In the digital flow (which you’ll use for your project), you don’t draw layout by hand. Instead, the PDK provides standard cells — pre-designed, pre-verified layout blocks for common logic gates. Each standard cell includes: - Layout (GDS) — DRC-clean physical geometry - Abstract (LEF) — Pin locations and blockages for the router - Timing model (Liberty/.lib) — Delay and power characteristics - Behavioral model (Verilog) — For simulation
- The Layout Process — including how chips are made
- Design Verification (DRC & LVS)
- Process Development Kits
- Tape Out & Layout Acceptance
- Fabrication Overview
- The Fabrication Process
- Chip Delivery & Packaging