Session6 - Synthesis & Physical Design¶

(Thur Mar 5) Super High Level…

Homework¶

1. Synthesize your design — review gate count¶

STEP 1. Prepare the files /foss/designs/hello_morse/ hello_morse.v, debounce.v

STEP 2. Run Yosys (Synthesis) yosys -p "read_verilog hello_morse.v debounce.v; synth -top hello_morse; stat" *This does: reads the Verilog files, sets hello_morse as the top module, synthesizes the design, prints resource statistics

STEP 3. Save a synthesized netlist yosys -p "read_verilog hello_morse.v debounce.v; synth -top hello_morse; write_verilog hello_morse_synth.v"

STEP 4. Review gate count yosys -p "read_verilog hello_morse.v debounce.v; synth -top hello_morse; stat"

Module	Total Cells
`debounce`	144
`hello_morse` (local only)	1421
Full design	1565

Gate Count Table

Cell Type	debounce	hello_morse (local)	Full Design (total)
`$_ANDNOT_`	38	516	554
`$_AND_`	2	25	27
`$_DFFE_PN0N_`	0	1	1
`$_DFFE_PN0P_`	1	30	31
`$_DFF_PN0_`	23	89	112
`$_DFF_PN1_`	0	2	2
`$_MUX_`	0	70	70
`$_NAND_`	11	85	96
`$_NOR_`	2	57	59
`$_NOT_`	1	21	22
`$_ORNOT_`	9	48	57
`$_OR_`	37	385	422
`$_XNOR_`	1	26	27
`$_XOR_`	19	66	85
Total Cells	144	1421	1565

2. check for unintended latches¶

yosys -p "read_verilog hello_morse.v debounce.v; proc" These are all safe truncation warnings from assigning 32-bit arithmetic results into smaller localparams. The clean fix is to make the widths explicit in the expression.

iverilog -g2012 -o hello_morese.vvp hello_morse.v hello_morse_tb.v debounce.v
vvp hello_morse.vvp
gtkwave hello_morse_tb.vcd

3. Run place and route flow (OpenROAD)¶

hello_morse.v debounce.v ↓ yosys synth.ys ↓ hello_morse_synth.v ↓ OpenROAD pnr.tcl ↓ hello_morse.def / hello_morse.gds

STEP 1. Generate gate-level netlist from Yosys.¶

1-1. Create a Yosys script ** touch synth.ys Output file: synth.ys (empty)

1-2. Write the Yosys script Output file: synth.ys

1-3. Run synthesis yosys synth.ys Output file: hello_morse_synth.v This file is used by OpenROAD for place-and-route.

STEP 2. Run place and route flow (OpenROAD)¶

2-1. Create the filetouch pnr.tcl Output file: pnr.tcl (empty)

1-2. Write the OpenRoad script Output file: pnr.tcl

2-2. Run openroad pnr.tcl Output file: hello_morse_pnr.v, hello_morse.def

4. Analyze timing reports — identify and fix any violations¶

A minimal constraints file with just create_clock is often enough. The example file is at examples/lib/constraints.sdc. Static Timing Analysis

</> tcl
# Pre-CTS / pre-route electrical cleanup
repair_design

# Post-CTS timing repair
set_propagated_clock [all_clocks]
repair_timing -setup
repair_timing -hold

Make a new file called constraints.sdc Put this inside: create_clock -name clk -period 20 [get_ports clk]
Replace your pnr.tcl with this

##############################################################################
# pnr.tcl — Standalone OpenROAD flow for hello_morse
##############################################################################

set DESIGN_NAME hello_morse

set pdk_root /foss/pdks/ciel/sky130/versions/54435919abffb937387ec956209f9cf5fd2dfbee/sky130A
set lib_path  $pdk_root/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
set tech_lef  $pdk_root/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
set cell_lef  $pdk_root/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
set sdc_file  constraints.sdc

read_lef $tech_lef
read_lef $cell_lef
read_liberty $lib_path

read_verilog hello_morse_synth.v
link_design $DESIGN_NAME

read_sdc $sdc_file

initialize_floorplan \
    -site unithd \
    -die_area "0 0 200 200" \
    -core_area "20 20 180 180"

make_tracks

place_pins \
    -hor_layers met3 \
    -ver_layers met2 \
    -corner_avoidance 5 \
    -min_distance 2 \
    -min_distance_in_tracks

global_placement
detailed_placement

# This part fixes your error
set_wire_rc -signal -layer met1
set_wire_rc -clock  -layer met3
estimate_parasitics -placement

repair_design

report_worst_slack -max
report_worst_slack -min

global_route

write_def hello_morse.def
write_verilog hello_morse_pnr.v

Do not use these lines yet Remove these for now: Right now they are causing confusion.

set_propagated_clock [all_clocks]
repair_timing -setup
repair_timing -hold

After you run it Show me the output of:

report_worst_slack -max
report_worst_slack -min

AI said “Good news: there is no timing violation right now.”

Finish routing in OpenROAD your script should end like this:

global_route
detailed_route

write_def hello_morse_final.def
write_verilog hello_morse_pnr.v

5. Generate GDS and review layout in KLayout¶

STEP 1. Finish routing successfully Before detailed_route, add tie cells:

insert_tiecells sky130_fd_sc_hd__conb_1/LO
insert_tiecells sky130_fd_sc_hd__conb_1/HI

Then use:

global_route
detailed_route
write_def hello_morse_final.def

STEP 2. Open that DEF in KLayout with the SKY130 tech/LEF files

I stuck here!¶

STEP 3. Save/export as GDS hello_morse.gds

** At this point, I refered from another advanced students about Makefile
My flow is:
Verilog
↓
Yosys synthesis
↓
OpenROAD pnr.tcl
↓
DEF
↓
KLayout → GDS: The Makefile flow automates all of this.

** I decided to apply Makefiles, and it needs the specific project directory.

Work in Progress¶

Class Note¶

1. What is Synthesis?¶

Synthesis converts RTL code into a netlist of logic gates.] Verilog RTL → [Synthesis] → Gate Netlist → [Place & Route] → GDS

2. Logic Synthesis with Yosys¶

Basic Yosys Commands ```# Read Verilog read_verilog my_design.v

Elaborate hierarchy¶

hierarchy -check -top my_design

Synthesize to generic gates¶

synth -top my_design

Map to Sky130 cells¶

dfflibmap -liberty sky130_fd_sc_hd__tt_025C_1v80.lib abc -liberty sky130_fd_sc_hd__tt_025C_1v80.lib

Clean up¶

clean

Write output¶

write_verilog -noattr synth.v ```

3. Standard Cells¶

Pre-designed,pre-characterized logic gates. Fixed height and variable width.

4. Place and Route¶

P&R takes the synthesized netlist and creates physical lauout. OpenROAD flow for place & route

5. Clock Tree Synthesis¶

CTS builds a balanced distribution network for the clock signal. For our projects: A minimal constraints file with just create_clock is often enough. The example file is at examples/lib/constraints.sdc.

6. Static Timing Analysis¶

STA checks if your design meets timing without simulation.

7. Power Analysis¶

PA estimate battery life, heat dissipation, and avoid exceeding package limits.

What You’ll Submit¶

For tapeout, you typically need:

A GDS file (generated by the flow)
Documentation (README, pinout diagram)
[The Tiny Tapeout GitHub template] handles most of this automatically - see tinytapeout.com for the submission guide.