Skip to content

Session7 - Packaging & Board Design

(Mon Mar 9)

Class Note

1. Why package a chip?

The silicon die is tiny and fragile, Packaging provides protection, concectivity, heat dissipation, handling.

2. Package Types

modern surface mount packages: SOIC, QFP, QFN(Quad Flat No-lead)

3. Wirebonding

Wirebonding conncects the die pads to the package leads using thin gold or aluminum wires. For your design, you need to specify: Which die pad connects to which package pin, Power (VDD) and Ground (GND) assignments, Any special requirements (short wires for high-speed signals). Tip: Keep power/ground pads on opposite sides of the die from signal pads to simplify routing and reduce noise coupling.

4. Evaluation Board Design

KiCad is a free, open-source PCB design tool. Workflow: Schematic(circuit connection) –> Footprint(physical package shape) –> Layout(Place components and route traces) –> Gerbers(manufacturing file) PCB fabs: JLCPCB, PCBWay, OSH Park

5. Power Integrity

Layout Tips: * Keep decoupling caps close - Place 100 nF within 5mm of VDD/GND pins * Short, fat traces for power - Minimize resistance and inductance * Ground plane - Use a solid copper pour for GND if possible * Separate analog and digital grounds - Join at one point near power input * Check current capacity - 10 mil (0.25mm) trace handles ~0.5A; our designs need much less

6. I/O Voltage Levels

Scenario Solution
1.8V chip ↔ 3.3V Arduino Level shifter IC or resistor divider for inputs
1.8V chip ↔ 5V Raspberry Pi Level shifter IC (bidirectional)
1.8V chip → 3.3V LED Direct connection OK (LED just needs current)
3.3V sensor → 1.8V chip Resistor divider (slow) or shifter (fast)

7. FPGA Prototyping

Filed Programmable Gate Array is like a breadboard for digital logic. Reprogrammable anytime, fast iteration raher than ASIC. If it works on the FPGA, it will probably work on silicon

# Synthesize for FPGA (iCE40 example)
yosys -p "synth_ice40 -top my_design -json my_design.json" my_design.v

# Place and route
nextpnr-ice40 --up5k --json my_design.json --pcf pins.pcf --asc my_design.asc

# Generate bitstream
icepack my_design.asc my_design.bin

# Program the FPGA
iceprog my_design.bin

8. Bring up and Testing

For Our Projects: * Fortune Teller - Press button, see output on serial terminal * Pocket Synth - Press keys, listen to speaker * Dice Roller - Press button, see 7-segment display * Morse Beacon - Power up, see LEDs flash Morse code

9. Debug Techniques

Debug Strategies * Divide and conquer: Isolate which block is failing, Test inputs and outputs of each block * Compare to simulation: Apply same inputs as testbench, Do outputs match? * Add observability: Route internal signals to spare pins, Add debug registers (if you planned ahead!)

Design for Debug (DFD) Plan ahead in your design: Spare I/O pins for probing internal signals, Bypass modes to isolate blocks, Status registers readable via serial

Homework

  1. Run final DRC/LVS on your design

  2. Document your chip: functionality, pin assignments, and interface details (e.g., timing parameters, frequencies, baud rates)

  3. Develop a verification test plan

  4. Morse Beacon - Power up, see LEDs flash Morse code

  5. Prepare your presentation for Thursday!