Session8 - Final Presentation

(Thur Mar 12) The head of Fab Future said to complete the project because it will be extended by one week. It’s hard, but it’s necessary, and I’m grateful to Faculty.

What you build: * Customize an example or design your own * Write/modify ~30-100 lines of Verilog * Take it through the full flow: simulate → lint → synthesize → P&R → GDS * Demo your chip at the end of week 4

1. Morse Beacon Concept

The human desire to connect with others across distance and time has driven the technological evolution and continues to inspire communication systems today.

The morse electrical communication is an early form of electronics communication. It represents information using short and long signals, similar to a simple 1-bit system that can be interpreted like binary 0 and 1. These signals are mapped to characters, forming the basis of digital communication. This idea eventually led to the rapid development of modern telecommunication.

I remember the low buzzer sound of a Morse telegraph. Even without knowing Morse code, the steady rhythm of short and long signals was easy to notice. Combining sound(beep) and visual(telegraph’s movement / LED) makes the signal even clearer to humane mind.

In this project, ASCII text such as “Here I am” is converted into Morse code ”.... . .-. . / .. / .- –“ and transmitted using both LED and a buzzer. The LED color can be changed using a button, increasing an interactive experience within morse beacon.

Museum of the American Railroad

2. Chip Design

Write Verilog → simulate → lint → synthesize → P&R → GDS

The terminal of my MacBook Air is still calculating hello_morse.def. Today is the deadline, so I’ll stop running here. Thank you to everyone who has ventured together for four weeks. Happy Microelectronics 2026!

3. Demo

In this project, I designed a Morse Beacon chip that converts ASCII text into Morse code and transmits the signals using an LED and a buzzer.

I wrote the Verilog logic and verified its functionality through simulation and linting.

The design was synthesized with Yosys and then processed through placement and routing using OpenROAD.

During the physical design stage, I resolved issues related to timing, RC settings, and tie cells.

The flow successfully generated a DEF layout, though the final GDS generation was not completed.