Session 4 > Fabrication Basics¶

Research¶

It was late and I was tired…so the class with Alex Wynn was a bit of a blur. I will have to review the video to understand more deeply all the content of the session. What stuck with me from the session was the description of nanoscale circuitry in stacked layers.

So while I wait for the class video to be uploaded, my classmate and friend Thorarinn posted this in our mattermost channel > 3D Printable Inverter Model

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A 3D Model we can print and get a tactile and intuitive understanding of nanoscale circuitry. I was sold. Press print, let’s go!!

Class Review¶

Analog > Layout > Design

Transistors > SPICE > Verilog

Digital design abstracts away the physics, but the physics is still there.

Alex gave us a roadmap of where we have been and where we are going (in this course). Up till now, we have been learning the fundamental knowledge (electrons, transistors, CMOS Logic gates) and tools needed to do what this course was meant to teach. From this point forward, we dive fully into the digital realm to progress towards a fabricatable (rudimentary) chip design.

SPICE is good up until up to about 1000 devices
Analog Flow vs Digital Flow
Verilog HDL code describes logic that exists as hardware gates and transistors on silicon (or on FPGA)

Layout Tools
- K-layout (used for what? vs XSchem?)

File Format
- GDS > most common, binary format
- Oasis > 10x more compact than GDS

Layout Procedure 1. Draw schematic > schematic capture: Xschem, LTspice 2. Convert to HDL Netlist 3. Run Simulations 4. View Waveforms

Open Source Analog ASIC design

LVS > Layout vs Schematic, the difference between schematic and actual physical devices. Schematic vs Layout Netlists!

Standard Cells > pre-designed, pre-verified layout blocks for common logic gates

Gotta admit, even after the second time through the lecture, I am still not certain as to what I am supposed to do and how to do it.

Design Rules

“DRC ensures that your layout meets the physical constraints of the fabrication process…because of lithography resolution limits, etching characteristics and reliability requirements.”

Example key Geometry Design Rules include:
- Minimum (metal pad) Width
- Minimum Spacing (between metal pads)
- Via (metal) Enclosure Width
- Metal Density (within a specific area)

Example Reliability Rules
- Antenna Rules > disperse charge on long wires with diodes or vias
- Electromigration Rules > minimum wire widths depending on expected current to avoid atoms migration

Layout Versus Schematic (LVS) Check
- extracts Netlist and compares it to the original physical geometry

Process Development Kit (PDK)
- all specifications needed for designing for a specific Fab process.
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Multilayered Metal
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Modern processors, in order to get more transistors in a smaller space, stacks metal layers 3-dimensionally.

Terminology¶

HDL > Hardware Description Language, hardware as code instead of drawn schematics

Yosys > is a framework for Verilog RTL, an open source synthesis tool that converts Verilog code into gate-level logic…a compiler for hardware (ChatGPT)

RTL > Register Transfer Level, a level of abstraction that describe how data moves between (flip-flop) registers and how combinational logic transforms that data. The Abstraction Heirarchy: Transistor Level (lowest, PMOS/NMOS) > Gate Level (after Yosys, NAND, NOR, Flip-Flops) > RTL (registers, cominational logic, clocked behavior, synthesizable) > Behavioral Level (high-level, “what should happen?”) (ChatGPT)

Combinational Logic > Logic where the output depends on only the current inputs. No memory. No clock. No flip-flops. No latches No previous state. Just pure logic. Has Propagation Delays, Rise/Fall Times, Gate Delay. Versus Sequential Logic (has memory). (ChatGPT) alt text

FPGA > Field Programmable Gate Array, a reprogrammable (using Hardware description language, Verilog HDL) integrated circuit

ASIC > Application Specific Integrated Circuit, not reprogrammable after initial programming, designed for specific tasks

Assignment Work¶

[ ] Block Diagram: > Sketch your project’s architecture (make a Flow Chart) showing major modules and data flow (e.g. Pocket Synth: button input > tone selector > oscillator > PWM output)

[ ] Explore a Standard Cell: Open sky130 standard cell library in Klayout and find an inverter (sky130_fd_sc_hd__inv_1). Identify metal, poly, and diffusion layers

klayout /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds

[ ] Connect the Dots: Pick one block from your diagram > what standard cells might implement it? (e.g. “counter” needs flip-flops, “tone selector” needs muxes)

My understanding of the 3 assignments:

Decide on a project and draw a flow diagram for it.
Poke around KLayout and learn how to navigate around it.
Choose a block from the flow diagram and choose a Standard Cell that might implement it.

The first one, seems hard. I will need time to think about a project. The third one depends on the first. So that leaves the second assignment.

Explore a Standard Cell in KLayout¶

Mission: > find an inverter “sky130_fd_sc_hd__inv_1”
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I followed the homework instructions (and hints) and the above was as far as I got. I thought to try something new and got the following:
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I think I managed to open the INV_1 file. Now to figure out how to find the Metal, Poly and Diffusion layers. On the right side, there are lots of names with the word ‘Metal’ in it. But one was highlighted, so I hid everything else alt text

and showed that one highlighted name and got this:
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Not sure what I am looking at, but happy to isolate something. I provided to unhide more and more things and discovered that the only layers that produced anything were the numbered layers at the bottom. So I turn showed them one by one.

64/20
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