Session 1: Introduction & Development Pipeline

Session 1 was both terrifying and thrilling at the same time. While much of what was discussed was new and confounding to me, I was surprised that I actually understood some percentage of the lecture. Looking forward to what comes next!

Assignment

• Install course toolchain (instructions provided) or set up VM/container
• Run hello world synthesis on a simple design
• Verify tools work end-to-end before Thursday

Assignment Work

Using Dockers

Not really sure what I was doing with dockers, I just followed the provided instructions. The big green button loomed, begging to be pressed > Start Container.

Pressed, a new set of options emerged.

Not knowing what I was doing, I chose Option 1 > **Open Browser VNC ** which launched this password request…

…and after entering the password, I arrived here

…and I did as instructed and right clicked on the screen, and arrived at a big list of options

Using Browser VNC

What next?? There were further instructions.

- Open your tool’s server in the browser, enter the VNC password.

- Once inside, you should see your server desktop.

- Right click on the desktop and select “Open Terminal” to access the command line.

- Type: cd /foss/examples Run simulations with: make sim-fortune or make sim-all

Running Simulations

Following the instructions, I arrived at the terminal screen and entered the suggested commands.

and got this.

Was it successful?? I ran it again with the other command (make sim-all) and got these screens.

Looks like a successful run. The last messaged stated “All simulations complete”.

Emboldened, I tried to see what files were in the directory and tried running some simulations with my own commands. Initially, they all failed…

…but then I figured out the syntax and got the pocket_synth simulation to run.

Failure to Generate Waveforms

Success Generating Waveforms

So with suggest from my friend Thorarinn’s documentation, I give waveform generation another try. Reading his documentation, it was not clear to me if he just moved the ‘tb’ file from inside the fortune_teller folder and changed the extension from ‘.v’ to ‘.vcd’…or did something else. Then it occurred to me to run ‘make sim-fortune’ command one more time, and I noticed a line that appears when the simulation is run that says ‘VCD info: dumpfile fortune_teller_tb.vcd opened for output’. This piqued my curiousity and when I listed the contents of the example folder again, there was a file called ‘fortune_teller_tb.vcd’ sitting there that was not there before.

So now when I run the command ‘gtkwave fortune_teller_tb.vcd’…the waveform user interface screen pops up!! Hooray!!

And then…I was stuck again. Thorarinn’s documentation mentioned something about using ‘Append’. I saw it at the bottom of the screen and clicked it…and nothing happened. Hmmmmm…

Then just by trying a bunch of random things, I clicked on ‘fortune_teller_tb’ in the ‘SST’ window, which showed a submenu called ‘dut’. Below that, in a window with column headings ‘Type’ and ‘Signals’ there were a bunch of listed items with one called ‘btn’ like was mentioned in Thorarinn’s documentation. At the risk of failure, I selected ‘btn’ and then clicked ‘Append’…and a waveform for btn appeared in the black window to the right!!! Hooray again!!

With the trick figured out, I just started appending all the signal options and got this cool but indeciperable signals graph. Success??!!

With a lot happening in the signal graph window, I discovered the ‘Zoom Best Fit’ hidden away in the ‘Time’ menu. Choosing that showed all the graphs in its full entirety.

I am gonna call this a win (self pat on back!). Hopefully this is what the instructors wanted us to do for homework.

With the fortune teller simulation waveform a success, I decided to see if I could replicate the success with another simulation > Pocket Synth. Essentially repeating the same procedure, I was able to generate waveforms for Pocket Synth as well. These images describes my process.

Run a “Hello World” Synthesis

I guess at some point I need to understand what a Synthesis is in the context of this exercise. Skipping it for now…

I opened the the markdown file called “Quickstart” and discovered a step-by-step set of instructions for doing our assignment for this week! Well, better than never I guess. Looks like I somehow made it through Step 5: Try All The Examples.

Moving on to Step 6: Look at the Code. The instructions tell us to type a command into the terminal to open the Fortune Teller code. I decided to open the Pocket Synth code instead.

This is what I got…

Typing ‘q’ to quit the view-only mode. I then entered the provide command to make it possible for me to edit the code. This time I stuck with the Fortune Teller code (as the next few steps works on that code).

…and got some scary looking warnings in the terminal

…but also successfully got the editable code window for the Fortune Teller code.

Moving on to Step 7: make it Yours I copied the Fortune Teller code to the foss/designs folder and edited the code.

I edited the code in the ROM section as suggested, changing from ‘Yes Definitely!’ to ‘Heck Yeah!!!!!!’.

And from ‘Outlook not good’ to ‘Yikes!! Not Good!’.

Time to test the changes!

Research

Terminology

• Synthesis >
• Simulation >
• Verify >

Understanding Verilog

I watched a few YouTube videos to understand what Verilog was. These were the best I encountered.

• An Introduction to Verilog
• Verilog Intro
• Verilog Basics

Why write a Verilog hardward description?

• The written description specifies all circuit components, how they are connected together and their input and output ports
• Program simulations can be run on the hardware description to virtually test its functionality…before making it into its final physical form in a chip

From the first video (the images following were screenshot from the video), I understood the following about Verilog.

• It is NOT a programming language…it is a Hardware Description Language (HDL)
• HDLs are is a text-based description of how different hardware modules of a digital circuit are connected to one another

• Modules are individual hardware components such as AND, OR, NOT gates…and they are connected to one another with wires
• A group of connected individual modules can also be defined as a module
• A group of connected modules will have points where they can connect ‘to the outside world’ called Ports…each with a unique identifying name (a letter designation like o, x, y)
• A written Verilog always begins with the word ‘module’ (plus a module name) and end with ‘endmodule’
• Built in Verilog modules can be instantiated by:
  • specify the name of the module to be instantiated (ex: AND)
  • give the instantiated module a name
  • specify how the module is connected…specifying the output port first, then input ports

• the order of the various modules in a circuit in the hardware description…does not matter
• Wires are also given indentifying names
• A full Verilog hardware description would look something like this:

From the third video, I learned:

• The hardware description can be done in 3 ways > Gate Level, Dataflow Level, Behavior Level…ranging in abstraction from less to more

• Gate Level > describe the logic gates in a system…troublesome when there are too many gates
  

• Dataflow Level > describes how data moves through a circuit
  

• Behavioral Level > describes how a circuit behaves (not what it is)
  

• Combinational Logic vs Sequential Logic

• Combinational Logic > output a function of the inputs
• Sequential Logic > output a function of both inputs and internal ‘states’

Looking at the IIC OSIC Tools

There was a link option to view all installed tools in the container. I couldn’t resist and wow, what a list!!

And I learned that IIC-OSIC-TOOLs is defined as follows…

IIC-OSIC-TOOLS (Integrated Infrastructure for Collaborative Open Source IC Tools) is an all-in-one Docker/Podman container for open-source-based integrated circuit designs for analog and digital circuit flows.