Session 2: Analog Basics

*image “Human Computer” from 3 Body Problem

I have always appreciated the simplicity and power of binary switches, their ability to combine to something of great complexity. In the book ‘Three Body Problem’ a fictional ancient civilization utilized an army of soldiers, each with a flag that could show either black or white (a binary outcome), to represent a computer utilized to calculate the path of three suns.

Research

AND OR NOT?

Before approaching the technicalities of the second assignment, I felt compelled to build a good foundation about Logic Gates first.

Here are my notes (and images) from the video Understanding Logic Gates

• Transistors…act as switches…with binary possibilities
• 1 = ON
• 0 = OFF
• Each switch contains a single BIT of information…either 0 or 1
• Computers transforms INPUTS into OUTPUTS
• Logic Gates are the building blocks of computer circuits…accept Inputs and producing Outputs…according to logical rules
• NOT Gate > inverts the Input value and Outputs it…0 becomes 1 and conversely 1 becomes 0

• AND Gate > receives 2 Inputs and Outputs a single value, 0 when the Input values are dissimilar or both zeros, and 1 when the Input values are both ones

• OR Gate > receives 2 Inputs and Outputs a single value, 0 when the Input values are zeroes, and 1 when the Input values are dissimilar or both ones

• When combined AND, OR, and NOT gates can create complex logical behaviors

• NAND Gate > is a combination of an AND and NOT gates, a logic gate that inverts the result of an AND gate

-NOR Gate > is a combination of an OR and NOT gates, a logic gate that inverts the result of an OR gate

Transfer-Resistor

The Trans-sistor is a critical component in a logic circuit. Producing binary outcome possibilities, it is fundamental to digital computing that relies binary notation.

Netlist

I looked at Verilog a bit in the homework for session 1. Netlisting (is this a word?) seems to be a very similar proposition…describing a hardware circuit using text.

Every component has a letter code designation:

R > Resistor C > Capacitor L > Inductor M > MOSFET (metal oxide semiconductor field effect transistor)

And there is a syntax as to how to describe the position and wire connections for every component in the circuit. The class notes tells us that Resistors, Capacitors and Inductors are indicated with the following syntax:

Component code + number, input connection name, output connection name, component value

ex: R1 in out R=1k

For the MOSFET, the syntax is a bit more complicated:

Component code + number, drain name, gate name, source name, bulk name, mos type, length, width

ex: M1 out in vdd vdd pmos L=1u W=2u

So where should a Netlist text file be written? Looks like the answer is SPICE (Simulation Program with Integrated Circuit Emphasis) software.

Terminology:

PDK > Process Design Kit, a collection of files that describe the specific fabrication process including device models, design rules, and libraries, allowing the simulation of circuits that match a real-world manufacturing process (ChatGPT)

Schmitt Trigger

“A logic INPUT type that provides hysteresis (2 different threshold levels for RISING and FALLING edges (of an electrical signal))” according to How to Mechatronics > Transistor Schmitt Trigger. Its common function is for cleaning noisy electrical signals, by setting specific voltage thresholds to generate a full HIGH or LOW voltage output, creating a clean Square Wave.

According to All About Electronics > Schmitt Trigger Explained:

Upper Threshold Voltage > triggers LOW to HIGH
Lower Threshold Voltage > triggers HIGH to LOW

Listening to How to Mechatronic’s description left me confused about how electrical flow was actually occurring in the circuit. So I decided to use the Falstad app to build the circuit and visualize the electrical flow as the circuit switches cleanly from LOW to HIGH.

Assignment Work

1. Change an AND gate Netlist…into an OR gate Netlist

(insert AND OR comparison image)

Comparing the circuit diagrams for the AND gate and the OR gate side-by-side, it becomes clear that they share many similarities…with the only difference being the way the 2 transistors are connected between Voltage supply and output and ground. In the AND gate circuit, the 2 transistors are connected in SERIES. In the OR gate circuit, however, the two transistors connected in PARALLEL to Voltage supply and to output and ground.

Our assignment tasks us to change an AND gate text description, the Netlist, to become an OR gate.

Based on the diagram provided in class…

…the circuit is a different circuit than the simple BJT transistor circuit that I studied from the YouTube video. The Netlist example utilizes CMOS transistors and is much more complex that the 2 transistor BJT example. The Netlist seems to show 6 CMOS transistors in pairs.

The AND gate Netlist code was provided by our instructors and looks like this…

* AND Gate using CMOS

* Power supply
Vdd vdd gnd 1.8

* Input signals (PWL)
Va a gnd PWL(0n 0 10n 0 11n 1.8 50n 1.8 51n 0 100n 0)
Vb b gnd PWL(0n 0 25n 0 26n 1.8 75n 1.8 76n 0 100n 0)

* NAND gate
* PMOS pull-up (parallel)
Mp1 nand_out a vdd vdd pmos L=1u W=2u
Mp2 nand_out b vdd vdd pmos L=1u W=2u

* NMOS pull-down (series)
Mn1 nand_out a mid gnd nmos L=1u W=1u
Mn2 mid b gnd gnd nmos L=1u W=1u

* Inverter (to make AND from NAND)
Mp3 out nand_out vdd vdd pmos L=1u W=2u
Mn3 out nand_out gnd gnd nmos L=1u W=1u

* Transistor models
.model nmos nmos (vth0=0.4)
.model pmos pmos (vth0=-0.4)

* Simulation control
.control
tran 0.1n 100n
plot v(a) v(b) v(out)
.endc

.end

Breaking down the Netlist code:

This specifies the power sourced named ‘Vdd’ with voltage set at 1.8V, between ‘vdd’ and ‘gnd’ connection points.

* Power supply
Vdd vdd gnd 1.8

These 2 lines defines the 2 INPUTs named ‘Va’ and ‘Vb’. Va is connected between ‘a’ and ‘gnd’ and a Piecewise Linear (PWL) signal ON/OFF profile showing OFF until 11 nanoseconds, ON (1.8V) between 11 and 50 nanoseconds, then OFF from 51 nanoseconds onwards. Vb is connected between ‘b’ and ‘gnd’ with its own PWL signal profile.

* Input signals (PWL)
Va a gnd PWL(0n 0 10n 0 11n 1.8 50n 1.8 51n 0 100n 0)
Vb b gnd PWL(0n 0 25n 0 26n 1.8 75n 1.8 76n 0 100n 0)

The next few lines defines the CMOS transistors making up the NAND (Not AND) gate. A pair of ‘pmos’ transistors connected in parallel named ‘Mp1’ and ‘Mp2’. A pair of ‘nmos’ transistors connected in series named ‘Mn1’ and ‘Mn2’. From the class notes, the 4 connection parameters following the name are the Drain, Gate, Source, and Substrate. The last 2 parameters ‘L’ and ‘W’ specifies the length and width of the transistor channels. The ‘length being the distance between the source and drain’ and the ‘width how wide the channel is affecting its current drive capability’ (ChatGPT)

* NAND gate
* PMOS pull-up (parallel)
Mp1 nand_out a vdd vdd pmos L=1u W=2u
Mp2 nand_out b vdd vdd pmos L=1u W=2u

* NMOS pull-down (series)
Mn1 nand_out a mid gnd nmos L=1u W=1u
Mn2 mid b gnd gnd nmos L=1u W=1u

Then 2 more lines describing 2 more CMOS transistors, one pmos and one nmos that make up a NOT gate.

* Inverter (to make AND from NAND)
Mp3 out nand_out vdd vdd pmos L=1u W=2u
Mn3 out nand_out gnd gnd nmos L=1u W=1u

“For NGSPICE to run a simulation, device models must be specified to dictate their behavior. The next 2 lines specify the NGSPICE nmos and pmos models to utilized in the simulation. The 3 parameters specifies the Model Name, Device Type, Threshold voltage (when it switches between HIGH and LOW). Extra note that PMOS devices have negative threshold voltage.” (ChatGPT)

* Transistor models
.model nmos nmos (vth0=0.4)
.model pmos pmos (vth0=-0.4)

In the last section of code the simulation is run with ‘.control’ and ‘.endc’ commands starting and ending the simulation. The ‘tran’ command defines the time duration of the simulation, from 0.1 nanoseconds to 100 nanoseconds in this case. Lastly, with the ‘plot’ command, 3 voltage plots are specified for 3 node points, point ‘a’, point ‘b’ and the ‘out’ node. Finally, ‘.end’ is used to close out the simulation program.

* Simulation control
.control
tran 0.1n 100n
plot v(a) v(b) v(out)
.endc

.end

Our homework instructions:

I copied the file ‘examples/analog_basics/and.sp’ into the designs folder and renamed it ‘designs/Analog_Basics/my_AND.sp’. In a terminal, I ran the command ‘ngspice my_AND.sp’ and this appeared.

Super excited that it seemed to work, but then I noticed that the third plot was missing…and there was an error indicated in the terminal. After some help from ChatGPT, it turns out that it is not permissible to name the output port as ‘and’ in lines 21 and 22 (because it is a reserved word for Ngspice). I renamed it as ‘out’ in those lines and also in line 35 (plot v(OUT)). I ran the Ngspice command again and…success.

Looking at the 3 plots together, it is clear that the OUT plot shows a HIGH signal only where both the A plot and B plot simultaneously show HIGH signals (boolean intersection).

So how to convert the AND netlist to an OR netlist?

I reviewed the class notes on CMOS Gate Structure and took note of the following:

• ‘Every CMOS logic gate has 2 parts’ > hence the many transistors in the simple AND gate

• When a PMOS is Pulled-UP, it outputs a HIGH signal

• When an NMOS is Pulled-DOWN, it outputs a LOW signal

…and then the Key Rules

• PMOS in parallel = OR function for pull-up
• PMOS in series = AND function for pull-up
• NMOS in parallel = OR function for pull-down
• NMOS in series = AND function for pull-down

This last bit probably contains the answer as the PMOS and NMOS transistors can generate AND or OR logic functions depending if they are connected in parallel or series in pull-up or pull-down configurations.

Looking at the diagram provided in class for the AND gate:

• The upper-left RED section has 2 PMOS connected in parallel in a pull-up network > so it is functioning as an OR gate with either receiving a LOW signal, the output would be HIGH
• The lower-left GREEN section has 2 NMOS connected in series in a pull-down network > so it is functioning as an AND gate with both receiving a HIGH signal, the output would be LOW

These first 2 pairs of transistors together make up a NAND gate.

• The right-most BLUE section has a PMOS and NMOS connected in series > so it is functioning as an Inverter or NOT gate and flipping the output signal from the NAND gate to its opposite, the AND gate

From the class notes, the Truth Table generated by this circuit is as follows:

a	b	Pmos1	Pmos 2	Nmos1	Nmos2	Output Path	NAND Out
0	0	ON	ON	OFF	OFF	VDD(pullup)	1
0	1	ON	OFF	OFF	ON	VDD(p1 ON)	1
1	0	OFF	ON	ON	OFF	VDD(p2 ON)	1
1	1	OFF	OFF	ON	ON	GND(pulldn)	0

PMOS and NMOS generate the opposite output to the same input. When the INPUT is 1, NMOS will conduct while the PMOS will not conduct. And vice versa when the INPUT is 0.

The PMOS Pull-Up network will output HIGH, when A or B INPUTs are 0…when the OR gate connects to VDD. “The PMOS network is a HIGH side switch.” (ChatGPT)

The NMOS Pull-Down network will output LOW, when A and B INPUTs are both 1…when the AND gate connects to GND. “The NMOS network is a LOW side switch.” (ChatGPT)

To change an AND gate configuration to an OR gate configuration, I am thinking that we need to change the NAND configuration to an NOR configuration (leaving the inverter configuration alone). And since the NMOS network is always the LOW side switch (pull-down) and the PMOS network is always the HIGH side switch, their position in the overall configuration will not change. The PMOS network will remain at the top and the NMOS network will remain at the bottom.

To make a NAND a NOR, the PMOS and NMOS configurations will need to change. PMOS goes from parallel to series and NMOS from series to parallel. PMOS will function as an AND gate. NMOS will function as an OR gate. This NOR configuration produces the following Truth Table:

a	b	Pmos1	Pmos 2	Nmos1	Nmos2	Output Path	NOR Out
0	0	ON	ON	OFF	OFF	VDD(pullup)	1
0	1	ON	OFF	OFF	ON	GND(pulldn)	0
1	0	OFF	ON	ON	OFF	GND(pulldn)	0
1	1	OFF	OFF	ON	ON	GND(pulldn)	0

And the invertor flips these output results to become OR gate (opposite) results.

Great! Now to rewrite the netlist. The only code that needs to change are from these…

* NAND gate
* PMOS pull-up (parallel)
Mp1 nand_out a vdd vdd pmos L=1u W=2u
Mp2 nand_out b vdd vdd pmos L=1u W=2u

* NMOS pull-down (series)
Mn1 nand_out a mid gnd nmos L=1u W=1u
Mn2 mid b gnd gnd nmos L=1u W=1u

to these..

* NOR gate
* PMOS pull-up (series)
Mp1 mid a vdd vdd pmos L=1u W=2u
Mp2 nand_out b mid vdd pmos L=1u W=2u

* NMOS pull-down (parallel)
Mn1 nand_out a gnd gnd nmos L=1u W=1u
Mn2 nand_out b gnd gnd nmos L=1u W=1u

Let’s test in ngspice!

I copied the ‘my_AND.sp’ netlist file and renamed it ‘my_OR.sp’. I made changes to the code, saved it and ran the simultation. This was the outcome:

Yay, success!!

2. Schmitt Trigger Analysis

Identify the tansistors that affect the LOWER and UPPER VOLTAGE thresholds.

Given that M1, M2, M3, M4 are parts of Pull-UP and Pull-DN networks…the Threshold setting CMOS must be M5 and M6.

I built the circuit in Falstad to visualize the answer.

LTSpice

Downloaded LTSpice from here

3. Build and Test Logic Circuits