Session 3 > Schematic Design & Simulation

Research

Review: Analog Basics

• Active (electronic) Component > Transistor
• Transistor > NMOS and PMOS (Source, Gate, Drain pins)
• 4th Substrate pin serves as internal voltage reference for NMOS and PMOS
• Adjusting the voltage to the Gate pin controls how much electricity flows through the CMOS transistors
• CMOS > Complementary Metal Oxide Semiconductor logic family (NMOS & CMOS)
• NMOS > source pin arrow points out, ON when Gate = 1 and Substrate (tied to ground) = 0, OFF when Gate = 0 and Substrate (to GND) = 0
• PMOS > source pin arrow points in, ON when Gate = 0 and Substrate (tied to kpower source) = 1, OFF when Gate = 1 and Substrate (to VDD) = 1
• NMOS and PMOS function in reverse to one another
• 1s and 0s can be used to make Logic Gates
• Netlist notations between different simulator software (NgSPICE, LTSPICE, WRSPICE,etc.) will usually be the same for passive components, but may be different for active components
• Simulation Key Points > the Netlist should accurately describe the circuit and proper device models are selected

Schematic Capture

Understanding the diagram components:
- WIRES > connect devices
- Devices > passive or active electronic components
- Power/Voltage Reference > VDD typically a DC power source (no frequency, no hertz)
- Net Labels > names of wires

SPICE Simulation

• x > subcircuit instance (like a subroutine in programming) commonly used collection of connected components, saved as a separate file as a component
• sky130.lib > industry-like simulation model library
• Power Supply > 1.8V
• Input Signal > pulse type (0V to 1.8V, starting time 0, Rise-Time 100 picoseconds, Fall-Time 100 picoseconds, 1 nanosecond hold time, 2 nanosecond (repeating) period)
• PMOS > drain gate source body (output connect to drain, input to gate, source at VDD, substrate at VDD, sky130 PFET model, width = 1 micron, length = 150 nanometer)
• NMOS > drain gate source body (output connect to drain, input to gate, source at GND, substrate at GND, sky130 NFET model, width = 0.5 micron, length = 150 nanometer)

Analysis Types

- Output Capacitance > The capacitor at the Output generates the curvature in the red line graph (time is needed for the peak voltage to be reached)…some times it is not a passive device, but an artifact of the wire itself

The Netlist is the ‘natural language of the simulator’

• Propagation Delay > the time it takes for a signal to move from Input to Output. Each logic gate has its own Propagation Delay (PD) characteristic. Chains of Logic exhibit PD serially (Total Delay can be calculated with a formula)

‘The clock cannot be faster than the Total Delay’

• Long wires also contributes to PD

- Signals usually don’t have sharp Rising and Falling edges…they have a slope
- The Slope for Rising and Falling edges can be differenta, measured time taken to go from 10% to 90% rising or falling
- PMOS controls Rising edges - NMOS controls Falling edges

Transient Measurement Command
“Measures the propagation delay from input rising edge to output falling edge” (ChatGPT)

• meas > measurement command
• tran > transient simulation analysis
• tpd_hl > name of measurement variable > pull-down from High to Low
• TRIG v(in) > triggered by Input Voltage node
• VAL = 0.9 > triggered at 0.9V (50% of VDD) threshold (start timer)
• RISE=1 > rising edge, 1st crossing
• TARG v(out) > to target of Output Voltage
• VaL = 0.9 > triggered at 0.9V (stop timer)

• FALL=1 . falling edge, 1st crossing

• 0.9V because ‘Propagation Delay is usually measured at 50% level’ (ChatGPT)

Inverter Example: (ChatGPT)
- Input Voltage moves from 0V to 1.8V
- Output Voltage moves from 1.8V to 0V
- Propagation Delay Time = Time Output Trigger Voltage hits while falling - Time Input Trigger Voltage hits while rising
- Input Rising makes NMOS turn ON and Output is pulled LOW (output falls)

Run simulation using the terminal commands for batch or interactive modes > ngspice -b inverter.spice or ngspice inverter.spice

Interactive Mode NgSPICE Commands

Success will look like this…

• For HIGH-to-LOW or LOW-to-HIGH analysis > output shows where the triggers occurred and the Total Delay time (seconds)

Saving as CSV and Python Plotting Results:

Troubleshooting Errors:

Libraries and PDKs

Corner Cases

Accounting for manufacturing variability and worse-case scenarios (corners)

Running Corner Simulations

• add the above code to the top of the Netlist description code

Rule: Design must meet timing at SS corner (slow-slow) and not exceed power budget at FF corner (fast-fast)
- Ex: Clock may need to be lowered if speed at slow-slow corner is too slow

Behavioral Modeling

Behavioral descriptions vs Transistor descriptions.

“Behavioral modeling describes what the circuit does, not how it physically does it. Modeling the function not the devices.” (ChatGPT)

• Uses Verilog-A
• An abstraction of Transistor modeling
• Faster
• Sacrifice physical accuracy for speed and clarity

• 2 modes of operation in the Analog Block:
  1. When voltage above a threshold(vth), current has one specifically defined resistance (ron) (ex: low resistance, 1 ohm) > device ON
  2. When voltage is below a threshold (vth), current has another defined resistance (roff) (ex: higher resistance, 1k ohm) > device OFF

Assignment Work

Homework

[x] Reuse ‘and.sp’ netlist…, remove the Output Inverter and change the models to refer to the PDK models.

[ ] Simulate (the modified netlist) in SPICE, verify the Truth Table, and measure the Propagation Delays (Low to High, High to Low)

[ ] Write an initial Analog Block that you can us in your Chip Project (e.g. an Adder, Counter, etc.) start here

refer to instructional markdown document lll

HW1. Modify the AND Netlist with PDK Models

After copying the ‘and.sp’ file from the examples folder and saving it into the ‘designs/schemaCapture’ folder as ‘nand.sp’, modifying the file to use the PDK model ‘sky130’ was pretty straight forward.

• First I located the needed library and in the directory and wrote the path into the Netlist
  
  

• Adjusted the Power Supply voltage to **1.8V **

• Change the PWL Input pulse description to match that provided in example during class > PULSE(0 1.8 1 100p 100p 1n 2n)

• Replaced the PMOS and NMOS definitions with the sky130 component descriptions
  

• Then I removed the 2 code lines describing the ‘Inverter‘
  

• Add code to describe an Output Capacitor
  

• And finally…added the simulation control codes as per the class example
  

HW2. Simulate the Netlist in SPICE

Simulation Checklist
[x] Include the correct PDK library
[x] Set appropriate simulation time/frequency range
[x] Use realistic input waveforms
[x] Add load capacitance on outputs
[ ] Check multiple process corners
[ ] Verify power consumption

The first attempt at running ngspice with the revised NAND netlist…failed.

The error message seems to indicate that the pfet and nfet definitions cannot be found.

I opened the reference sky130 library just to see what the file contains…and I noticed descriptions of many corner cases that was discussed in class. I noticed in particular the ‘tt’ case at the top, which I remembered from the class represents the typical corner case. Then looking at the class example ngspice example code again…I noticed that there was a ‘tt’ outside of the path specifications…that I neglected to add. So I added this, saved it and ran it again.

And again…after what appears to be a lengthy processing time (about 60 seconds)…the same error.

In our class mattermost chat, other students also faced the same issue. Luckily, some of the students found the solution. The length and width definitions for the NMOS and PMOS transistors need to be defined in microns (u) (I had my lengths defined in nanometers (n)) for it to work.

Well, regardless of my applying the adjustments made by my student colleagues…I continue to see the same error again and again. So I went to ChatGPT for help. Here is what it concluded > the Netlist code is OK, the sky130 library I am pointing to is the wrong one…does not include the transistor models I need. Here is ChatGPT’s recommendation for a fix:

Hours later, trying to debug with ChatGPT…to no avail.

Ultimately, it was my colleague’s documentation that resulted in success.

The adjustments that lead to success were:

• Ensuring that the library path is correct and points to the ‘tt’ corner
• Adding ‘X’ in front of the PMOS and NMOS model description
• Adjusting the Propagation Delay measurement script

Description of the Plots
The graphs describe NAND behavior > Vout goes LOW at between 1-3ns and 14-15ns. Output is LOW only when both A and B inputs are HIGH.

HW3. Write an Analog Block

“An Analog Block is a section of a circuit that processes continuous signals, not digital 0s and 1s.” (ChatGPT)

What it does?
- Amplifies signals

• Filters signals
  

• Generates waveforms
  

• Regulates voltage
  

Analog vs Digital Block

“When you build CMOS gates in ngspice, it is Digital Abstraction, but physically they are still Analog Devices” (ChatGPT)

“Analog blocks deal with real-world signals. Digital blocks deal with logic decisions.” (ChatGPT)

Our instructor Jennifer recommended that we look at the Analog Hub website to see examples. This was the “COUNTER” example.

The Circuit

The Waveforms

The Verilog-A Code

// Verilog-A model for Binary Counter
// Source: AnalogHub.ie
// Author: A. Sidun
// Reference: A. Beckett

\`include "constants.vams"
\`include "disciplines.vams"
\`define bits 4

module counter (clk,en,out);
input clk, en;
output [\`bits-1 :0] out;
electrical clk, en;
electrical  [\`bits-1 :0] out;

parameter integer start_code = 0 from [0:(1<<\`bits)-1];   // Start code for the counter
parameter integer count_up = 1 from [0:1];         // Set 1 for increasing or 0 for decreasing
parameter integer step_size = 1;              // Step size for the counter
parameter real vth_clk = 0.5;               // Clock threshold
parameter real vtol = 0;                  // Signal tolerance on the clk
parameter real ttol = 0;                  // Time tolerance on the clk
parameter real vdd = 1.0;
parameter real vth = 1;
parameter real vss = 0;
parameter real t_delay = 30p;               // Delay time for the output waveform
parameter real t_edge = 30p;               // Rising/falling times of the output waveform
integer outval;                      // Internal counter 

analog begin
  @(initial_step("static","ac")) outval = start_code;
  @(cross(V(clk)-vth_clk,1,vtol,ttol)) begin
    if (V(en)<vth) outval=0.0;
    else outval = (outval +(+count_up- !count_up)*step_size)%(1<<\`bits);
  end
  generate j (\`bits-1 , 0) begin
    V(out[j]) <+ transition (!(!(outval &(1<,[object Object]

To understand how to proceed with Verilog-A, I watched this tutorial video. Notes as follows:

• Verilog-A is a subset of Verilog-AMS, it is a High-Level Hardware Description Language (HDL) specifically for Analog designs
• SPICE is good for transistor level analog circuit modeling, but difficult to model high-level system behaviors

References