Session 1: Introduction & Development Pipeline¶

Notes¶

This is the first time for me to learn the microelectronics. In the first leacture, it is introduced the history of microchips, ICs from Intel 4004, MOS6502, LR35902 (Game Boy CPU).... until Apple M1 (most recent microchip by Silicon).

The Chip or it could be said “Integrated Circuit” (IC) is a set of electronic circuit on a small… (very small !) flat piece of semiconductor material. Essentially important is Transister. In the class, the design hierarchy of transister to system are presented. In the class, deveopment pipeline also presented. In this course, we will focused to learn the basics of full chip development flow, that are consisted of:

Analog fundamentals: Transistor, SPICE (Simulation Program with Integrated Circuit Emphasis) simulation, device behavior
Digital design: Verilog, synthesis, place and route, timing analysis
Physical Design: Layout, DRC, LVS, tpeout

Taxnomy

Verilog is and hardware description language that are standarized by IEEE1364. It looks like C language. Extension is .v, and the result of simulation written by verilog are recorded into .vcd file (value change dump).

Assignment¶

Install the course toolchain (Docker container)
Run a “hello world” synthesis
Verify your tools work befor Thursday

Access to Microelectronics Class Toolchain¶

In this class, we use Virtual Remote Machine consisted by Docker container. The following is the procedure which I accedded to my remove machine.

Go to tool server of micro electronics, and click “Start Container”.

Click “Open Browser VNC” to access the desktop remotelly.

Enter the password for connecting

Then, we can see the desktop of the toochain machine.

Run Sample Verilog Code¶

Right click on the desktop, then click “Terminal”

Type the following command.

cd /foss/examples

Then, type the following command. Here, I will start the sim-fortune

make sim-fortune

I could see the following output, it means simulation is successfully finished.

run this command to view waveforms

gtkwave fortune_teller_tb.vcd

Finally, we can see the

Then, finally, I could start gtkwave for simulation.

Access via VNC client¶

In Mac OS, Screen Sharing App can be used for accessing to VNC Server.

First, select “Go” -> “Connect to Server …”

Enter the vnc server address with port. Don’t forget to add ‘vnc://’ before the server address.

Then, enter the password to access to the server.

Now, the desktop has come to see.

Run the following command to setup all simulation examples.

make sim-all

Then, it shows ” all simulation complete”

Gtkwave could also be started.

GTKWave for seeing the waveform¶

So, returning the GTKWave. This is the tool for seeing the simulated result of hardware behavior defined by Verilog code. In this case, I did “make sim-fortune” to generate .vcd file the recorded the waveform data of Verilog simulation.

To see each signals in the wavefor viewer, the following steps are needed.

Select the module that are recorded the signal (on top left pain)
Select the signal that I want to see. (on the bottm left pain)
Then, the signal would come to waveform viewer.

Added some signals, but still cannot see any waves… That is because the time series interval is 1ps (pico second)… too small. So, I pushed “Zoom Out” to see the waveform more wider range.

Looking back to the result of “make sim-fortune”…

/foss/examples > make sim-fortune
iverilog -Wall -g2012 -Ilib -o fortune_teller/fortune_teller.vvp fortune_teller/fortune_teller.v fortune_teller/fortune_teller_tb.v lib/debounce.v lib/uart_tx.v
vvp fortune_teller/fortune_teller.vvp
VCD info: dumpfile fortune_teller_tb.vcd opened for output.
Pressing button...
Cannot predict.

Pressing button again...
Yes definitely!

Test complete
fortune_teller/fortune_teller_tb.v:221: $finish called at 51055000000 (1ps)

Those are the simulation output. So, looks at the Verilog code of fortune_teller. That is “fortune_teller.v” file located in the “fortune_teller” folder.

So, open the fortune_teller.v file in any editer software. And see the insde the Verilog code. The first section wrote as follow:

// ============================================================================
// Fortune Teller - A Magic 8-Ball on a Chip
// ============================================================================
//
// HOW IT WORKS:
//   1. Press the button
//   2. Chip picks a random fortune from memory
//   3. Fortune appears on your computer's serial terminal
//
// WHAT YOU'LL LEARN:
//   - ROM (Read-Only Memory) - storing data in your chip
//   - LFSR (Linear Feedback Shift Register) - generating random numbers
//   - State machines - controlling the sequence of operations
//   - Using library modules - connecting pre-built components

It says this simulation code would do that if the button is pressed, the random message which are stored in ROM (Read-Only-Memory) would be picked up and printed out to the serial monitor.

Also, looking down to the code, I could find this section:

 // ========================================================================
    // Fortune ROM (Read-Only Memory)
    // ========================================================================
    // We store 8 different fortunes in memory. Each fortune can be up to
    // 20 characters long. Characters are stored as ASCII codes.
    //
    // ASCII codes: 'A'=0x41, 'a'=0x61, ' '=0x20, '.'=0x2E, '\n'=0x0A, etc.
    // 0x00 marks the end of a string (null terminator).
    //
    // Total memory: 8 fortunes x 20 bytes = 160 bytes

    reg [7:0] rom [0:159];  // 160 bytes of ROM

    // Initialize the ROM with our fortunes
    // (In a real chip, this would be hardcoded during manufacturing)
    initial begin
        // Fortune 0: "Yes definitely!\n"
        rom[0]  = 8'h59;  // 'Y'
        rom[1]  = 8'h65;  // 'e'
        rom[2]  = 8'h73;  // 's'
        rom[3]  = 8'h20;  // ' '
        rom[4]  = 8'h64;  // 'd'
        rom[5]  = 8'h65;  // 'e'
        rom[6]  = 8'h66;  // 'f'
        rom[7]  = 8'h69;  // 'i'
        rom[8]  = 8'h6E;  // 'n'
        rom[9]  = 8'h69;  // 'i'
        rom[10] = 8'h74;  // 't'
        rom[11] = 8'h65;  // 'e'
        rom[12] = 8'h6C;  // 'l'
        rom[13] = 8'h79;  // 'y'
        rom[14] = 8'h21;  // '!'
        rom[15] = 8'h0A;  // '\n' (newline)
        rom[16] = 8'h00;  // End of string
        rom[17] = 8'h00;
        rom[18] = 8'h00;
        rom[19] = 8'h00;

That is that section to define which characters are stored into which memory number. Those would come out on “current_char[7:0]” and “rom_addr[7:0]”. If the rom_addr point “00”, then current_char show “59”. “59” (in ASCII “Y”). If the rom_addr point “01”, the current_char come “65” (in ASCII “e”).

If zoom out, the correspondance of ROM and the character could be seen.

On the time pain, select the signal and right click. Then choose “Data Format” as “ASCII”.

Then, the characters could appear on the waveform.

Verilog “Hello, World”¶

Looking at the Makefile… I can found:

# Default shell
SHELL := /bin/bash

# Tools
IVERILOG := iverilog
VVP := vvp
VERILATOR := verilator
YOSYS := yosys

# Common options
IVERILOG_FLAGS := -Wall -g2012
VERILATOR_FLAGS := --lint-only -Wall

# Library path
LIB := lib

Also, here is the section for defining Simulation targets

# =============================================================================
# Simulation targets
# =============================================================================

.PHONY: sim-fortune sim-synth sim-dice sim-led sim-all

sim-fortune: fortune_teller/fortune_teller.vvp
    $(VVP) $<

sim-synth: pocket_synth/pocket_synth.vvp
    $(VVP) $<

sim-dice: dice_roller/dice_roller.vvp
    $(VVP) $<

sim-led: morse_beacon/morse_beacon.vvp
    $(VVP) $<

sim-all: sim-fortune sim-synth sim-dice sim-led
    @echo "All simulations complete."

And, the section defining compilation section are founded as:

# =============================================================================
# Compilation targets
# =============================================================================

fortune_teller/fortune_teller.vvp: fortune_teller/fortune_teller.v fortune_teller/fortune_teller_tb.v $(LIB)/debounce.v $(LIB)/uart_tx.v
    $(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^

pocket_synth/pocket_synth.vvp: pocket_synth/pocket_synth.v pocket_synth/pocket_synth_tb.v $(LIB)/debounce.v
    $(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^

dice_roller/dice_roller.vvp: dice_roller/dice_roller.v dice_roller/dice_roller_tb.v $(LIB)/debounce.v $(LIB)/uart_tx.v
    $(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^

morse_beacon/morse_beacon.vvp: morse_beacon/morse_beacon.v morse_beacon/morse_beacon_tb.v $(LIB)/debounce.v
    $(IVERILOG) $(IVERILOG_FLAGS) -I$(LIB) -o $@ $^

Then, also looking back to the result of “make sim-fortune”, and I could find the executed commands as follow:

/foss/examples > make sim-fortune
iverilog -Wall -g2012 -Ilib -o fortune_teller/fortune_teller.vvp fortune_teller/fortune_teller.v fortune_teller/fortune_teller_tb.v lib/debounce.v lib/uart_tx.v
vvp fortune_teller/fortune_teller.vvp

Verilog is similar with C/C++, it means that first is to complied and generate something like a binary code, afterthat simulation command is executed.

iverilog: Officially called “Icarus verilog”, it is open-souce verilog HDL (hardware Design Language) compiler and simulator. It generate the middle file for simulation.
vvp: Opensource Icarus Verilog vvp runtime engine. It run the middle file generated by iverilog command, then generate the result file of simulation (.vcd)

Noted at the class page that we should make our design file into “/foss/design” folder. So, I moved to there, then start gvim to write a “hello world” verilog code with reffering this website. This is my first verilog code.

gvim hello-world.v

The hello world code is here:

module tb;

    initial
        $display("Hello World !");

endmodule

Then, execute the following command:

iverilog -Wall -g2012 -Ilib -o hello_world.vvp  hello_world.v

Then, “hello_world.vvp” are generated.

And, run this command:

vvp hello_world.vvp

And, “Hello World!” has come!!!