Session 2: Analog Basics¶

In this session, we learned about the basics of analog cricuit. The key thing is the mechanism of the transistors.

Assgnment¶

Modify the AND gate netlist to create an OR gate instead
Schmitt trigger analysis: Look up a CMOS Schmitt trigger schematic and identify which transistors set the upper vs lower threshold
Optional: Build a simple circuit (LED + resistor + button) in TinkerCAD and observe current flow

AND Gate¶

AND Gate is consisted of NAND Gate and NOT gate as following:

And, the netlist is here (the sample in class page):

* AND Gate using CMOS

* Power supply
Vdd vdd gnd 1.8

* Input signals (PWL)
Va a gnd PWL(0n 0 10n 0 11n 1.8 50n 1.8 51n 0 100n 0)
Vb b gnd PWL(0n 0 25n 0 26n 1.8 75n 1.8 76n 0 100n 0)

* NAND gate
* PMOS pull-up (parallel)
Mp1 nand_out a vdd vdd pmos L=1u W=2u
Mp2 nand_out b vdd vdd pmos L=1u W=2u

* NMOS pull-down (series)
Mn1 nand_out a mid gnd nmos L=1u W=1u
Mn2 mid b gnd gnd nmos L=1u W=1u

* Inverter (to make AND from NAND)
Mp3 out nand_out vdd vdd pmos L=1u W=2u
Mn3 out nand_out gnd gnd nmos L=1u W=1u

* Transistor models
.model nmos nmos (vth0=0.4)
.model pmos pmos (vth0=-0.4)

* Simulation control
.control
tran 0.1n 100n
plot v(a) 
plot v(b) 
plot v(out)
.endc

.end

I saved this code in /foss/design folder as AND.sp

Then run ngspice command.

ngspice and.sp

The result is shown in the terminal as follow:

/foss/designs > ngspice and.sp
******
** ngspice-45.2 : Circuit level simulation program
** Compiled with KLU Direct Linear Solver
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Copyright 2001-2025, The ngspice team.
** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html
** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html
** Creation Date: Mon Feb 16 14:08:33 UTC 2026
******

Note: No compatibility mode selected!


Circuit: * and gate using cmos

Warning: Model issue on line 24 :
  .model nmos nmos (vth0=0.4) ...
unrecognized parameter (vth0) - ignored

Warning: Model issue on line 25 :
  .model pmos pmos (vth0=0.4) ...
unrecognized parameter (vth0) - ignored

Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Using SPARSE 1.3 as Direct Linear Solver

Initial Transient Solution
--------------------------

Node                                   Voltage
----                                   -------
vdd                                        1.8
a                                            0
b                                            0
nand_out                                   1.8
mid                                 -5.653e-07
out                                5.02778e-08
vb#branch                                    0
va#branch                                    0
vdd#branch                           -3.62e-12


No. of Data Rows : 1032
ngspice 1 ->

And the simulation result is generated with a plot of a graph.

Here, v(a) is defined as following in the AND.sp netlist.

It says input A define first 0 nano second to 10 nano second as 0V(LOW), next 11 nano second to 50 nano second as 1.8V(HIGH) finally 51 nano second until 100 nano second as 0V(LOW).

Va a gnd PWL(0n 0 10n 0 11n 1.8 50n 1.8 51n 0 100n 0)

The graph shows the voltage transition of input A as defined in the netlist.

Here, v(b) is defined as following in the netlist.

It says input B define first 0 nano second to 25 nano second as 0V(LOW), next 26 nano second to 76 nano second as 1.8V(HIGH), finally next 76 nano second until 100 nano second as 0V(LOW).

Vb b gnd PWL(0n 0 25n 0 26n 1.8 75n 1.8 76n 0 100n 0)

The graph shows input B as defined in the netlist.

So, this is AND logic, and the graph of v(out) is indicated that v(out) would be 1.8V (HIGH) between 25 nano second and 50 nano second, for both input A and B are turn into HIGH.

Assignment 1: OR Gate¶

OR Gate consists of NOR Gate and NOT Gate. And, NOR Gate consiste of PMOS serial and NMOS Parallel.

In case A=LOW, B=LOW, OUT would be LOW as following. Both PMOS are conencted and Both NMOS are disconnected.

In case A=LOW, B=HIGH, OUT would be HIGH as following. PMOS A is connected but PMOS B is disconnected, as a result, both PMOS are disconnected. On the other hand, NMOS A is disconnected and NMOS B is connected. Then, the out of NOR Gate would be 0V(LOW). In the NOT Gate, PMOS is LOW and connected to VDD, and NMOS is also LOW and NMOS is disconnected. As a result, OUT would be HIGH.

In case A=LOW, B=HIGH, OUT would also be HIGH as following. PMOS B is connected but PMOS A is disconnected, as a result, both PMOS are disconnected. On the other hand, NMOS A is connected and NMOS B is disconnected. Then, the OUT of NOR Gate would be 0V(LOW). In the NOT Gate, PMOS is LOW and NMOS is also LOW. Then, only PMOS is connected to VCC. As a result, OUT would be HIGH.

In case A=HIGH, B=HIGH, OUT would be HIGH as following. Both PMOS are disconencted, and both NMOS are connected. Then the OUT of NOR Gate would be LOW. In the NOT Gate, PMOS is LOW and NMOS is also LOW. Then, only PMOS is connected to VCC. As a result, OUT would be HIGH.

In the netlist, it would be revise the definition of PMOS and NMOS. In AND.sp, PMOS and NMOS are defined as follow.

* NAND gate
* PMOS pull-up (parallel)
Mp1 nand_out a vdd vdd pmos L=1u W=2u
Mp2 nand_out b vdd vdd pmos L=1u W=2u

* NMOS pull-down (series)
Mn1 nand_out a mid gnd nmos L=1u W=1u
Mn2 mid b gnd gnd nmos L=1u W=1u

We would revise this part with PMOS as serial and NMOS as parallel.

* NOR gate
* PMOS pull-up (series)
Mp1 nor_out a mid vdd pmos L=1u W=2u
Mp2 mid b vdd vdd pmos L=1u W=2u

* NMOS pull-down (parallel)
Mn1 nor_out a gnd gnd nmos L=1u W=1u
Mn2 nor_out b gnd gnd nmos L=1u W=1u

The whole netlist is as following.

* AND Gate using CMOS

* Power supply
Vdd vdd gnd 1.8

* Input signals (PWL)
Va a gnd PWL(0n 0 10n 0 11n 1.8 50n 1.8 51n 0 100n 0)
Vb b gnd PWL(0n 0 25n 0 26n 1.8 75n 1.8 76n 0 100n 0)

* NOR gate
* PMOS pull-up (series)
Mp1 mid a vdd vdd pmos L=1u W=2u
Mp2 nor_out b mid vdd pmos L=1u W=1u

* NMOS pull-down (parallel)
Mn1 nor_out a gnd gnd nmos L=1u W=2u
Mn2 nor_out b gnd gnd nmos L=1u W=2u

* Inverter (to make AND from NAND)
Mp3 out nor_out vdd vdd pmos L=1u W=2u
Mn3 out nor_out gnd gnd nmos L=1u W=1u

* Transistor models
.model nmos nmos (vth0=0.4)
.model pmos pmos (vth0=0.4)

* Simulation control
.control
tran 0.1n 100n
plot v(a)
plot v(b)
plot v(out)
*plot v(a) v(b) v(out)

.endc

.end

The result is here.

/foss/designs > ngspice or.sp 
******
** ngspice-45.2 : Circuit level simulation program
** Compiled with KLU Direct Linear Solver
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Copyright 2001-2025, The ngspice team.
** Please get your ngspice manual from https://ngspice.sourceforge.io/docs.html
** Please file your bug-reports at http://ngspice.sourceforge.net/bugrep.html
** Creation Date: Mon Feb 16 14:08:33 UTC 2026
******

Note: No compatibility mode selected!


Circuit: * and gate using cmos

Warning: Model issue on line 24 :
  .model nmos nmos (vth0=0.4) ...
unrecognized parameter (vth0) - ignored

Warning: Model issue on line 25 :
  .model pmos pmos (vth0=0.4) ...
unrecognized parameter (vth0) - ignored

Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Using SPARSE 1.3 as Direct Linear Solver

Initial Transient Solution
--------------------------

Node                                   Voltage
----                                   -------
vdd                                        1.8
a                                            0
b                                            0
nor_out                                    1.8
mid                                        1.8
out                                5.02778e-08
vb#branch                                    0
va#branch                                    0
vdd#branch                           -5.43e-12


No. of Data Rows : 1032
ngspice 1 ->

Assignment 2: Schmmit Trigger¶

Look up a CMOS Schmitt trigger schematic and identify which transistors set the upper vs lower threshold

I have still not understand it well, but here is the summary of the problem of usual analog input and the role of schmitt trigger.

Generally, analog/digita input is unstable, sometime it could see bouncing, noise,,, and so on.

The following simulation circuit, I developed at [falstad.com], have 1 PMOS and 1 NMOS that show simple switching. The left side input 0-5voltage and right side output LOW or HIGH. The graph of left bottom show the transisions of voltage in left-bottom line and right-bottom line. The graph show something like a unstable curve when the output turn into HIGH/LOW.

Then following simulation circuit is the one that is added one more PMOS and NMOS. But, the left-bottom graph show still unstable when the output turn into HIGH/LOW.

The following simulation circuit (which is shown in the class powerpoint slide) have more PMOS and NMOS added to right side. By adding these PMOS/NMOS, the voltage output became stable. Those Transistors (M3, M6) would be affected to voltage trhedsholds (to be stable).

Simulation by TinkerCAD¶

AND Gate

Here is the simulation of AND Gate on the TinkerCAD. First, the circuit doesn’t worked. And, I found out that I failed to understand how to connect NMOS. NMOS source should be connected to GND (Not to the Drain of PMOS). I made two slide switch to input HIGH/LOW to both PMOS and NMOS Gate.