Session 04: Layout & Fabrication¶
This week, we learn how to design my IC chip and how to fabricate it. It is very first time to learn about it. And this session’s contents are very annoy and difficult for me because this is the very first time to hear about it. Also, it feel difficult to learn some design tools for chip layout desin… Still struggle....
Assignment 1:¶
Block diagram: Sketch your project’s architecture showing major modules and data flow (e.g., Pocket Synth: button inputs → tone selector → oscillator → PWM output)
I will try to make 4-bit adder subractor. It is a digital logic circuit capable of performing both binary addition and subtraction within a single circuit.
Assignment 3:¶
Connect the dots: Pick one block from your diagram — what standard cells might implement it? (e.g., “counter” needs flip-flops, “tone selector” needs muxes)
It consists of four Full adders. Each Full adders consist of Two Half Adder and And Gate with control signal.
- Half Adder: is a logic circuit that adds two 1-bit binary numbers (X and Y) and outputs the sum (Z) and a carry (C). It calculates the sum (Z) using an XOR gate and the carry (C) using an AND gate.
- Full Adder: is a basic logic circuit that adds three 1-bit binary inputs (input A, input B, and the carry from the lower digit) and outputs two bits: the sum of those digits () and the carry to the higher digit (). Unlike a half adder, it can account for the carry from the lower digit, enabling addition of any number of digits by connecting multiple units.
Assignment 2;¶
Explore a standard cell: Open the sky130 standard cell library in KLayout and find an inverter (sky130_fd_sc_hd__inv_1). Identify metal, poly, and diffusion layers.
First, I run the klayout as following:
/foss/designs > klayout /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
Then, the klayout is start.
Select “sky130_fc_sc_hd__inv_1” on the left side “cells” window.
Then, right click and select “Show as new top”
Inverter Cells is shown:
The right window show the layers in the cell. We can see active layer by right click “Hide Empty Layers”.
However… the layer name displayed in the right-hand window was a meaningless string of numbers. I was get lost the way what should I do next....
So, I read how does other classmates could solve it....
According to Layer Specification in the Klayout Documentation, those numbers indicate a layer number and datatype. For example, 17/5 give layer 17, datatype 5.
SKY130 PDK reference have a layer table and it include GDS layer.datatype information.
| layer number / datatype | layer specification |
|---|---|
| 64/5 | (Text type) |
| 64/16 | (Text type) |
| 64/20 | N-well region |
| 64/59 | (Text and datatype) |
| 65/20 | Active (diffusion) area (type opposite of well/substrate underneath) |
| 66/20 | Polysilicon |
| 66/44 | Contact to local interconnect |
| 67/5 | (Text type) |
| 67/16 | (Text and data) |
| 67/44 | Contact from local interconnect to metal1 |
| 68/5 | (Text type) |
| 68/16 | (Text and data) |
| 68/20 | Metal1 |
| 78/44 | High-Vt LVPMOS implant |
| 81/4 | Standard cell identifier |
| 83/44 | (Text type) |
| 93/44 | N+ source/drain implant |
| 94/20 | P+ source/drain implant |
| 95/20 | Nitride poly cut (under licon1 areas) |
| 122/16 | (text type) |
Metal
Above information, Metal layer is 68/20. I activate this layer.
Poly
Above information, Poly layer is 66/20 (Polysilicon) and 95/20 (Nitride poly cut).
diffusion
Diffusion layer is critical semiconductor regions on a silicon substrate that serve as the source, drain, and substrate contact (tap) of a MOS transistor, formed by diffusing or ion-implanting impurities (such as boron or phosphorus). Those are layer 93/44 and 94/20.
The following is combined of each metal, poly and diffusion layer.
