Session 06: Synthesis & Physical Design¶
(I have bad headache in this class day… so I just following up with showing class video…)
In this session, we learn the process to make synthesis and physical design of my IC chip defined RTL and simulated by Verilog in the last session. This session is also hard to learn…
Homeworks¶
- Synthesize your design — review gate count and check for unintended latches
- Run place and route flow
- Analyze timing reports — identify and fix any violations
- Generate GDS and review layout in KLayout
Assignment 1: Synthesis the design¶
I used yosys for synthesize my IC design, wrote in last session.
First, type command ‘yosys’
(base) yosuke@ysk-M1Pro synthesis % yosys
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2026 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.63 (git sha1 70a11c6bf0e8dd669f56c7da3587f78b405138e2, clang++ 17.0.0 -fPIC -O3)
yosys>
Then, read verilogs which I wrote in the last session (alu_core.v and top_wrapper.v)
yosys> read_verilog alu_core.v top_wrapper.v
1. Executing Verilog-2005 frontend: alu_core.v
Parsing Verilog input from `alu_core.v' to AST representation.
Generating RTLIL representation for module `\alu_core'.
Successfully finished Verilog frontend.
2. Executing Verilog-2005 frontend: top_wrapper.v
Parsing Verilog input from `top_wrapper.v' to AST representation.
Generating RTLIL representation for module `\top_wrapper'.
Successfully finished Verilog frontend.
Next, elaborate hierarchy
yosys> hierarchy -check -top top_wrapper
3. Executing HIERARCHY pass (managing design hierarchy).
3.1. Analyzing design hierarchy..
Top module: \top_wrapper
Used module: \alu_core
3.2. Analyzing design hierarchy..
Top module: \top_wrapper
Used module: \alu_core
Removed 0 unused modules.
After that, synthsize to generic gates
yosys> synth -top top_wrapper
Then, I could see the process of synthesis. The important part is here:
4.25. Printing statistics.
=== top_wrapper ===
+----------Local Count, excluding submodules.
|
15 wires
36 wire bits
15 public wires
36 public wire bits
10 ports
19 port bits
12 cells
12 $_SDFFE_PP0P_
1 submodules
1 alu_core
=== alu_core ===
+----------Local Count, excluding submodules.
|
28 wires
41 wire bits
6 public wires
19 public wire bits
5 ports
14 port bits
27 cells
6 $_ANDNOT_
1 $_MUX_
1 $_NOR_
2 $_NOT_
2 $_ORNOT_
3 $_OR_
5 $_XNOR_
7 $_XOR_
=== design hierarchy ===
+----------Count including submodules.
|
39 top_wrapper
27 alu_core
+----------Count including submodules.
|
43 wires
77 wire bits
21 public wires
55 public wire bits
15 ports
33 port bits
- memories
- memory bits
- processes
39 cells
6 $_ANDNOT_
1 $_MUX_
1 $_NOR_
2 $_NOT_
2 $_ORNOT_
3 $_OR_
12 $_SDFFE_PP0P_
5 $_XNOR_
7 $_XOR_
1 submodules
1 alu_core
4.26. Executing CHECK pass (checking for obvious problems).
Checking module top_wrapper...
Checking module alu_core...
Found and reported 0 problems.
Then, map to Sky130 cells. First, I execute “dfflibmap” command.
yosys> dfflibmap -liberty /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
5. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
cell sky130_fd_sc_hd__dfxtp_1 (noninv, pins=3, area=20.02) is a direct match for cell type $_DFF_P_.
cell sky130_fd_sc_hd__dfrtn_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_NN0_.
cell sky130_fd_sc_hd__dfrtp_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_PN0_.
cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_.
cell sky130_fd_sc_hd__edfxtp_1 (noninv, pins=4, area=30.03) is a direct match for cell type $_DFFE_PP_.
cell sky130_fd_sc_hd__dfbbn_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_NNN_.
cell sky130_fd_sc_hd__dfbbp_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_PNN_.
final dff cell mappings:
unmapped dff cell: $_DFF_N_
\sky130_fd_sc_hd__dfxtp_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q));
\sky130_fd_sc_hd__dfrtn_1 _DFF_NN0_ (.CLK_N( C), .D( D), .Q( Q), .RESET_B( R));
unmapped dff cell: $_DFF_NN1_
unmapped dff cell: $_DFF_NP0_
unmapped dff cell: $_DFF_NP1_
\sky130_fd_sc_hd__dfrtp_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R));
\sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R));
unmapped dff cell: $_DFF_PP0_
unmapped dff cell: $_DFF_PP1_
unmapped dff cell: $_DFFE_NN_
unmapped dff cell: $_DFFE_NP_
unmapped dff cell: $_DFFE_PN_
\sky130_fd_sc_hd__edfxtp_1 _DFFE_PP_ (.CLK( C), .D( D), .DE( E), .Q( Q));
\sky130_fd_sc_hd__dfbbn_1 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_NNP_
unmapped dff cell: $_DFFSR_NPN_
unmapped dff cell: $_DFFSR_NPP_
\sky130_fd_sc_hd__dfbbp_1 _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S));
unmapped dff cell: $_DFFSR_PNP_
unmapped dff cell: $_DFFSR_PPN_
unmapped dff cell: $_DFFSR_PPP_
5.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
<suppressed ~24 debug messages>
Mapping DFF cells in module `\top_wrapper':
mapped 12 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_1 cells.
Mapping DFF cells in module `\alu_core':
After that, I execute “abc” command.
osys> abc -liberty /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
6. Executing ABC pass (technology mapping using ABC).
6.1. Extracting gate netlist of module `\top_wrapper' to `<abc-temp-dir>/input.blif'..
6.1.1. Executed ABC.
Extracted 24 gates and 53 wires to a netlist network with 28 inputs and 12 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lib -w /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
ABC: Parsing finished successfully. Parsing time = 0.07 sec
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__diode_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_0".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_8".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_8".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_bleeder_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__lpflow_inputisolatch_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" has 334 cells (94 skipped: 63 seq; 13 tri-state; 18 no func; 0 dont_use; 0 with 2 outputs; 0 with 3+ outputs). Time = 0.10 sec
ABC: Memory = 19.85 MB. Time = 0.10 sec
ABC: Warning: Detected 9 multi-output cells (for example, "sky130_fd_sc_hd__fa_1").
ABC: + strash
ABC: + &get -n
ABC: + &fraig -x
ABC: + &put
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + &get -n
ABC: + &dch -f
ABC: + &nf
ABC: + &put
ABC: + write_blif <abc-temp-dir>/output.blif
6.1.2. Re-integrating ABC results.
ABC RESULTS: sky130_fd_sc_hd__mux2i_1 cells: 12
ABC RESULTS: sky130_fd_sc_hd__nor2_1 cells: 12
ABC RESULTS: internal signals: 13
ABC RESULTS: input signals: 28
ABC RESULTS: output signals: 12
Removing temp directory.
6.2. Extracting gate netlist of module `\alu_core' to `<abc-temp-dir>/input.blif'..
6.2.1. Executed ABC.
Extracted 27 gates and 36 wires to a netlist network with 9 inputs and 5 outputs.
Running ABC script: <abc-temp-dir>/abc.script
ABC: ======== ABC command line "source <abc-temp-dir>/abc.script"
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lib -w /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
ABC: Parsing finished successfully. Parsing time = 0.07 sec
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__decap_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__diode_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__dlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__edfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_0".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvn_8".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_2".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_4".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__einvp_8".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_bleeder_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_12" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_3" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_6" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__lpflow_decapkapwr_8" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__lpflow_inputisolatch_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbn_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfbbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtn_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfrtp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfsbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfstp_4".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sdfxtp_4".
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_1" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_2" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "sky130_fd_sc_hd__sdlclkp_4" without logic function.
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxbp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_2".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__sedfxtp_4".
ABC: Library "sky130_fd_sc_hd__tt_025C_1v80" from "/Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" has 334 cells (94 skipped: 63 seq; 13 tri-state; 18 no func; 0 dont_use; 0 with 2 outputs; 0 with 3+ outputs). Time = 0.10 sec
ABC: Memory = 19.85 MB. Time = 0.10 sec
ABC: Warning: Detected 9 multi-output cells (for example, "sky130_fd_sc_hd__fa_1").
ABC: + strash
ABC: + &get -n
ABC: + &fraig -x
ABC: + &put
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + strash
ABC: + &get -n
ABC: + &dch -f
ABC: + &nf
ABC: + &put
ABC: + write_blif <abc-temp-dir>/output.blif
6.2.2. Re-integrating ABC results.
ABC RESULTS: sky130_fd_sc_hd__maj3_1 cells: 3
ABC RESULTS: sky130_fd_sc_hd__mux2_1 cells: 1
ABC RESULTS: sky130_fd_sc_hd__xnor2_1 cells: 6
ABC RESULTS: sky130_fd_sc_hd__xor2_1 cells: 4
ABC RESULTS: internal signals: 22
ABC RESULTS: input signals: 9
ABC RESULTS: output signals: 5
Removing temp directory.
Removing global temp directory.
Then, clean up.
yosys> clean
Removed 0 unused cells and 88 unused wires.
And, I could see the statistics of my synthesis
stat
And, the result is here:
7. Printing statistics.
=== top_wrapper ===
+----------Local Count, excluding submodules.
|
39 wires
60 wire bits
15 public wires
36 public wire bits
10 ports
19 port bits
36 cells
12 sky130_fd_sc_hd__dfxtp_1
12 sky130_fd_sc_hd__mux2i_1
12 sky130_fd_sc_hd__nor2_1
1 submodules
1 alu_core
=== alu_core ===
+----------Local Count, excluding submodules.
|
15 wires
28 wire bits
6 public wires
19 public wire bits
5 ports
14 port bits
14 cells
3 sky130_fd_sc_hd__maj3_1
1 sky130_fd_sc_hd__mux2_1
6 sky130_fd_sc_hd__xnor2_1
4 sky130_fd_sc_hd__xor2_1
=== design hierarchy ===
+----------Count including submodules.
|
50 top_wrapper
14 alu_core
+----------Count including submodules.
|
54 wires
88 wire bits
21 public wires
55 public wire bits
15 ports
33 port bits
- memories
- memory bits
- processes
50 cells
12 sky130_fd_sc_hd__dfxtp_1
3 sky130_fd_sc_hd__maj3_1
1 sky130_fd_sc_hd__mux2_1
12 sky130_fd_sc_hd__mux2i_1
12 sky130_fd_sc_hd__nor2_1
6 sky130_fd_sc_hd__xnor2_1
4 sky130_fd_sc_hd__xor2_1
1 submodules
1 alu_core
And, I could find my IC has…
| Metric | Value |
|---|---|
| Total Cells | 50 |
| Flip-flops | 12 |
| Muxes | 13 |
| XOR/XNOR | 10 |
And, there are No latches warning!
Finally, write an output as netlist
yosys> write_verilog -noattr synth.v
7. Executing Verilog backend.
7.1. Executing BMUXMAP pass.
7.2. Executing DEMUXMAP pass.
Dumping module `\alu_core'.
Dumping module `\top_wrapper'.
Then, generated ‘synth.v’ file.
Assignment 2: Place and Route¶
I used openroad for place and route. First, I wrote the following script for running in openroad.
# Read technology files
# Read technology files
read_lef /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
read_lef /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
read_liberty /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
# Read synthesized netlist (from Yosys)
read_verilog synth.v
link_design top_wrapper
# Read timing constraints
read_sdc constraints.sdc
# Initialize floorplan (core utilization, aspect ratio, core-to-die margin)
initialize_floorplan -die_area "0 0 200 200" -core_area "20 20 180 180" -site unithd
# Create power distribution network
source /Users/yosuke/.ciel/sky130A/libs.tech/librelane/sky130_fd_sc_hd/tracks.info
pdngen
# Place standard cells
global_placement
detailed_placement
# Clock tree synthesis
clock_tree_synthesis
# Route
global_route
detailed_route
# Write outputs
write_def adder-subtractor.def
write_verilog adder-subtractor.v
Also, I wrote constraints.sdc as follow:
# Define a 50 MHz clock (20 ns period) on the 'clk' input
create_clock -name clk -period 20 [get_ports clk]
# Input signals arrive 5 ns after clock edge
set_input_delay -clock clk 5 [all_inputs]
# Output signals must be valid 5 ns before next clock edge
set_output_delay -clock clk 5 [all_outputs]
# Reset is asynchronous - don't check timing on it
set_false_path -from [get_ports rst]
# Account for clock jitter/skew
set_clock_uncertainty 0.5 [get_clocks clk]
Then, run the script with openroad. But, I have a error.... still fixing it.
(base) yosuke@ysk-M1Pro synthesis % /Users/yosuke/FabFutures/ME/src/install/OpenROAD/bin/openroad run_openroad.tcl
OpenROAD bazel-nostamp
Features included (+) or not (-): -GPU +GUI -Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0227] LEF file: /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef, created 14 layers, 25 vias
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef at line 2.
[INFO ODB-0227] LEF file: /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells
[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.
[WARNING IFP-0028] Core area lower left (20.000, 20.000) snapped to (20.240, 21.760).
[INFO IFP-0001] Added 58 rows of 347 site unithd.
[INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 200.000 200.000 ) um
[INFO IFP-0101] Core BBox: ( 20.240 21.760 ) ( 179.860 179.520 ) um
[INFO IFP-0102] Core area: 25181.651 um^2
[INFO IFP-0103] Total instances area: 534.262 um^2
[INFO IFP-0104] Effective utilization: 0.021
[INFO IFP-0105] Number of instances: 50
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: ( 0.460 2.720 ) um
[INFO GPL-0004] CoreBBox: ( 20.240 21.760 ) ( 179.860 179.520 ) um
[INFO GPL-0036] Movable instances area: 534.262 um^2
[INFO GPL-0037] Total instances area: 534.262 um^2
[INFO GPL-0035] Pin density area adjust: 49.740 um^2
[ERROR GPL-0326] acc[0] toplevel port is not placed.
Error: run_openroad.tcl, 23 GPL-0326
I saw Þórarinn’s session 06 documentation. His documentation is very helpful. With thanks to him, I changed my openroad.tcl as follow.
set design_name adder_subtractor
set top_module top_wrapper
set netlist "synth.v"
set sdc_file "constraints.sdc"
set out_dir "openroad_out"
read_lef /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
read_lef /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
read_liberty /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog $netlist
link_design $top_module
#create_clock -name clk -period 20 [get_ports clk]
read_sdc $sdc_file
initialize_floorplan -die_area "0 0 50 50" -core_area "5 5 45 45" -site unithd
clock_tree_synthesis
make_tracks
place_pins \
-hor_layers met3 \
-ver_layers met2
global_placement
detailed_placement
global_route
detailed_route
write_def $out_dir/${design_name}.def
write_verilog $out_dir/${design_name}_a.v
report_design_area
report_checks
gui::show
exit
Then, run openroad again.
yosuke@ysk-M1Pro synthesis % /Users/yosuke/FabFutures/ME/src/install/OpenROAD/bin/openroad run_openroad.tcl
OpenROAD bazel-nostamp
Features included (+) or not (-): -GPU +GUI -Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0227] LEF file: /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef, created 14 layers, 25 vias
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef at line 2.
[INFO ODB-0227] LEF file: /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells
[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.
[WARNING IFP-0028] Core area lower left (5.000, 5.000) snapped to (5.060, 5.440).
[INFO IFP-0001] Added 14 rows of 86 site unithd.
[INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 50.000 50.000 ) um
[INFO IFP-0101] Core BBox: ( 5.060 5.440 ) ( 44.620 43.520 ) um
[INFO IFP-0102] Core area: 1506.445 um^2
[INFO IFP-0103] Total instances area: 534.262 um^2
[INFO IFP-0104] Effective utilization: 0.355
[INFO IFP-0105] Number of instances: 50
[WARNING CTS-0104] Clock wire resistance/capacitance values are zero.
Use set_wire_rc to set them.
[INFO CTS-0050] Root buffer is sky130_fd_sc_hd__clkbuf_1.
[INFO CTS-0051] Sink buffer is sky130_fd_sc_hd__clkbuf_1.
[INFO CTS-0052] The following clock buffers will be used for CTS:
sky130_fd_sc_hd__clkbuf_1
[INFO CTS-0049] Characterization buffer is sky130_fd_sc_hd__clkbuf_1.
[INFO CTS-0007] Net "clk" found for clock "clk".
[WARNING CTS-0041] Net "clk" has 0 sinks. Skipping...
[WARNING CTS-0083] No clock nets have been found.
[INFO CTS-0008] TritonCTS found 0 clock nets.
[WARNING CTS-0082] No valid clock nets in the design.
Found 0 macro blocks.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0001] Number of available slots 172
[INFO PPL-0002] Number of I/O 19
[INFO PPL-0003] Number of I/O w/sink 19
[INFO PPL-0004] Number of I/O w/o sink 0
[INFO PPL-0005] Slots per section 200
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 557.87 um.
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: ( 0.460 2.720 ) um
[INFO GPL-0004] CoreBBox: ( 5.060 5.440 ) ( 44.620 43.520 ) um
[INFO GPL-0036] Movable instances area: 534.262 um^2
[INFO GPL-0037] Total instances area: 534.262 um^2
[INFO GPL-0035] Pin density area adjust: 49.740 um^2
[INFO GPL-0032] ---- Initialize Region: Top-level
[INFO GPL-0006] Number of instances: 50
[INFO GPL-0007] Movable instances: 50
[INFO GPL-0008] Fixed instances: 0
[INFO GPL-0009] Dummy instances: 0
[INFO GPL-0010] Number of nets: 64
[INFO GPL-0011] Number of pins: 185
[INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 50.000 50.000 ) um
[INFO GPL-0013] Core BBox: ( 5.060 5.440 ) ( 44.620 43.520 ) um
[INFO GPL-0016] Core area: 1506.445 um^2
[INFO GPL-0014] Region name: top-level.
[INFO GPL-0015] Region area: 1506.445 um^2
[INFO GPL-0017] Fixed instances area: 0.000 um^2
[INFO GPL-0018] Movable instances area: 584.003 um^2
[INFO GPL-0019] Utilization: 38.767 %
[INFO GPL-0020] Standard cells area: 584.003 um^2
[INFO GPL-0021] Large instances area: 0.000 um^2
[INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
[INFO GPL-0051] Source of initial instance position counters:
Odb location = 0 Core center = 50 Region center = 0
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000010 HPWL: 890020
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000008 HPWL: 644205
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000009 HPWL: 648500
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000009 HPWL: 650506
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000007 HPWL: 651722
[INFO GPL-0033] ---- Initialize Nesterov Region: Top-level
[INFO GPL-0023] Placement target density: 0.7000
[INFO GPL-0024] Movable insts average area: 11.680 um^2
[INFO GPL-0025] Ideal bin area: 16.686 um^2
[INFO GPL-0026] Ideal bin count: 90
[INFO GPL-0027] Total bin area: 1506.445 um^2
[INFO GPL-0028] Bin count (X, Y): 8 , 8
[INFO GPL-0029] Bin size (W * H): 4.945 * 4.760 um
[INFO GPL-0030] Number of bins: 64
[INFO GPL-0007] ---- Execute Nesterov Global Placement.
[INFO GPL-0031] HPWL: Half-Perimeter Wirelength
Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group
---------------------------------------------------------------
0 | 0.8164 | 3.352760e+02 | +0.00% | 5.28e-14 |
10 | 0.8304 | 3.395260e+02 | +1.27% | 8.59e-14 |
20 | 0.8302 | 3.391760e+02 | -0.10% | 1.40e-13 |
30 | 0.8301 | 3.391350e+02 | -0.01% | 2.28e-13 |
40 | 0.8301 | 3.391290e+02 | -0.00% | 3.71e-13 |
50 | 0.8301 | 3.390990e+02 | -0.01% | 6.05e-13 |
60 | 0.8301 | 3.390920e+02 | -0.00% | 9.85e-13 |
70 | 0.8301 | 3.391120e+02 | +0.01% | 1.61e-12 |
80 | 0.8300 | 3.391330e+02 | +0.01% | 2.61e-12 |
90 | 0.8300 | 3.392210e+02 | +0.03% | 4.26e-12 |
100 | 0.8297 | 3.395810e+02 | +0.11% | 6.94e-12 |
110 | 0.8289 | 3.404010e+02 | +0.24% | 1.13e-11 |
120 | 0.8280 | 3.410270e+02 | +0.18% | 1.84e-11 |
130 | 0.8268 | 3.412250e+02 | +0.06% | 3.00e-11 |
140 | 0.8254 | 3.404930e+02 | -0.21% | 4.88e-11 |
150 | 0.8225 | 3.407670e+02 | +0.08% | 7.96e-11 |
160 | 0.8164 | 3.437020e+02 | +0.86% | 1.30e-10 |
170 | 0.8069 | 3.480550e+02 | +1.27% | 2.11e-10 |
180 | 0.7954 | 3.592600e+02 | +3.22% | 3.44e-10 |
190 | 0.7840 | 3.768330e+02 | +4.89% | 5.60e-10 |
200 | 0.7719 | 4.032340e+02 | +7.01% | 9.12e-10 |
210 | 0.7423 | 4.349950e+02 | +7.88% | 1.49e-09 |
220 | 0.6941 | 4.609550e+02 | +5.97% | 2.42e-09 |
230 | 0.6492 | 4.911330e+02 | +6.55% | 3.94e-09 |
240 | 0.6073 | 5.276460e+02 | +7.43% | 6.42e-09 |
250 | 0.5568 | 5.601830e+02 | +6.17% | 1.05e-08 |
260 | 0.5023 | 5.923610e+02 | +5.74% | 1.70e-08 |
270 | 0.4452 | 6.157530e+02 | +3.95% | 2.78e-08 |
280 | 0.3883 | 6.457900e+02 | +4.88% | 4.52e-08 |
290 | 0.3363 | 6.750890e+02 | +4.54% | 7.29e-08 |
300 | 0.2931 | 6.859740e+02 | +1.61% | 1.07e-07 |
310 | 0.2445 | 6.967870e+02 | +1.58% | 1.58e-07 |
320 | 0.2064 | 7.120020e+02 | +2.18% | 2.33e-07 |
330 | 0.1584 | 7.269070e+02 | +2.09% | 3.43e-07 |
340 | 0.1200 | 7.367860e+02 | +1.36% | 5.06e-07 |
348 | 0.0991 | 7.460570e+02 | | 7.17e-07 |
---------------------------------------------------------------
[INFO GPL-1001] Global placement finished at iteration 348
[INFO GPL-1002] Placed Cell Area 584.0029
[INFO GPL-1003] Available Free Area 1506.4448
[INFO GPL-1004] Minimum Feasible Density 0.3900 (cell_area / free_area)
[INFO GPL-1006] Suggested Target Densities:
[INFO GPL-1007] - For 90% usage of free space: 0.4307
[INFO GPL-1008] - For 80% usage of free space: 0.4846
[INFO GPL-1009] - For 50% usage of free space: 0.7753
[INFO GPL-1014] Final placement area: 584.00 (+0.00%)
Placement Analysis
---------------------------------
total displacement 109.1 u
average displacement 2.2 u
max displacement 6.7 u
original HPWL 744.5 u
legalized HPWL 842.5 u
delta HPWL 13 %
[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
Units: 1000
Number of layers: 13
Number of macros: 437
Number of vias: 25
Number of viarulegen: 25
[INFO DRT-0150] Reading design.
Design: top_wrapper
Die area: ( 0 0 ) ( 50000 50000 )
Number of track patterns: 12
Number of DEF vias: 0
Number of components: 50
Number of terminals: 19
Number of snets: 0
Number of nets: 64
[INFO DRT-0167] List of default vias:
Layer via
default via: M1M2_PR
Layer via2
default via: M2M3_PR
Layer via3
default via: M3M4_PR
Layer via4
default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
[INFO DRT-0164] Number of unique instances = 13.
[INFO DRT-0168] Init region query.
[INFO DRT-0024] Complete FR_MASTERSLICE.
[INFO DRT-0024] Complete licon.
[INFO DRT-0024] Complete li1.
[INFO DRT-0024] Complete mcon.
[INFO DRT-0024] Complete met1.
[INFO DRT-0024] Complete via.
[INFO DRT-0024] Complete met2.
[INFO DRT-0024] Complete via2.
[INFO DRT-0024] Complete met3.
[INFO DRT-0024] Complete via3.
[INFO DRT-0024] Complete met4.
[INFO DRT-0024] Complete via4.
[INFO DRT-0024] Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] licon shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 1647.
[INFO DRT-0033] mcon shape region query size = 0.
[INFO DRT-0033] met1 shape region query size = 196.
[INFO DRT-0033] via shape region query size = 0.
[INFO DRT-0033] met2 shape region query size = 19.
[INFO DRT-0033] via2 shape region query size = 0.
[INFO DRT-0033] met3 shape region query size = 0.
[INFO DRT-0033] via3 shape region query size = 0.
[INFO DRT-0033] met4 shape region query size = 0.
[INFO DRT-0033] via4 shape region query size = 0.
[INFO DRT-0033] met5 shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0078] Complete 96 pins.
[INFO DRT-0081] Complete 13 unique inst patterns.
[INFO DRT-0084] Complete 35 groups.
#scanned instances = 50
#unique instances = 13
#stdCellGenAp = 283
#stdCellValidPlanarAp = 0
#stdCellValidViaAp = 215
#stdCellPinNoAp = 0
#stdCellPinCnt = 166
#instTermValidViaApCnt = 0
#macroGenAp = 0
#macroValidPlanarAp = 0
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:03, memory = 233.28 (MB), peak = 233.28 (MB)
[INFO DRT-0157] Number of guides: 381
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 7 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 7 STEP 6900 ;
[INFO DRT-0028] Complete FR_MASTERSLICE.
[INFO DRT-0028] Complete licon.
[INFO DRT-0028] Complete li1.
[INFO DRT-0028] Complete mcon.
[INFO DRT-0028] Complete met1.
[INFO DRT-0028] Complete via.
[INFO DRT-0028] Complete met2.
[INFO DRT-0028] Complete via2.
[INFO DRT-0028] Complete met3.
[INFO DRT-0028] Complete via3.
[INFO DRT-0028] Complete met4.
[INFO DRT-0028] Complete via4.
[INFO DRT-0028] Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035] Complete FR_MASTERSLICE (guide).
[INFO DRT-0035] Complete licon (guide).
[INFO DRT-0035] Complete li1 (guide).
[INFO DRT-0035] Complete mcon (guide).
[INFO DRT-0035] Complete met1 (guide).
[INFO DRT-0035] Complete via (guide).
[INFO DRT-0035] Complete met2 (guide).
[INFO DRT-0035] Complete via2 (guide).
[INFO DRT-0035] Complete met3 (guide).
[INFO DRT-0035] Complete via3 (guide).
[INFO DRT-0035] Complete met4 (guide).
[INFO DRT-0035] Complete via4 (guide).
[INFO DRT-0035] Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] licon guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 132.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 103.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 58.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 0.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 0.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 233.45 (MB), peak = 233.45 (MB)
[INFO DRT-0245] skipped writing guide updates to database.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 190 vertical wires in 1 frboxes and 103 horizontal wires in 1 frboxes.
[INFO DRT-0186] Done with 15 vertical wires in 1 frboxes and 22 horizontal wires in 1 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 233.86 (MB), peak = 233.86 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 233.86 (MB), peak = 233.86 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 246.89 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 270.92 (MB), peak = 507.66 (MB)
Total wire length = 971 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 473 um.
Total wire length on LAYER met2 = 498 um.
Total wire length on LAYER met3 = 0 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 325.
Up-via summary (total 325):
----------------------
FR_MASTERSLICE 0
li1 167
met1 158
met2 0
met3 0
met4 0
----------------------
325
[WARNING DRT-0290] Warning: no DRC report specified, skipped writing DRC report
[INFO DRT-0198] Complete detail routing.
Total wire length = 971 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 473 um.
Total wire length on LAYER met2 = 498 um.
Total wire length on LAYER met3 = 0 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 325.
Up-via summary (total 325):
----------------------
FR_MASTERSLICE 0
li1 167
met1 158
met2 0
met3 0
met4 0
----------------------
325
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 269.98 (MB), peak = 507.66 (MB)
[INFO DRT-0180] Post processing.
Design area 534 um^2 35% utilization.
Startpoint: sub (input port clocked by clk)
Endpoint: carry_out (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
5.00 5.00 v input external delay
0.00 5.00 v sub (in)
0.30 5.30 v u_core/_13_/X (sky130_fd_sc_hd__mux2_1)
0.39 5.69 v u_core/_15_/X (sky130_fd_sc_hd__maj3_1)
0.39 6.08 v u_core/_16_/X (sky130_fd_sc_hd__maj3_1)
0.33 6.41 v u_core/_18_/X (sky130_fd_sc_hd__maj3_1)
0.00 6.41 v carry_out (out)
6.41 data arrival time
20.00 20.00 clock clk (rise edge)
0.00 20.00 clock network delay (ideal)
-0.50 19.50 clock uncertainty
0.00 19.50 clock reconvergence pessimism
-5.00 14.50 output external delay
14.50 data required time
---------------------------------------------------------
14.50 data required time
-6.41 data arrival time
---------------------------------------------------------
8.09 slack (MET)
Then, I could see Place and Route of my IC design on OpenRoad GUI. This is very nice!
And,,, as Þórarinn mentioned, my dsign also don’t have a power grid. So, with following his document, I modified openroad script as follow.
set design_name adder_subtractor
set top_module top_wrapper
set netlist "synth.v"
set sdc_file "constraints.sdc"
set out_dir "openroad_out"
read_lef /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef
read_lef /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef
read_liberty /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_verilog $netlist
link_design $top_module
#create_clock -name clk -period 20 [get_ports clk]
read_sdc $sdc_file
initialize_floorplan -die_area "0 0 200 200" -core_area "20 20 180 180" -site unithd
clock_tree_synthesis
tapcell -distance 13 -tapcell_master "sky130_fd_sc_hd__tapvpwrvgnd_1"
add_global_connection -net VPWR -pin_pattern {VPWR} -power
add_global_connection -net VGND -pin_pattern {VGND} -ground
set_voltage_domain -power VPWR -ground VGND
define_pdn_grid -name "stdcell_grid" -starts_with POWER
add_pdn_stripe -grid "stdcell_grid" -layer "met1" -width 0.48 -pitch 5.44 -offset 0 -extend_to_core_ring
add_pdn_stripe -grid "stdcell_grid" -layer "met4" -width 1.6 -pitch 27.0 -offset 13.5 -extend_to_core_ring
add_pdn_connect -grid "stdcell_grid" -layers {met1 met4}
pdngen
add_pdn_stripe -grid "stdcell_grid" -layer "met4" -width 1.6 -pitch 27.0 -offset 13.5 -extend_to_core_ring
add_pdn_ring -grid "stdcell_grid" -layers {met4 met5} \
-widths {2.0 2.0} \
-spacings {1.7 1.7} \
-core_offsets {2.0 2.0} \
-add_connect
pdngen
make_tracks
place_pins \
-hor_layers met3 \
-ver_layers met2
global_placement
detailed_placement
global_route
detailed_route
write_def $out_dir/${design_name}.def
write_verilog $out_dir/${design_name}_a.v
report_design_area
report_checks
gui::show
exit
Then, run again openroad.
yosuke@ysk-M1Pro synthesis % /Users/yosuke/FabFutures/ME/src/install/OpenROAD/bin/openroad run_openroad-2.tcl
OpenROAD bazel-nostamp
Features included (+) or not (-): -GPU +GUI -Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0227] LEF file: /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef, created 14 layers, 25 vias
[WARNING ODB-0220] WARNING (LEFPARS-2008): NOWIREEXTENSIONATPIN statement is obsolete in version 5.6 or later.
The NOWIREEXTENSIONATPIN statement will be ignored. See file /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef at line 2.
[INFO ODB-0227] LEF file: /Users/yosuke/.ciel/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef, created 437 library cells
[WARNING STA-0441] set_input_delay relative to a clock defined on the same port/pin not allowed.
[WARNING IFP-0028] Core area lower left (10.000, 10.000) snapped to (10.120, 10.880).
[INFO IFP-0001] Added 18 rows of 108 site unithd.
[INFO IFP-0100] Die BBox: ( 0.000 0.000 ) ( 70.000 70.000 ) um
[INFO IFP-0101] Core BBox: ( 10.120 10.880 ) ( 59.800 59.840 ) um
[INFO IFP-0102] Core area: 2432.333 um^2
[INFO IFP-0103] Total instances area: 534.262 um^2
[INFO IFP-0104] Effective utilization: 0.220
[INFO IFP-0105] Number of instances: 50
[WARNING CTS-0104] Clock wire resistance/capacitance values are zero.
Use set_wire_rc to set them.
[INFO CTS-0050] Root buffer is sky130_fd_sc_hd__clkbuf_1.
[INFO CTS-0051] Sink buffer is sky130_fd_sc_hd__clkbuf_1.
[INFO CTS-0052] The following clock buffers will be used for CTS:
sky130_fd_sc_hd__clkbuf_1
[INFO CTS-0049] Characterization buffer is sky130_fd_sc_hd__clkbuf_1.
[INFO CTS-0007] Net "clk" found for clock "clk".
[WARNING CTS-0041] Net "clk" has 0 sinks. Skipping...
[WARNING CTS-0083] No clock nets have been found.
[INFO CTS-0008] TritonCTS found 0 clock nets.
[WARNING CTS-0082] No valid clock nets in the design.
[INFO TAP-0005] Inserted 30 tapcells.
[INFO PDN-0001] Inserting grid: stdcell_grid
[WARNING PDN-0200] Removing floating shape: VGND (36.3200, 13.3600) - (37.9200, 57.3600) on met4
[WARNING PDN-0213] No shapes were created for net VGND.
[INFO PDN-0001] Inserting grid: stdcell_grid
Found 0 macro blocks.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0001] Number of available slots 244
[INFO PPL-0002] Number of I/O 19
[INFO PPL-0003] Number of I/O w/sink 19
[INFO PPL-0004] Number of I/O w/o sink 0
[INFO PPL-0005] Slots per section 200
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 747.99 um.
[INFO GPL-0001] ---- Initialize GPL Main Data Structures
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: ( 0.460 2.720 ) um
[INFO GPL-0004] CoreBBox: ( 10.120 10.880 ) ( 59.800 59.840 ) um
[INFO GPL-0036] Movable instances area: 534.262 um^2
[INFO GPL-0037] Total instances area: 571.798 um^2
[INFO GPL-0035] Pin density area adjust: 49.740 um^2
[INFO GPL-0032] ---- Initialize Region: Top-level
[INFO GPL-0006] Number of instances: 80
[INFO GPL-0007] Movable instances: 50
[INFO GPL-0008] Fixed instances: 30
[INFO GPL-0009] Dummy instances: 0
[INFO GPL-0010] Number of nets: 64
[INFO GPL-0011] Number of pins: 185
[INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 70.000 70.000 ) um
[INFO GPL-0013] Core BBox: ( 10.120 10.880 ) ( 59.800 59.840 ) um
[INFO GPL-0016] Core area: 2432.333 um^2
[INFO GPL-0014] Region name: top-level.
[INFO GPL-0015] Region area: 2432.333 um^2
[INFO GPL-0017] Fixed instances area: 37.536 um^2
[INFO GPL-0018] Movable instances area: 584.003 um^2
[INFO GPL-0019] Utilization: 24.386 %
[INFO GPL-0020] Standard cells area: 584.003 um^2
[INFO GPL-0021] Large instances area: 0.000 um^2
[INFO GPL-0005] ---- Execute Conjugate Gradient Initial Placement.
[INFO GPL-0051] Source of initial instance position counters:
Odb location = 0 Core center = 50 Region center = 0
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000009 HPWL: 2360620
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000007 HPWL: 738034
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000008 HPWL: 740812
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000011 HPWL: 741332
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000011 HPWL: 741499
[INFO GPL-0033] ---- Initialize Nesterov Region: Top-level
[INFO GPL-0023] Placement target density: 0.7000
[INFO GPL-0024] Movable insts average area: 11.680 um^2
[INFO GPL-0025] Ideal bin area: 16.686 um^2
[INFO GPL-0026] Ideal bin count: 145
[INFO GPL-0027] Total bin area: 2432.333 um^2
[INFO GPL-0028] Bin count (X, Y): 8 , 8
[INFO GPL-0029] Bin size (W * H): 6.210 * 6.120 um
[INFO GPL-0030] Number of bins: 64
[INFO GPL-0007] ---- Execute Nesterov Global Placement.
[INFO GPL-0031] HPWL: Half-Perimeter Wirelength
Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group
---------------------------------------------------------------
0 | 0.7873 | 4.479900e+02 | +0.00% | 7.24e-14 |
10 | 0.7957 | 4.523400e+02 | +0.97% | 1.18e-13 |
20 | 0.7961 | 4.522490e+02 | -0.02% | 1.92e-13 |
30 | 0.7958 | 4.522240e+02 | -0.01% | 3.13e-13 |
40 | 0.7959 | 4.522380e+02 | +0.00% | 5.10e-13 |
50 | 0.7958 | 4.522330e+02 | -0.00% | 8.30e-13 |
60 | 0.7959 | 4.522270e+02 | -0.00% | 1.35e-12 |
70 | 0.7958 | 4.522220e+02 | -0.00% | 2.20e-12 |
80 | 0.7957 | 4.522170e+02 | -0.00% | 3.59e-12 |
90 | 0.7956 | 4.522160e+02 | -0.00% | 5.84e-12 |
100 | 0.7955 | 4.524120e+02 | +0.04% | 9.52e-12 |
110 | 0.7953 | 4.533880e+02 | +0.22% | 1.55e-11 |
120 | 0.7949 | 4.541760e+02 | +0.17% | 2.53e-11 |
130 | 0.7945 | 4.541010e+02 | -0.02% | 4.11e-11 |
140 | 0.7938 | 4.529110e+02 | -0.26% | 6.70e-11 |
150 | 0.7921 | 4.534810e+02 | +0.13% | 1.09e-10 |
160 | 0.7887 | 4.550210e+02 | +0.34% | 1.78e-10 |
170 | 0.7812 | 4.576310e+02 | +0.57% | 2.90e-10 |
180 | 0.7704 | 4.658380e+02 | +1.79% | 4.72e-10 |
190 | 0.7559 | 4.794850e+02 | +2.93% | 7.68e-10 |
200 | 0.7304 | 4.982990e+02 | +3.92% | 1.25e-09 |
210 | 0.7001 | 5.235120e+02 | +5.06% | 2.04e-09 |
220 | 0.6682 | 5.605420e+02 | +7.07% | 3.32e-09 |
230 | 0.6221 | 5.900800e+02 | +5.27% | 5.41e-09 |
240 | 0.5763 | 6.240640e+02 | +5.76% | 8.81e-09 |
250 | 0.5262 | 6.600810e+02 | +5.77% | 1.44e-08 |
260 | 0.4726 | 6.932170e+02 | +5.02% | 2.34e-08 |
270 | 0.4217 | 7.316130e+02 | +5.54% | 3.81e-08 |
280 | 0.3693 | 7.798950e+02 | +6.60% | 6.20e-08 |
290 | 0.3246 | 7.988340e+02 | +2.43% | 9.71e-08 |
300 | 0.2764 | 8.082660e+02 | +1.18% | 1.43e-07 |
310 | 0.2262 | 8.200610e+02 | +1.46% | 2.11e-07 |
320 | 0.1526 | 8.199180e+02 | -0.02% | 3.10e-07 |
330 | 0.1448 | 8.352740e+02 | +1.87% | 4.57e-07 |
340 | 0.1098 | 8.395540e+02 | +0.51% | 6.73e-07 |
342 | 0.0960 | 8.391200e+02 | | 7.56e-07 |
---------------------------------------------------------------
[INFO GPL-1001] Global placement finished at iteration 342
[INFO GPL-1002] Placed Cell Area 584.0029
[INFO GPL-1003] Available Free Area 2394.7968
[INFO GPL-1004] Minimum Feasible Density 0.2500 (cell_area / free_area)
[INFO GPL-1006] Suggested Target Densities:
[INFO GPL-1007] - For 90% usage of free space: 0.2710
[INFO GPL-1008] - For 80% usage of free space: 0.3048
[INFO GPL-1009] - For 50% usage of free space: 0.4877
[INFO GPL-1014] Final placement area: 584.00 (+0.00%)
Placement Analysis
---------------------------------
total displacement 137.8 u
average displacement 1.7 u
max displacement 6.7 u
original HPWL 841.4 u
legalized HPWL 972.2 u
delta HPWL 16 %
[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
Units: 1000
Number of layers: 13
Number of macros: 437
Number of vias: 33
Number of viarulegen: 25
[INFO DRT-0150] Reading design.
Design: top_wrapper
Die area: ( 0 0 ) ( 70000 70000 )
Number of track patterns: 12
Number of DEF vias: 0
Number of components: 80
Number of terminals: 19
Number of snets: 2
Number of nets: 64
[INFO DRT-0167] List of default vias:
Layer via
default via: M1M2_PR
Layer via2
default via: M2M3_PR
Layer via3
default via: M3M4_PR
Layer via4
default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
[INFO DRT-0164] Number of unique instances = 14.
[INFO DRT-0168] Init region query.
[INFO DRT-0024] Complete FR_MASTERSLICE.
[INFO DRT-0024] Complete licon.
[INFO DRT-0024] Complete li1.
[INFO DRT-0024] Complete mcon.
[INFO DRT-0024] Complete met1.
[INFO DRT-0024] Complete via.
[INFO DRT-0024] Complete met2.
[INFO DRT-0024] Complete via2.
[INFO DRT-0024] Complete met3.
[INFO DRT-0024] Complete via3.
[INFO DRT-0024] Complete met4.
[INFO DRT-0024] Complete via4.
[INFO DRT-0024] Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] licon shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 1767.
[INFO DRT-0033] mcon shape region query size = 0.
[INFO DRT-0033] met1 shape region query size = 352.
[INFO DRT-0033] via shape region query size = 373.
[INFO DRT-0033] met2 shape region query size = 182.
[INFO DRT-0033] via2 shape region query size = 306.
[INFO DRT-0033] met3 shape region query size = 201.
[INFO DRT-0033] via3 shape region query size = 306.
[INFO DRT-0033] met4 shape region query size = 90.
[INFO DRT-0033] via4 shape region query size = 14.
[INFO DRT-0033] met5 shape region query size = 18.
[INFO DRT-0165] Start pin access.
[INFO DRT-0078] Complete 92 pins.
[INFO DRT-0081] Complete 14 unique inst patterns.
[INFO DRT-0084] Complete 36 groups.
#scanned instances = 80
#unique instances = 14
#stdCellGenAp = 259
#stdCellValidPlanarAp = 0
#stdCellValidViaAp = 194
#stdCellPinNoAp = 0
#stdCellPinCnt = 166
#instTermValidViaApCnt = 0
#macroGenAp = 0
#macroValidPlanarAp = 0
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:03, memory = 236.31 (MB), peak = 236.31 (MB)
[INFO DRT-0157] Number of guides: 334
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 10 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 10 STEP 6900 ;
[INFO DRT-0028] Complete FR_MASTERSLICE.
[INFO DRT-0028] Complete licon.
[INFO DRT-0028] Complete li1.
[INFO DRT-0028] Complete mcon.
[INFO DRT-0028] Complete met1.
[INFO DRT-0028] Complete via.
[INFO DRT-0028] Complete met2.
[INFO DRT-0028] Complete via2.
[INFO DRT-0028] Complete met3.
[INFO DRT-0028] Complete via3.
[INFO DRT-0028] Complete met4.
[INFO DRT-0028] Complete via4.
[INFO DRT-0028] Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035] Complete FR_MASTERSLICE (guide).
[INFO DRT-0035] Complete licon (guide).
[INFO DRT-0035] Complete li1 (guide).
[INFO DRT-0035] Complete mcon (guide).
[INFO DRT-0035] Complete met1 (guide).
[INFO DRT-0035] Complete via (guide).
[INFO DRT-0035] Complete met2 (guide).
[INFO DRT-0035] Complete via2 (guide).
[INFO DRT-0035] Complete met3 (guide).
[INFO DRT-0035] Complete via3 (guide).
[INFO DRT-0035] Complete met4 (guide).
[INFO DRT-0035] Complete via4 (guide).
[INFO DRT-0035] Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] licon guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 131.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 97.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 55.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 0.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 0.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 236.45 (MB), peak = 236.45 (MB)
[INFO DRT-0245] skipped writing guide updates to database.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 186 vertical wires in 1 frboxes and 97 horizontal wires in 1 frboxes.
[INFO DRT-0186] Done with 17 vertical wires in 1 frboxes and 26 horizontal wires in 1 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 237.06 (MB), peak = 237.06 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 237.06 (MB), peak = 237.06 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 245.77 (MB).
Completing 50% with 2 violations.
elapsed time = 00:00:00, memory = 250.17 (MB).
Completing 70% with 10 violations.
elapsed time = 00:00:00, memory = 250.70 (MB).
Completing 100% with 13 violations.
elapsed time = 00:00:00, memory = 251.72 (MB).
[INFO DRT-0199] Number of violations = 21.
Viol/Layer met1 met2
Metal Spacing 5 0
Recheck 7 1
Short 8 0
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 272.92 (MB), peak = 509.12 (MB)
Total wire length = 1123 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 479 um.
Total wire length on LAYER met2 = 644 um.
Total wire length on LAYER met3 = 0 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 317.
Up-via summary (total 317):
----------------------
FR_MASTERSLICE 0
li1 168
met1 149
met2 0
met3 0
met4 0
----------------------
317
[INFO DRT-0195] Start 1st optimization iteration.
Completing 20% with 21 violations.
elapsed time = 00:00:00, memory = 272.95 (MB).
Completing 50% with 21 violations.
elapsed time = 00:00:00, memory = 273.06 (MB).
Completing 70% with 19 violations.
elapsed time = 00:00:00, memory = 273.09 (MB).
Completing 100% with 1 violations.
elapsed time = 00:00:00, memory = 277.14 (MB).
[INFO DRT-0199] Number of violations = 1.
Viol/Layer met1
Short 1
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 292.34 (MB), peak = 530.09 (MB)
Total wire length = 1100 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 452 um.
Total wire length on LAYER met2 = 647 um.
Total wire length on LAYER met3 = 0 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 319.
Up-via summary (total 319):
----------------------
FR_MASTERSLICE 0
li1 168
met1 151
met2 0
met3 0
met4 0
----------------------
319
[INFO DRT-0195] Start 2nd optimization iteration.
Completing 10% with 1 violations.
elapsed time = 00:00:00, memory = 292.34 (MB).
Completing 20% with 1 violations.
elapsed time = 00:00:00, memory = 292.34 (MB).
Completing 30% with 1 violations.
elapsed time = 00:00:00, memory = 292.34 (MB).
Completing 40% with 1 violations.
elapsed time = 00:00:00, memory = 292.34 (MB).
Completing 50% with 1 violations.
elapsed time = 00:00:00, memory = 292.34 (MB).
Completing 60% with 1 violations.
elapsed time = 00:00:00, memory = 292.34 (MB).
Completing 70% with 1 violations.
elapsed time = 00:00:00, memory = 292.34 (MB).
Completing 80% with 1 violations.
elapsed time = 00:00:00, memory = 292.34 (MB).
Completing 100% with 3 violations.
elapsed time = 00:00:00, memory = 301.81 (MB).
[INFO DRT-0199] Number of violations = 3.
Viol/Layer met1 met2
Metal Spacing 2 0
Short 0 1
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 308.83 (MB), peak = 545.55 (MB)
Total wire length = 1100 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 457 um.
Total wire length on LAYER met2 = 643 um.
Total wire length on LAYER met3 = 0 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 319.
Up-via summary (total 319):
----------------------
FR_MASTERSLICE 0
li1 168
met1 151
met2 0
met3 0
met4 0
----------------------
319
[INFO DRT-0195] Start 3rd guides tiles iteration.
Completing 30% with 3 violations.
elapsed time = 00:00:00, memory = 309.02 (MB).
Completing 60% with 3 violations.
elapsed time = 00:00:00, memory = 309.50 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 309.50 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 315.47 (MB), peak = 550.81 (MB)
Total wire length = 1103 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 457 um.
Total wire length on LAYER met2 = 641 um.
Total wire length on LAYER met3 = 4 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 321.
Up-via summary (total 321):
----------------------
FR_MASTERSLICE 0
li1 168
met1 151
met2 2
met3 0
met4 0
----------------------
321
[WARNING DRT-0290] Warning: no DRC report specified, skipped writing DRC report
[INFO DRT-0198] Complete detail routing.
Total wire length = 1103 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 457 um.
Total wire length on LAYER met2 = 641 um.
Total wire length on LAYER met3 = 4 um.
Total wire length on LAYER met4 = 0 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 321.
Up-via summary (total 321):
----------------------
FR_MASTERSLICE 0
li1 168
met1 151
met2 2
met3 0
met4 0
----------------------
321
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 315.47 (MB), peak = 550.81 (MB)
[INFO DRT-0180] Post processing.
Design area 572 um^2 24% utilization.
Startpoint: sub (input port clocked by clk)
Endpoint: carry_out (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
5.00 5.00 v input external delay
0.00 5.00 v sub (in)
0.30 5.30 v u_core/_13_/X (sky130_fd_sc_hd__mux2_1)
0.39 5.69 v u_core/_15_/X (sky130_fd_sc_hd__maj3_1)
0.39 6.08 v u_core/_16_/X (sky130_fd_sc_hd__maj3_1)
0.33 6.41 v u_core/_18_/X (sky130_fd_sc_hd__maj3_1)
0.00 6.41 v carry_out (out)
6.41 data arrival time
20.00 20.00 clock clk (rise edge)
0.00 20.00 clock network delay (ideal)
-0.50 19.50 clock uncertainty
0.00 19.50 clock reconvergence pessimism
-5.00 14.50 output external delay
14.50 data required time
---------------------------------------------------------
14.50 data required time
-6.41 data arrival time
---------------------------------------------------------
8.09 slack (MET)
And, I could see the power line.
Assignment 3: Timing Report¶
I checked the report of openroad.
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
5.00 5.00 v input external delay
0.00 5.00 v sub (in)
0.30 5.30 v u_core/_13_/X (sky130_fd_sc_hd__mux2_1)
0.39 5.69 v u_core/_15_/X (sky130_fd_sc_hd__maj3_1)
0.39 6.08 v u_core/_16_/X (sky130_fd_sc_hd__maj3_1)
0.33 6.41 v u_core/_18_/X (sky130_fd_sc_hd__maj3_1)
0.00 6.41 v carry_out (out)
6.41 data arrival time
20.00 20.00 clock clk (rise edge)
0.00 20.00 clock network delay (ideal)
-0.50 19.50 clock uncertainty
0.00 19.50 clock reconvergence pessimism
-5.00 14.50 output external delay
14.50 data required time
---------------------------------------------------------
14.50 data required time
-6.41 data arrival time
---------------------------------------------------------
8.09 slack (MET)
From the report, I got…
- Data arrival time: 6.41 ns
- Data required time: 14.50 un
- Slack: 8.09 (MET)
Slack is positive.
Assignment 4: Generate GDS.¶
Because Klayout in my macos works strenge, I run this command on the class VM.
After running openroad script, we could get the .def file and verilog file of place and route of IC design.
/foss/designs/openroad_out > ls -la
total 268
drwxr-xr-x 2 designer designers 4096 Mar 11 16:52 .
drwxr-xr-x 4 designer designers 4096 Mar 11 16:52 ..
-rw-r--r-- 1 designer designers 7019 Mar 11 16:52 adder_subtractor_a.v
-rw-r--r-- 1 designer designers 70415 Mar 11 16:52 adder_subtractor.def
/foss/designs/openroad_out >
Then, with following Þórarinn’s documentation, I run this command.
strm2gds adder_subtractor.def adder_subtractor.gds \ --lefdef-lef-layouts /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.merged.lef,/foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
Generated .gds file, then, I run klayout.
klayout adder_subtractor.gds
Then, my IC design physical layout has come… I was deeply moved to see this.
