Lecture #4 Notes:Layout & Fabrication¶
I decided to split this information from this week into two different pages:
- Notes from the lecture.
- Assignment.
It was getting confusine.
Missed Class What is a cell? Cell is a layer of a chip How are layers and cells related? Is it fabricatable? Design Rules What is M1? Sky 130 is a pdk? Sky 130 -> 130 nm is the representation of size Layout vs schematic checking FOundary develops the PDKs (Process Development Kits) Bare die or packaged part
Homework¶
-
Block diagram: Sketch your project’s architecture showing major modules and data flow (e.g., Pocket Synth: button inputs → tone selector → oscillator → PWM output)
-
Explore a standard cell: Open the sky130 standard cell library in KLayout and find an inverter (sky130_fd_sc_hd__inv_1). Identify metal, poly, and diffusion layers.
- In the container:
- klayout /foss/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds Tip: Use Edit → Find (Ctrl+F) to search for “inv_1”
-
Connect the dots: Pick one block from your diagram — what standard cells might implement it? (e.g., “counter” needs flip-flops, “tone selector” needs muxes)
Block Diagram of Project’s Architecture¶
No clue how to proceed - block diagram verify Digital block run the test bench
Since I did not get a chance to attend the live lecture I needed to do something else. The plan: Read the documentation Layout & Fabrication
Capture what I learned
Watch video of Layout & Fabrication
Capture what I learned
Attempt the assignment
More than likely research
Try something, more than likely be wrong
Repeat
Let’s Go¶
DRC - Design Rule Checking - This is done to capture layout violations, bridging the gap between design and manufacturing
| Week 1-2 (Foundation): | Week 3-4 (Application): | |
|---|---|---|
| Electrons | → | Verilog HDL |
| ↓ | ↓ | |
| Transistors | → | Logic Gates |
| ↓ | ↓ | |
| CMOS Logic Gates | → | Synthesized Layout |
| ↓ | ↓ | |
| Layout & DRC | → | Your Working Chip |
(same gates!)
Yosys - A digital Logic synthesis tool, takes a hardware description and turns it into a gate level netlist Summarized by me using ChatGPT
This gave me my first clue to read a verilog file
netlist - text description of a circuit amongst it’s hardware. Common netlist types: RTL netlist, Gate-level netlist, transistor level
LVS - Layout Verses Schematic
Netlist Types and Typical Tools - Generated by ChatGPT¶
| Netlist type | What it represents | Common formats | Common software (create / read / use) |
|---|---|---|---|
| RTL netlist (behavioral) | Registers + combinational logic described at a high level | Verilog, SystemVerilog, VHDL | Create: any HDL editor • Sim/verify: Icarus Verilog (iverilog), Verilator, ModelSim/Questa, Xcelium, VCS • Synthesize: Yosys, Synopsys Design Compiler, Cadence Genus |
| Gate-level netlist (standard-cell) | Logic mapped to real library cells (NAND, DFF, etc.) | Verilog (structural), EDIF, JSON (tool-specific) | Create: Yosys+ABC, Design Compiler, Genus • Sim: iverilog, Verilator, ModelSim/Questa, Xcelium, VCS • P&R: OpenROAD, Cadence Innovus, Synopsys ICC2 • LVS reference: Calibre, Pegasus, Netgen |
| Transistor-level netlist | Individual devices (MOSFETs), R/C elements, sources | SPICE (*.sp), Spectre format | Create/edit: Xschem, Virtuoso Schematic • Sim: ngspice, Xyce, Spectre, HSPICE |
| Post-layout extracted netlist (PEX) | Transistor/cell netlist + extracted parasitics (R/C) from layout | SPICE + parasitic decks (often SPEF / SPICE-RC) | Extract: Magic, KLayout, Calibre xRC, StarRC, Quantus • Sim: ngspice, Spectre, HSPICE |
| Parasitic netlist / parasitic data | Interconnect parasitics for timing/power analysis | SPEF (common), DSPF, RSPF | Generate: OpenROAD, StarRC, Quantus, Calibre xRC • Use: STA tools (OpenSTA, PrimeTime, Tempus) |
| PCB netlist | Connectivity between schematic symbols and PCB footprints | KiCad netlist, EDIF, IPC-2581 (often), tool-specific | Create/use: KiCad, Altium Designer, OrCAD/Allegro, Eagle/Fusion Electronics |
| SPICE “subcircuit” library netlists | Reusable blocks/models (cells, IOs, analog macros) | SPICE .SUBCKT, Spectre libraries |
Use: ngspice, Spectre, HSPICE • Manage: PDKs / model libraries |
From Lecture
There are two fundamental flows for getting a circuit onto a chip:
| Analog Flow | Digital Flow | |
|---|---|---|
| Design Entry | Schematic (XScheme) | HDL code(Verilog) |
| Verification | Spice Simulation | Logic Simulation |
| Layout | Manual(or assisted) | Automated (P&R) |
| Typical Use | Amplifiers,ADCs,Sensors | Processors, controllers |
| What you control | Every Transistor | Achitecture and Timing |
HDL - Hardware Description Language - Used to describe digital Hardware cricuits HDL is to a chip what CAD is to a mechanical part
P&R - Place and Route
In order to understand the flow better, I used ChatGPT to create a table which matches the Digtil, Analog, to a mechanical DFM workflow. To this is extremely helpful.
‘Digital -> Analog -> Mechanical’ Design to Manufacturing Workflow¶
| Stage / Idea | Analog IC flow | Digital IC flow | Mechanical analog |
|---|---|---|---|
| Design entry | Transistor schematic (Xschem) | HDL/RTL code (Verilog/SystemVerilog) | CAD model + requirements (parts, assemblies) |
| Primary goal | Voltage/current performance (gain, noise, stability) | Correct logic + timing/power/area | Function + strength/stiffness/fit + cost |
| Main verification | SPICE (DC/AC/transient/noise, corners, Monte Carlo) | Logic sim + formal + STA (timing) | Hand calcs + FEA (static/fatigue/thermal) + tolerance stack |
| “Building blocks” | Transistors, caps, resistors, devices | Standard cells (NAND, flops, muxes) | Standard parts (fasteners, bearings) + features (holes, ribs, bosses) |
| “Layout / implementation” | Custom layout (manual/assisted) | Automated P&R (place & route) | CAD detailing + CAM/toolpaths + nesting; assembly layout |
| What you control most | Every device geometry + placement/matching/parasitics | Architecture, constraints, timing intent | Geometry, materials, interfaces, GD&T |
| Common checks before release | DRC/LVS + post-layout SPICE (PEX) | DRC/LVS + STA + power/IR/EM + sign-off | Interference checks + DFM/DFA + drawing review + inspection plan |
| Output artifact | GDSII layout + netlist | Gate-level netlist + GDSII | Drawings (GD&T), BOM, CAM files, inspection criteria |
| Typical use cases | Amps, PLLs, ADC/DAC front ends, sensors, IO | CPUs, controllers, accelerators, DSP | Mechanisms, fixtures, enclosures, frames, precision parts |
| Iteration driver | Parasitics/matching/noise margins | Timing closure, congestion, power | Test results, manufacturability, tolerances, cost |
| Automation level | Lower (expert-driven) | Higher (tool-driven) | Medium (parametric CAD/CAM + expert judgment) |
Folow to directions¶
In the docker and in the terminal xschem
Failed Attempt! It seems the path is incorrect.
Explore a standard Cell¶
Connect the dots¶
Resources:¶
- https://ngspice.sourceforge.io/osdi.html
- https://en.wikipedia.org/wiki/Verilog-A