Lecture #5 Notes:RTL Design and Verification¶

RTL -Register Transfer Level

Verilog 2005 is recommended due to the support

Flip flop: retentioner, made of two latches

Latches

Design in modules and heirachy: Clean clever abstracted way.

synchronous you needs a clock asynchronous you did not need a clock

combinational logic - no memory - Gate level Modeling

sequential logic: verfiy same time - require memory

non-blocking flip flop always

FSM: Finite State Machines

When do we do a testbench?

posedge for flip flop always

Heartbeat code and test https://github.com/siliconcompiler/siliconcompiler/blob/main/examples/heartbeat/heartbeat.v