Session 2: Analog Basics¶
Unfortunately I missed the lecture today due to having my own class to teach. However, I was able to catch the video and I have some experience with logic gates. I have even less experience with CMOS logic so I did learn a tremedous amount working through the assignments, watching the lecutre and reseaching on my own. I started out watching and doing some tutorials to get familar with the material, which I do not know if this was the best approach. Because I did the tutorials before watching the lecture I had a lot of questions. I was more attentive watching the lecture. Most of the questions I got answered, however some still go unanswered.
Homework¶
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Modify the AND gate netlist to create an OR gate instead
Hint: Swap the series/parallel arrangement of transistors
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Schmitt trigger analysis: Look up a CMOS Schmitt trigger schematic and identify which transistors set the upper vs lower threshold
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Optional: Build a simple circuit (LED + resistor + button) in TinkerCAD and observe current flow
Personal Goals¶
- Learn the basic flow of ngspice
- Gerenate a XOR gate
Approach¶
- Watch the video of class that I missed
- Run ngspce and.sp
- Complete simple tutorial -1
Documentation¶
Completing Tutorial 3 Circuit with Passive Elements, Operating Point¶
I ran and completed tutorial 3 where I wanted to understand the logic flow and sytanx of ngspice better. Although I did the tutorial I am still not understanding the connecting points or how the points are connecting for each element. I am trying to understand the image of the passive elements and how they map to the code. I understand the V1 is connected to ground by 0 and is give one volt. Heres where I get a little confused: The picture shows R1 connected to the + of V1, but I do not see this in code YET. Is it because it is just next line of code?
voltage divider netlist
V1 in 0 1
R1 in out 1k
R2 out 0 2k
.end
\n I completed #3 tutorial as shown above and still do not understand the full mapping of the image and the code.
Tutorial 4¶
I completed tutorial 4 with an insight. The connections on the image are labeled. “in” and “out” are labels. Now time to test if this is correct. so I modify the “in” to “on” to see if this is the case.\n - YES SUCCESS, now I have an understanding of a simple RC circuit schematic mapping to ngspice code. \n - OK, now I can picture the figure in my head as I read the code.\n
Documentation Learning¶
I was looking for a way to rename a batch set of screenshots in order to increase the speed of documenting workflow. I found a tool PowerToys which gives the ability to rename batch files quickly and in a intuitive GUI.
Creating the OR GATE¶
For me to understand how to implement the CMOS OR logic gate I decided to go old school and draw the OR gate with the advise from the instructor, Jennifer Volk. I put the pull-up network as series and the pull-down network in parallel. Then tested the gate with the truth table similar to the presentation. This turned out the be extremely valuable for understanding not only how the gate works, but also the behavior of the PMOS and NMOS became solidified in my brain.\n
\nFigure #1: My first and second attempt at creating an OR gate using PMOS and NMOS.\n
\nFigure #2: Shows the different types of states for the PMOS and CMOS MOSFETS\n
\nFigure# 3: The top image shows when both signals A and B are 0 then the output is also 0. The bottom images shows when A is low and B is high that output is high. I needed to keep in mind PMOS source is high and the NMOS source is low. Slighty confusing at first. The process of actually showing the closed and open MOSFET is informative to learn about the flow and states of the circuit. \n
\nFigure #4: The top image shows when A is high, B is low, output is high. The bottom show when A is high, B is high, and the output is high. For the last couple of images map to the OR gate.\n
\nFigure #5: Shows the start of mapping the OR gate to ngspice. Once I got through two of them I was able to complete the rest.\n
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Schmitt Trigger Identification/Analysis¶
Well I am first figuring out what is meant by identify the transistor set the high and the low threshold. My initial gues is the M5 and M6 for no reason. Now I need to research if this is correct or not.
- The source for the NMOS connects to low voltage
- The source for the PMOS connects to high voltage
Tinker CAD simulation check
M1 (NMOS) - Source /GND / - Gate /VG / - Drain / /
M2 (NMOS) - Source / / - Gate / / - Drain / /
M3 (NMOS) - Source / / - Gate / / - Drain / /
M4 (PMOS) - Source /VDD / - Gate /VG / - Drain / M5 Source /
M5 (PMOS) - Source /M4 Drain/ M6Source - Gate / VG / - Drain /Vo/M2 Drain/M6 Gate/M3 Gate
M6 (PMOS) - Source /M4 Drain/M6Source - Gate /M5 Drain/M3 Gate/Vo - Drain /GND /
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TinkerCAD¶
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Personal Project code and run an XOR Gate¶
In order to do this I need an invterted signal, don’t know how to do this in ngspice YET. I know how to convert a signal, but I need to finish documentation first and still understand which MOSFETS control the threshold in a Schmitt Cir
Documentation Learning¶
I was looking for a way to rename a batch set of screenshots in order to increase the speed of documenting workflow. I found a tool PowerToys which gives the ability to rename batch files quickly and in a intuitive GUI.
Lessons Learned¶
- Read CMOS Gate Logic
- Understand CMOS AND,OR Logic Gate
- Understand the basics of ngspice