Session #3: Schematic Design and Simulation¶
I learned many things in the lecture, thank you Jennifer.
Homework¶
- Reuse and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter) and change the models to refer to the PDK models
- Simulate it in SPICE, verify truth table (it will look something like the right table)
- measure propagation delays (low-to-high and high-to-low)
- Write an initial analog block that you can use in your chip project (e.g., an adder, counter, etc.)
Here’s a good starting point: https://analoghub.ie/category/verilogModels/article/counter
AND to an NAND in ngspice¶
Problems¶
Verify Truth Table for the NAND gate¶
In order to verify the NAND Truth table I turned to Falstad, under Neil’s and others’ recommendation. Falstad was very easy to learn and seems powerful for learning. I am not convinced of using the software for designing, due to the limitations BOM and other items. Hoever, using it was fun. I love to see the lights passing through the circuit when the circuit works the way it was intended.
Visualization of a NAND gate in Falstad¶
This below section was very satisifying to do
| A | B | NAND |
|---|---|---|
0 |
0 |
1 |
| A | B | NAND |
|---|---|---|
1 |
0 |
0 |
| A | B | NAND |
|---|---|---|
0 |
1 |
0 |
| A | B | NAND |
|---|---|---|
1 |
1 |
0 |
Verify the NAND Truth Table with Spice¶
Create a analog block: Adder, counter, etc..¶
!!! Note: “Don’t even know where to begin?” My initial thought, so I dug in. My first goal is figure out which commands to run to run the counter example provided to us.
Resources:¶
- https://ngspice.sourceforge.io/osdi.html
- https://en.wikipedia.org/wiki/Verilog-A