Session 3: Schematic Design & Simulation¶

My (funny) learnings for this week¶

How software guys see the invisible world¶

Clock is paramount. We (the software guys) are deeply concerned with time ticking. We know our code goes line by line, in a sequential way, as fast as the clock let us go, We have to share the time with others (process) Voltage is kind of a message we pass through the data pipe, current is how large the pipe is. A resistor is like a bandwith limiter. A capacitor looks like a buffer that triggers a callback when its time comes. A transistor is like an IF statement. Regarding performance, well, just give me a better computer and my code will be fine…

How analog circuits designers (and plumbers..) see the invisible world¶

Voltage is water pressure, current is flow rate, and resistance is pipe diameter. A pump represents the battery, while capacitors act as membranes and inductors as water wheels. While effective, the analogy breaks down because water flows at different speeds across a pipe’s diameter, whereas electrons behave differently, and water is not truly compressible like charge in a circuit, especially at high frequencies. Electromagnetic interference (EMI) and radio frequency interference (RFI) are a big concern.

How ASIC (and maybe FPGAs ?) designers see the invisible world¶

The clock is here again, everywhere. Everybody runs on the clock, simultaneously. Well, they have time to prepare (ramp-up) and to take some rest after (ramp-down). Speed, cost/duration of fabrication cycle and power budget are big concerns.

My (serious) learnings for this week¶

There are two ways for circuit modeling:

Structural Modeling: show how the structure is and how parts are connected¶

Like we do this week and like we did last week

Behavioural Modeling: describe what the circuit should do¶

Since I’m a software guy, it talks to me.. but I see big differences vs C code, mainly the fact that it does not run sequentialy

Useful links¶

Project homework:¶

Reuse and.sp netlist, which has a 2-input AND gate to make a 2-input NAND gate (e.g., remove the output inverter)¶

When both A and B are LOW, output is HIGH

When A is high and B is LOW, output is HIGH

When A is low and B is HIGH, output is HIGH

When both are HIGH, output is LOW

Change the models to refer to the PDK models¶

* NAND gate ngspice with PDK

* Include the Sky130 device models
.lib "/foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice" tt

* Power supply: 1.8V
Vdd vdd gnd 1.8

There are two inputs: A and B Feed each input with a pulse, with different periodicity to be able to create the 4 basic scenarios

* Inputs
* PULSE(initial final delay rise fall widht period)
VinA inA gnd PULSE(0 1.8 0ns 100ps 100ps 2ns 4ns)
VinB inB gnd PULSE(0 1.8 0ns 100ps 100ps 2ns 8ns)

I found out that sky130_fd_pr__pfet_01v8 does not work, or does not exist.. The _hvt one works fine, no idea what it is exactly

* Two PMOS transistors in parralel for the pull-up network  (W=1u, L=150n)
* Format: Mname drain gate source body model W=... L=...
Xp1 NAND inA vdd vdd sky130_fd_pr__pfet_01v8_hvt  l=0.150  w=0.99
Xp2 NAND inB vdd vdd sky130_fd_pr__pfet_01v8_hvt  l=0.150  w=0.99

* Two NMOS transistors in series for the pull-down network  (W=0.5u, L=150n)
Xn1 NAND inA npd gnd sky130_fd_pr__nfet_01v8  l=0.150  w=0.495
Xn2 npd  inB gnd gnd sky130_fd_pr__nfet_01v8  l=0.150  w=0.495

We need a capacitor at the end as a typical load

* Output load capacitor (typical gate load)
Cload NAND gnd 10f

* Simulation: transient analysis for 30ns
.tran 10p 30ns

* Save node voltages for plotting
.save v(inA) v(inB) v(NAND)

* Control block for ngspice
.control
run
plot v(inA) v(inB) v(NAND)
plot v(inA) v(NAND)
plot v(inB) v(NAND)
meas tran tpd_hl TRIG v(inA) VAL=0.9 RISE=1 TARG v(NAND) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(inA) VAL=0.9 FALL=1 TARG v(NAND) VAL=0.9 RISE=1
meas tran tpd_hl TRIG v(inB) VAL=0.9 RISE=1 TARG v(NAND) VAL=0.9 FALL=1
meas tran tpd_lh TRIG v(inB) VAL=0.9 FALL=1 TARG v(NAND) VAL=0.9 RISE=1

.endc

.end

Simulate it in SPICE, verify truth table¶

The A input: 2ns every 4 ns

The B input: 2ns every 8 ns

The output, corresponding to the truth table. OUT is HIGH only when both A and B are LOW

Measure propagation delays (low-to-high and high-to-low)¶

Write an initial analog block that you can use in your chip project (e.g., an adder, counter, etc.)¶

More to come…

BONUS: explore and learn Verilog using the code sample provided during class¶

Module declaration : module name, plus three parameters. We don’t know the type and direction at the moment

// Ideal voltage-controlled switch
`include "constants.vams"
`include "disciplines.vams"

module vcswitch(p, n, ctrl);

Port declarations: port type (default = bit) and direction (input, output or inout (bidirectionnal)

    inout p, n;
    input ctrl;

Data type declaration section: a list of nets (physical links) and variables (= temporary storage, implemented by registers or flip-flops).

In Verilog-AMS (Analog and Mixed-Signal) and Verilog-A, the electrical keyword is a conservative discipline used to define a net as an analog node that carries both potential (voltage) and flow (current) information

    electrical p, n, ctrl;

Parameters: from within the module, see them as constants. From outside, parameters can be overridden with new values during module instantiation, NOT after

    parameter real ron = 1;      // On resistance
    parameter real roff = 1e9;   // Off resistance
    parameter real vth = 0.5;    // Threshold

Analog begin keyword pair in Verilog-AMS (and Verilog-A) is used to define a procedural block containing behavioral descriptions of analog circuits

The block is executed continuously in a looping manner

<+ is a non blocking assignment symbol, i.e not blocking execution of the statement that follows. Here, the is just one statement (per if branch), so I guess it does not change anything

    analog begin
        if (V(ctrl) > vth)
            I(p, n) <+ V(p, n) / ron;
        else
            I(p, n) <+ V(p, n) / roff;
    end
endmodule

Simulation using OpenVAF

/foss/tools/openvaf/bin > openvaf /foss/designs/philippelibioulle/designs/week2session3/vcswitch.va 
Finished building vcswitch.va in 0.03s

An .osdi file is generated (binary format). OpenVAF generates shared objects that can be loaded by circuit simulators at run-time. To ensure compatibility with a wide variety of simulators SemiMod has developed a simulator independent interface called OSDI (Open Source Device Interface).

TODO: ok, we have a generic module here, but nothing specific and not net. How can we simulate anything ? TODO: read https://www.spiceopus.si/osdi.html